1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a55.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14 /* -------------------------------------------------- 15 * Errata Workaround for Cortex A55 Errata #768277. 16 * This applies only to revision r0p0 of Cortex A55. 17 * Inputs: 18 * x0: variant[4:7] and revision[0:3] of current cpu. 19 * Shall clobber: x0-x17 20 * -------------------------------------------------- 21 */ 22func errata_a55_768277_wa 23 /* 24 * Compare x0 against revision r0p0 25 */ 26 mov x17, x30 27 bl check_errata_768277 28 cbz x0, 1f 29 mrs x1, CORTEX_A55_CPUACTLR_EL1 30 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 31 msr CORTEX_A55_CPUACTLR_EL1, x1 32 isb 331: 34 ret x17 35endfunc errata_a55_768277_wa 36 37func check_errata_768277 38 mov x1, #0x00 39 b cpu_rev_var_ls 40endfunc check_errata_768277 41 42 /* ------------------------------------------------------------------ 43 * Errata Workaround for Cortex A55 Errata #778703. 44 * This applies only to revision r0p0 of Cortex A55 where L2 cache is 45 * not configured. 46 * Inputs: 47 * x0: variant[4:7] and revision[0:3] of current cpu. 48 * Shall clobber: x0-x17 49 * ------------------------------------------------------------------ 50 */ 51func errata_a55_778703_wa 52 /* 53 * Compare x0 against revision r0p0 and check that no private L2 cache 54 * is configured 55 */ 56 mov x17, x30 57 bl check_errata_778703 58 cbz x0, 1f 59 mrs x1, CORTEX_A55_CPUECTLR_EL1 60 orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL 61 msr CORTEX_A55_CPUECTLR_EL1, x1 62 mrs x1, CORTEX_A55_CPUACTLR_EL1 63 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING 64 msr CORTEX_A55_CPUACTLR_EL1, x1 65 isb 661: 67 ret x17 68endfunc errata_a55_778703_wa 69 70func check_errata_778703 71 mov x16, x30 72 mov x1, #0x00 73 bl cpu_rev_var_ls 74 /* 75 * Check that no private L2 cache is configured 76 */ 77 mrs x1, CORTEX_A55_CLIDR_EL1 78 and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3 79 cmp x1, #0 80 mov x2, #ERRATA_NOT_APPLIES 81 csel x0, x0, x2, eq 82 ret x16 83endfunc check_errata_778703 84 85 /* -------------------------------------------------- 86 * Errata Workaround for Cortex A55 Errata #798797. 87 * This applies only to revision r0p0 of Cortex A55. 88 * Inputs: 89 * x0: variant[4:7] and revision[0:3] of current cpu. 90 * Shall clobber: x0-x17 91 * -------------------------------------------------- 92 */ 93func errata_a55_798797_wa 94 /* 95 * Compare x0 against revision r0p0 96 */ 97 mov x17, x30 98 bl check_errata_798797 99 cbz x0, 1f 100 mrs x1, CORTEX_A55_CPUACTLR_EL1 101 orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 102 msr CORTEX_A55_CPUACTLR_EL1, x1 103 isb 1041: 105 ret x17 106endfunc errata_a55_798797_wa 107 108func check_errata_798797 109 mov x1, #0x00 110 b cpu_rev_var_ls 111endfunc check_errata_798797 112 113func cortex_a55_reset_func 114 mov x19, x30 115 116#if ERRATA_DSU_936184 117 bl errata_dsu_936184_wa 118#endif 119 120 bl cpu_get_rev_var 121 mov x18, x0 122 123#if ERRATA_A55_768277 124 mov x0, x18 125 bl errata_a55_768277_wa 126#endif 127 128#if ERRATA_A55_778703 129 mov x0, x18 130 bl errata_a55_778703_wa 131#endif 132 133#if ERRATA_A55_798797 134 mov x0, x18 135 bl errata_a55_798797_wa 136#endif 137 138 ret x19 139endfunc cortex_a55_reset_func 140 141 /* --------------------------------------------- 142 * HW will do the cache maintenance while powering down 143 * --------------------------------------------- 144 */ 145func cortex_a55_core_pwr_dwn 146 /* --------------------------------------------- 147 * Enable CPU power down bit in power control register 148 * --------------------------------------------- 149 */ 150 mrs x0, CORTEX_A55_CPUPWRCTLR_EL1 151 orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK 152 msr CORTEX_A55_CPUPWRCTLR_EL1, x0 153 isb 154 ret 155endfunc cortex_a55_core_pwr_dwn 156 157#if REPORT_ERRATA 158/* 159 * Errata printing function for Cortex A55. Must follow AAPCS & can use stack. 160 */ 161func cortex_a55_errata_report 162 stp x8, x30, [sp, #-16]! 163 bl cpu_get_rev_var 164 mov x8, x0 165 166 /* 167 * Report all errata. The revision variant information is at x8, where 168 * "report_errata" is expecting it and it doesn't corrupt it. 169 */ 170 report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184 171 report_errata ERRATA_A55_768277, cortex_a55, 768277 172 report_errata ERRATA_A55_778703, cortex_a55, 778703 173 report_errata ERRATA_A55_798797, cortex_a55, 798797 174 175 ldp x8, x30, [sp], #16 176 ret 177endfunc cortex_a55_errata_report 178#endif 179 180 /* --------------------------------------------- 181 * This function provides cortex_a55 specific 182 * register information for crash reporting. 183 * It needs to return with x6 pointing to 184 * a list of register names in ascii and 185 * x8 - x15 having values of registers to be 186 * reported. 187 * --------------------------------------------- 188 */ 189.section .rodata.cortex_a55_regs, "aS" 190cortex_a55_regs: /* The ascii list of register names to be reported */ 191 .asciz "cpuectlr_el1", "" 192 193func cortex_a55_cpu_reg_dump 194 adr x6, cortex_a55_regs 195 mrs x8, CORTEX_A55_CPUECTLR_EL1 196 ret 197endfunc cortex_a55_cpu_reg_dump 198 199declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ 200 cortex_a55_reset_func, \ 201 cortex_a55_core_pwr_dwn 202