docs: update usage of ARM_ARCH_MAJOR/MINOR

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I433488ecbaf7773a9e062223599fb0d3bc892f94

docs(spm): memory region nodes definition

Update the documentation related with memory region nodes
of SP's FF-A manifest, to relate to changes from patches [1].

[1] https://review.trustedfirmware.

docs(spm): memory region nodes definition

Update the documentation related with memory region nodes
of SP's FF-A manifest, to relate to changes from patches [1].

[1] https://review.trustedfirmware.org/q/topic:%22ja%252Fmem_region_fix%22+(status:open%20OR%20status:merged)

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I16595ec581b0ad9d2c20fca8dab64b6fd9ad001a

show more ...

docs: add Juno runtime instrumentation data

Add results from running the TFTF test suite Runtime Instrumentation on Juno.

Change-Id: I4c5b64e1a80b5b88e42835f0700294a02edc8032
Signed-off-by: Harriso

docs: add Juno runtime instrumentation data

Add results from running the TFTF test suite Runtime Instrumentation on Juno.

Change-Id: I4c5b64e1a80b5b88e42835f0700294a02edc8032
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

fix(doc): match boot-order size to implementation

Docs had boot-order field as being u32 but code uses uint16_t.
FF-A specification does not specify a required size.

Signed-off-by: Kathleen Capella

fix(doc): match boot-order size to implementation

Docs had boot-order field as being u32 but code uses uint16_t.
FF-A specification does not specify a required size.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: Ia4c3fc66b9e733ea1417d34c2601bce1f81c4d32

show more ...

Merge "docs(prerequisites): update software and libraries prerequisites" into integration

docs(prerequisites): update software and libraries prerequisites

Update to use the following software:

- mbed TLS == 3.4.0
- (DTC) >= 1.4.7
- Ubuntu 22.04 for builds.

Signed-off-by: Govindraj Raja

docs(prerequisites): update software and libraries prerequisites

Update to use the following software:

- mbed TLS == 3.4.0
- (DTC) >= 1.4.7
- Ubuntu 22.04 for builds.

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I384aab4dfee9cae9453eebf4091abe82ef9ccfaa

show more ...

feat(memmap): add topological memory view

Present memory usage in hierarchical view. This view maps modules to
their respective segments and sections.

Change-Id: I5c374b46738edbc83133441ff3f4268f08

feat(memmap): add topological memory view

Present memory usage in hierarchical view. This view maps modules to
their respective segments and sections.

Change-Id: I5c374b46738edbc83133441ff3f4268f08cb011d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

feat(memmap): add tabular memory use data

Add support for tabulating static memory consumption data from ELF
binaries. This relies on static symbols, defined in the linker files,
that provide inform

feat(memmap): add tabular memory use data

Add support for tabulating static memory consumption data from ELF
binaries. This relies on static symbols, defined in the linker files,
that provide information about the memory ranges.

Change-Id: Ie19cd2b80a7b591607640feeb84c63266963ea4d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

refactor: improve readability of symbol table

Make the symbol table produced by the memory mapping script more
readable. Add a generic interface for interacting with ELF binaries.
This interface ena

refactor: improve readability of symbol table

Make the symbol table produced by the memory mapping script more
readable. Add a generic interface for interacting with ELF binaries.
This interface enables us to get symbols that provide some insights into
TF-A's memory usage.

Change-Id: I6646f817a1d38d6184b837b78039b7465a533c5c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

docs: fix syntax error in note

Change-Id: Ibd4599c761641431e02778bd65c2696fb886a326
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

docs(spm): threat model for memory sharing functionality

Update the SPM threat model with information about FF-A v1.1
memory sharing functionality.

Change-Id: I65ea0d53aba8ac2f8432539968ceaab6be109

docs(spm): threat model for memory sharing functionality

Update the SPM threat model with information about FF-A v1.1
memory sharing functionality.

Change-Id: I65ea0d53aba8ac2f8432539968ceaab6be109ac8
Signed-off-by: J-Alves <joao.alves@arm.com>

show more ...

docs(spm): add memory sharing documentation

Add documentation that explains implementation specific
relevant information from the update done to FF-A v1.1
memory sharing in Hafnium.

Change-Id: Ifc3

docs(spm): add memory sharing documentation

Add documentation that explains implementation specific
relevant information from the update done to FF-A v1.1
memory sharing in Hafnium.

Change-Id: Ifc3c6b86c0545d53331207b017b990427ee84f2d
Signed-off-by: J-Alves <joao.alves@arm.com>

show more ...

docs(psci): expound runtime instrumentation docs

Change-Id: I3c30b44d4196c30fd07373282150e543959fce1a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

Merge "docs: update release and code freeze dates" into integration

Merge changes from topic "mp/feat_ras" into integration

* changes:
refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED
refactor(ras): replace RAS_EXTENSION with FEAT_RAS

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround platforms non-arm interconnect
refactor(errata_abi): factor in non-arm interconnect
feat(errata_abi): errata management firmware interface

show more ...

Merge changes from topic "bk/context_refactor" into integration

* changes:
fix(gicv3): restore scr_el3 after changing it
refactor(cm): make SVE and SME build dependencies logical

Merge "docs: update TZC secured DRAM map for FVP and Juno" into integration

Merge changes I06b35f11,If80573d6 into integration

* changes:
docs: remove plat_convert_pk() interface from release doc
chore(io): remove io_dummy driver

refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firm

refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firmware first
handling(FFH) of RAS errors.
2. Manage the FEAT_RAS extension when switching the worlds.

FFH means that all the EAs from NS are trapped in EL3 first and signaled
to NS world later after the first handling is done in firmware. There is
an alternate way of handling RAS errors viz Kernel First handling(KFH).
Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the
feature is needed for proper handling KFH in as well.

This patch breaks down the RAS_EXTENSION flag into a flag to denote the
CPU architecture `ENABLE_FEAT_RAS` which is used in context management
during world switch and another flag `RAS_FFH_SUPPORT` to pull in
required framework and platform hooks for FFH.

Proper support for KFH will be added in future patches.

BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The
equivalent functionality can be achieved by the following
2 options:
- ENABLE_FEAT_RAS
- RAS_FFH_SUPPORT

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec

show more ...

docs(build): update GCC to 12.2.Rel1 version

Updating toolchain to the latest production release version
12.2.Rel1 publicly available on https://developer.arm.com/

We build TF-A in CI using:
AArch3

docs(build): update GCC to 12.2.Rel1 version

Updating toolchain to the latest production release version
12.2.Rel1 publicly available on https://developer.arm.com/

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: Ib603cf7417e6878683a1100d5f55311188e36e8e
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

show more ...

docs: update TZC secured DRAM map for FVP and Juno

Updated the documentation to include missing details about the
TZC secured DRAM mapping for the FVP and Juno platforms.

Change-Id: I10e59b9f9686fa

docs: update TZC secured DRAM map for FVP and Juno

Updated the documentation to include missing details about the
TZC secured DRAM mapping for the FVP and Juno platforms.

Change-Id: I10e59b9f9686fa2fef97f89864ebc272b10e5c0b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

docs(errata_abi): document the errata abi changes

Updated errata ABI feature enable flag and the errata non-arm
interconnect based flag, the default values for when the
feature is not enabled.

Chan

docs(errata_abi): document the errata abi changes

Updated errata ABI feature enable flag and the errata non-arm
interconnect based flag, the default values for when the
feature is not enabled.

Change-Id: Ieb2144a1bc38f4ed684fda8280842a18964ba148
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

show more ...

fix(cpus): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on a

fix(cpus): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on arm/non-arm interconnect IP. The ABI helps assist the Kernel
in the process of mitigation for the following errata:

Cortex-A715: erratum 2701951
Neoverse V2: erratum 2719103
Cortex-A710: erratum 2701952
Cortex-X2: erratum 2701952
Neoverse N2: erratum 2728475
Neoverse V1: erratum 2701953
Cortex-A78: erratum 2712571
Cortex-A78AE: erratum 2712574
Cortex-A78C: erratum 2712575

EL3 provides an appropriate return value via errata ABI when the
kernel makes an SMC call using the EM_CPU_ERRATUM_FEATURES FID with the
appropriate erratum ID.

Change-Id: I35bd69d812dba37410dd8bc2bbde20d4955b0850
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

show more ...

docs: update release and code freeze dates

Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: If782bd337d10213cb74503f4ea54ed304d6e4c34