1 /* 2 * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include MBEDTLS_CONFIG_FILE 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 #include <plat/common/common_def.h> 20 21 #include "../juno_def.h" 22 #ifdef JUNO_ETHOSN_TZMP1 23 #include "../juno_ethosn_tzmp1_def.h" 24 #endif 25 26 /* Required platform porting definitions */ 27 /* Juno supports system power domain */ 28 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 29 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 30 JUNO_CLUSTER_COUNT + \ 31 PLATFORM_CORE_COUNT) 32 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 33 JUNO_CLUSTER1_CORE_COUNT) 34 35 /* Cryptocell HW Base address */ 36 #define PLAT_CRYPTOCELL_BASE UL(0x60050000) 37 38 /* 39 * Other platform porting definitions are provided by included headers 40 */ 41 42 /* 43 * Required ARM standard platform porting definitions 44 */ 45 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 46 47 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 48 49 /* Use the bypass address */ 50 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 51 BL1_ROM_BYPASS_OFFSET) 52 53 #define NSRAM_BASE UL(0x2e000000) 54 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 55 56 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 57 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 58 59 /* Range of kernel DTB load address */ 60 #define JUNO_DTB_DRAM_MAP_START ULL(0x82000000) 61 #define JUNO_DTB_DRAM_MAP_SIZE ULL(0x00008000) /* 32KB */ 62 63 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 64 JUNO_DTB_DRAM_MAP_START, \ 65 JUNO_DTB_DRAM_MAP_SIZE, \ 66 MT_MEMORY | MT_RO | MT_NS) 67 68 #ifdef JUNO_ETHOSN_TZMP1 69 #define JUNO_ETHOSN_PROT_FW_RW MAP_REGION_FLAT( \ 70 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 71 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE, \ 72 MT_MEMORY | MT_RW | MT_SECURE) 73 #endif 74 75 /* virtual address used by dynamic mem_protect for chunk_base */ 76 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 77 78 /* 79 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 80 */ 81 82 #if USE_ROMLIB 83 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 84 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 85 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) 86 #else 87 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 88 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 89 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) 90 #endif 91 92 /* 93 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 94 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 95 * flash 96 */ 97 98 #if TRUSTED_BOARD_BOOT 99 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 100 #else 101 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 102 #endif /* TRUSTED_BOARD_BOOT */ 103 104 /* 105 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 106 * plat_arm_mmap array defined for each BL stage. 107 */ 108 #ifdef IMAGE_BL1 109 # define PLAT_ARM_MMAP_ENTRIES 7 110 # define MAX_XLAT_TABLES 4 111 #endif 112 113 #ifdef IMAGE_BL2 114 #ifdef SPD_opteed 115 # define PLAT_ARM_MMAP_ENTRIES 13 116 # define MAX_XLAT_TABLES 5 117 #else 118 # define PLAT_ARM_MMAP_ENTRIES 11 119 # define MAX_XLAT_TABLES 5 120 #endif 121 #endif 122 123 #ifdef IMAGE_BL2U 124 # define PLAT_ARM_MMAP_ENTRIES 5 125 # define MAX_XLAT_TABLES 3 126 #endif 127 128 #ifdef IMAGE_BL31 129 # define PLAT_ARM_MMAP_ENTRIES 7 130 # define MAX_XLAT_TABLES 5 131 #endif 132 133 #ifdef IMAGE_BL32 134 # define PLAT_ARM_MMAP_ENTRIES 6 135 # define MAX_XLAT_TABLES 4 136 #endif 137 138 /* 139 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 140 * plus a little space for growth. 141 */ 142 #if TRUSTED_BOARD_BOOT 143 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 144 #else 145 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 146 #endif 147 148 /* 149 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 150 * little space for growth. 151 */ 152 #if TRUSTED_BOARD_BOOT 153 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 154 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 155 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 156 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 157 #else 158 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 159 #endif 160 #else 161 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 162 #endif 163 164 /* 165 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 166 * calculated using the current BL31 PROGBITS debug size plus the sizes of 167 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 168 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 169 */ 170 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 171 172 #if JUNO_AARCH32_EL3_RUNTIME 173 /* 174 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 175 * calculated using the current BL32 PROGBITS debug size plus the sizes of 176 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 177 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 178 */ 179 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000) 180 #endif 181 182 /* 183 * Size of cacheable stacks 184 */ 185 #if defined(IMAGE_BL1) 186 # if TRUSTED_BOARD_BOOT 187 # define PLATFORM_STACK_SIZE UL(0x1000) 188 # else 189 # define PLATFORM_STACK_SIZE UL(0x440) 190 # endif 191 #elif defined(IMAGE_BL2) 192 # if TRUSTED_BOARD_BOOT 193 # define PLATFORM_STACK_SIZE UL(0x1000) 194 # else 195 # define PLATFORM_STACK_SIZE UL(0x400) 196 # endif 197 #elif defined(IMAGE_BL2U) 198 # define PLATFORM_STACK_SIZE UL(0x400) 199 #elif defined(IMAGE_BL31) 200 # if PLAT_XLAT_TABLES_DYNAMIC 201 # define PLATFORM_STACK_SIZE UL(0x800) 202 # else 203 # define PLATFORM_STACK_SIZE UL(0x400) 204 # endif 205 #elif defined(IMAGE_BL32) 206 # define PLATFORM_STACK_SIZE UL(0x440) 207 #endif 208 209 /* CCI related constants */ 210 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 211 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 212 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 213 214 /* System timer related constants */ 215 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 216 217 /* TZC related constants */ 218 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 219 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 220 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 221 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 222 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 223 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 224 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 225 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 226 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 227 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 228 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 229 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 230 231 /* TZC related constants */ 232 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 233 234 /* 235 * Required ARM CSS based platform porting definitions 236 */ 237 238 /* GIC related constants (no GICR in GIC-400) */ 239 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 240 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 241 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 242 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 243 244 /* MHU related constants */ 245 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 246 247 /* 248 * Base address of the first memory region used for communication between AP 249 * and SCP. Used by the BOM and SCPI protocols. 250 */ 251 #if !CSS_USE_SCMI_SDS_DRIVER 252 /* 253 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 254 * means the SCP/AP configuration data gets overwritten when the AP initiates 255 * communication with the SCP. The configuration data is expected to be a 256 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 257 * which CPU is the primary, according to the shift and mask definitions below. 258 */ 259 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 260 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 261 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 262 #endif 263 264 /* 265 * SCP_BL2 uses up whatever remaining space is available as it is loaded before 266 * anything else in this memory region and is handed over to the SCP before 267 * BL31 is loaded over the top. 268 */ 269 #define PLAT_CSS_MAX_SCP_BL2_SIZE \ 270 ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) 271 272 #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE 273 274 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 275 CSS_G1S_IRQ_PROPS(grp), \ 276 ARM_G1S_IRQ_PROPS(grp), \ 277 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 278 (grp), GIC_INTR_CFG_LEVEL), \ 279 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 280 (grp), GIC_INTR_CFG_LEVEL), \ 281 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 282 (grp), GIC_INTR_CFG_LEVEL), \ 283 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 284 (grp), GIC_INTR_CFG_LEVEL), \ 285 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 286 (grp), GIC_INTR_CFG_LEVEL), \ 287 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 288 (grp), GIC_INTR_CFG_LEVEL), \ 289 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 290 (grp), GIC_INTR_CFG_LEVEL), \ 291 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 292 (grp), GIC_INTR_CFG_LEVEL) 293 294 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 295 296 /* 297 * Required ARM CSS SoC based platform porting definitions 298 */ 299 300 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 301 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 302 303 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 304 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 305 306 /* System power domain level */ 307 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 308 309 /* 310 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 311 */ 312 #ifdef __aarch64__ 313 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 314 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 315 #else 316 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 317 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 318 #endif 319 320 /* Number of SCMI channels on the platform */ 321 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 322 323 /* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */ 324 #ifdef JUNO_ETHOSN_TZMP1 325 #define ARM_ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT 326 #define ARM_ETHOSN_NPU_PROT_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_PROT 327 #define ARM_ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE 328 #define ARM_ETHOSN_NPU_FW_IMAGE_LIMIT \ 329 (JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE) 330 #endif 331 332 #endif /* PLATFORM_DEF_H */ 333