1 /* 2 * Copyright (c) 2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef JUNO_ETHOSN_TZMP1_DEF_H 8 #define JUNO_ETHOSN_TZMP1_DEF_H 9 10 #define JUNO_ETHOSN_TZC400_NSAID_FW_PROT 7 11 #define JUNO_ETHOSN_TZC400_NSAID_DATA_PROT 8 12 13 #define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE UL(0x000400000) /* 4 MB */ 14 #define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE (ARM_DRAM2_BASE) 15 #define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END (ARM_DRAM2_BASE + \ 16 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE \ 17 - 1U) 18 19 #define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_SIZE UL(0x004000000) /* 64 MB */ 20 #define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE ( \ 21 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END + 1) 22 #define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END ( \ 23 JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE + \ 24 JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_SIZE - 1U) 25 26 #define JUNO_ETHOSN_NS_DRAM2_BASE (JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END + \ 27 1) 28 #define JUNO_ETHOSN_NS_DRAM2_END (ARM_DRAM2_END) 29 #define JUNO_ETHOSN_NS_DRAM2_SIZE (ARM_DRAM2_SIZE - \ 30 JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END) 31 32 #define JUNO_FW_TZC_PROT_ACCESS \ 33 (TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_FW_PROT)) 34 #define JUNO_DATA_TZC_PROT_ACCESS \ 35 (TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_DATA_PROT)) 36 37 #define JUNO_ETHOSN_TZMP_REGIONS_DEF \ 38 { ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE, \ 39 TZC_REGION_S_RDWR, 0 }, \ 40 { ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, \ 41 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS }, \ 42 { JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 43 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END, \ 44 TZC_REGION_S_RDWR, JUNO_FW_TZC_PROT_ACCESS }, \ 45 { JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE, \ 46 JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END, \ 47 TZC_REGION_S_NONE, JUNO_DATA_TZC_PROT_ACCESS }, \ 48 { JUNO_ETHOSN_NS_DRAM2_BASE, JUNO_ETHOSN_NS_DRAM2_END, \ 49 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS } 50 51 #endif /* JUNO_ETHOSN_TZMP1_DEF_H */ 52