1 /* 2 * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include MBEDTLS_CONFIG_FILE 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 #include <plat/common/common_def.h> 20 21 #include "../juno_def.h" 22 #ifdef JUNO_ETHOSN_TZMP1 23 #include "../juno_ethosn_tzmp1_def.h" 24 #endif 25 26 /* Required platform porting definitions */ 27 /* Juno supports system power domain */ 28 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 29 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 30 JUNO_CLUSTER_COUNT + \ 31 PLATFORM_CORE_COUNT) 32 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 33 JUNO_CLUSTER1_CORE_COUNT) 34 35 /* Cryptocell HW Base address */ 36 #define PLAT_CRYPTOCELL_BASE UL(0x60050000) 37 38 /* 39 * Other platform porting definitions are provided by included headers 40 */ 41 42 /* 43 * Required ARM standard platform porting definitions 44 */ 45 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 46 47 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 48 49 /* Use the bypass address */ 50 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 51 BL1_ROM_BYPASS_OFFSET) 52 53 #define NSRAM_BASE UL(0x2e000000) 54 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 55 56 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 57 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 58 59 /* Range of kernel DTB load address */ 60 #define JUNO_DTB_DRAM_MAP_START ULL(0x82000000) 61 #define JUNO_DTB_DRAM_MAP_SIZE ULL(0x00008000) /* 32KB */ 62 63 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 64 JUNO_DTB_DRAM_MAP_START, \ 65 JUNO_DTB_DRAM_MAP_SIZE, \ 66 MT_MEMORY | MT_RO | MT_NS) 67 68 /* virtual address used by dynamic mem_protect for chunk_base */ 69 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 70 71 /* 72 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 73 */ 74 75 #if USE_ROMLIB 76 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 77 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 78 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) 79 #else 80 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 81 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 82 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) 83 #endif 84 85 /* 86 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 87 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 88 * flash 89 */ 90 91 #if TRUSTED_BOARD_BOOT 92 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 93 #else 94 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 95 #endif /* TRUSTED_BOARD_BOOT */ 96 97 /* 98 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 99 * plat_arm_mmap array defined for each BL stage. 100 */ 101 #ifdef IMAGE_BL1 102 # define PLAT_ARM_MMAP_ENTRIES 7 103 # define MAX_XLAT_TABLES 4 104 #endif 105 106 #ifdef IMAGE_BL2 107 #ifdef SPD_opteed 108 # define PLAT_ARM_MMAP_ENTRIES 11 109 # define MAX_XLAT_TABLES 5 110 #else 111 # define PLAT_ARM_MMAP_ENTRIES 10 112 # define MAX_XLAT_TABLES 4 113 #endif 114 #endif 115 116 #ifdef IMAGE_BL2U 117 # define PLAT_ARM_MMAP_ENTRIES 5 118 # define MAX_XLAT_TABLES 3 119 #endif 120 121 #ifdef IMAGE_BL31 122 # define PLAT_ARM_MMAP_ENTRIES 7 123 # define MAX_XLAT_TABLES 5 124 #endif 125 126 #ifdef IMAGE_BL32 127 # define PLAT_ARM_MMAP_ENTRIES 6 128 # define MAX_XLAT_TABLES 4 129 #endif 130 131 /* 132 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 133 * plus a little space for growth. 134 */ 135 #if TRUSTED_BOARD_BOOT 136 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 137 #else 138 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 139 #endif 140 141 /* 142 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 143 * little space for growth. 144 */ 145 #if TRUSTED_BOARD_BOOT 146 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 147 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 148 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 149 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 150 #else 151 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 152 #endif 153 #else 154 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 155 #endif 156 157 /* 158 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 159 * calculated using the current BL31 PROGBITS debug size plus the sizes of 160 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 161 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 162 */ 163 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 164 165 #if JUNO_AARCH32_EL3_RUNTIME 166 /* 167 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 168 * calculated using the current BL32 PROGBITS debug size plus the sizes of 169 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 170 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 171 */ 172 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000) 173 #endif 174 175 /* 176 * Size of cacheable stacks 177 */ 178 #if defined(IMAGE_BL1) 179 # if TRUSTED_BOARD_BOOT 180 # define PLATFORM_STACK_SIZE UL(0x1000) 181 # else 182 # define PLATFORM_STACK_SIZE UL(0x440) 183 # endif 184 #elif defined(IMAGE_BL2) 185 # if TRUSTED_BOARD_BOOT 186 # define PLATFORM_STACK_SIZE UL(0x1000) 187 # else 188 # define PLATFORM_STACK_SIZE UL(0x400) 189 # endif 190 #elif defined(IMAGE_BL2U) 191 # define PLATFORM_STACK_SIZE UL(0x400) 192 #elif defined(IMAGE_BL31) 193 # if PLAT_XLAT_TABLES_DYNAMIC 194 # define PLATFORM_STACK_SIZE UL(0x800) 195 # else 196 # define PLATFORM_STACK_SIZE UL(0x400) 197 # endif 198 #elif defined(IMAGE_BL32) 199 # define PLATFORM_STACK_SIZE UL(0x440) 200 #endif 201 202 /* CCI related constants */ 203 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 204 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 205 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 206 207 /* System timer related constants */ 208 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 209 210 /* TZC related constants */ 211 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 212 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 213 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 214 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 215 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 216 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 217 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 218 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 219 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 220 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 221 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 222 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 223 224 /* TZC related constants */ 225 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 226 227 /* 228 * Required ARM CSS based platform porting definitions 229 */ 230 231 /* GIC related constants (no GICR in GIC-400) */ 232 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 233 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 234 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 235 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 236 237 /* MHU related constants */ 238 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 239 240 /* 241 * Base address of the first memory region used for communication between AP 242 * and SCP. Used by the BOM and SCPI protocols. 243 */ 244 #if !CSS_USE_SCMI_SDS_DRIVER 245 /* 246 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 247 * means the SCP/AP configuration data gets overwritten when the AP initiates 248 * communication with the SCP. The configuration data is expected to be a 249 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 250 * which CPU is the primary, according to the shift and mask definitions below. 251 */ 252 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 253 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 254 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 255 #endif 256 257 /* 258 * SCP_BL2 uses up whatever remaining space is available as it is loaded before 259 * anything else in this memory region and is handed over to the SCP before 260 * BL31 is loaded over the top. 261 */ 262 #define PLAT_CSS_MAX_SCP_BL2_SIZE \ 263 ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) 264 265 #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE 266 267 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 268 CSS_G1S_IRQ_PROPS(grp), \ 269 ARM_G1S_IRQ_PROPS(grp), \ 270 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 271 (grp), GIC_INTR_CFG_LEVEL), \ 272 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 273 (grp), GIC_INTR_CFG_LEVEL), \ 274 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 275 (grp), GIC_INTR_CFG_LEVEL), \ 276 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 277 (grp), GIC_INTR_CFG_LEVEL), \ 278 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 279 (grp), GIC_INTR_CFG_LEVEL), \ 280 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 281 (grp), GIC_INTR_CFG_LEVEL), \ 282 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 283 (grp), GIC_INTR_CFG_LEVEL), \ 284 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 285 (grp), GIC_INTR_CFG_LEVEL) 286 287 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 288 289 /* 290 * Required ARM CSS SoC based platform porting definitions 291 */ 292 293 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 294 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 295 296 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 297 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 298 299 /* System power domain level */ 300 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 301 302 /* 303 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 304 */ 305 #ifdef __aarch64__ 306 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 307 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 308 #else 309 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 310 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 311 #endif 312 313 /* Number of SCMI channels on the platform */ 314 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 315 316 /* Protected memory NSAIDs for the Arm(R) Ethos(TM)-N NPU driver */ 317 #ifdef JUNO_ETHOSN_TZMP1 318 #define ARM_ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT 319 #define ARM_ETHOSN_NPU_PROT_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_PROT 320 #endif 321 322 #endif /* PLATFORM_DEF_H */ 323