fix(cpus): workaround for Cortex-X3 erratum 4302966

Cortex-X3 erratum 4302966 applies to revisions r0p0,
r1p0, r1p1, r1p2, and it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1

fix(cpus): workaround for Cortex-X3 erratum 4302966

Cortex-X3 erratum 4302966 applies to revisions r0p0,
r1p0, r1p1, r1p2, and it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest

Change-Id: I284ee7fe611c4c9861696fde62f796e6fae6dff6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 3888125

Cortex-X3 erratum 3888125 that applies to revisions r0p0,
r1p0, r1p1 and r1p2 of the CPU. It is still open.

The erratum can be avoided by setting

fix(cpus): workaround for Cortex-X3 erratum 3888125

Cortex-X3 erratum 3888125 that applies to revisions r0p0,
r1p0, r1p1 and r1p2 of the CPU. It is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest

Change-Id: I5c01dfcffc6e56163aba03428e21fedee8cc7042
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes I7af8857d,I7fc84d2c into integration

* changes:
docs(maintainers): add Gabriel as clock framework maintainer
docs(maintainers): sort frameworks alphabetically

Merge "docs(per-cpu): update diagram for NUMA enabled per-cpu layout" into integration

Merge "feat(docs): document PSCI power_state" into integration

Merge "docs: update Ignored Checkpatch Warnings chapter" into integration

Merge "docs(threat-model): clarify scope of experimental features" into integration

Merge changes from topic "xl/v2-errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V2 erratum 4302968
fix(cpus): workaround for Neoverse-V2 erratum 3888126

fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FE

fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FEATURE. Setting -march directly can lead to unexpected results
when using the above flags and is generally not recommended within tfa.

This patch migrates all instances of -march=armv8-a+crc to
ARM_ARCH_FEATURE=crc. Arm platforms (via arm_common.mk) are checked and
those that support cores greater than arm8.1 do not get the flag as it
is automatically pulled in.

Change-Id: I846f97367eab9529524a2805d5b87d34cce2360f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(cpus): workaround for Cortex-A76AE erratum 2753838" into integration

fix(cpus): workaround for Neoverse-V2 erratum 4302968

Neoverse-V2 erratum 4302968 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR5_E

fix(cpus): workaround for Neoverse-V2 erratum 4302968

Neoverse-V2 erratum 4302968 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I42b27e19d61a7f9c57efe1b5f5336d165eb98210
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Neoverse-V2 erratum 3888126

Neoverse-V2 erratum 3888126 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR2[2

fix(cpus): workaround for Neoverse-V2 erratum 3888126

Neoverse-V2 erratum 3888126 that applies to revisions
r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I4068aa73d38a70c00d66bb894169be2659d67de7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 4302969

Cortex-X2 erratum 4302969 that applies to revisions
r0p0, r1p0, r2p0 and r2p1, and is still open.

This erratum can be avoided by setting CPUACTLR

fix(cpus): workaround for Cortex-X2 erratum 4302969

Cortex-X2 erratum 4302969 that applies to revisions
r0p0, r1p0, r2p0 and r2p1, and is still open.

This erratum can be avoided by setting CPUACTLR5_EL1[50] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I6c5de5843f2199fa697f8336558fa56a87ee846d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X2 erratum 3888122

Cortex-X2 erratum 3888122 that applies to revisions r0p0,
r1p0, r2p0 and r2p1 and is still open.

The erratum can be avoided by setting CPUACTLR2[

fix(cpus): workaround for Cortex-X2 erratum 3888122

Cortex-X2 erratum 3888122 that applies to revisions r0p0,
r1p0, r2p0 and r2p1 and is still open.

The erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I368cfdd216ea5875b81640415ff71b15f46ea953
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-A76AE erratum 2753838

Cortex-A76AE erratum 2753838 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by addin

fix(cpus): workaround for Cortex-A76AE erratum 2753838

Cortex-A76AE erratum 2753838 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by adding a DSB instruction before
the ISB of the power-down code sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/latest/

Change-Id: I338834a21c14879faee5280876a59153d549cb7b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "xl/x925-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X925 erratum 3865185
fix(cpus): workaround for Cortex-X925 erratum 3730893
fix(cpus): wor

Merge changes from topic "xl/x925-errata" into integration

* changes:
fix(cpus): workaround for Cortex-X925 erratum 3865185
fix(cpus): workaround for Cortex-X925 erratum 3730893
fix(cpus): workaround for Cortex-X925 erratum 3692980
fix(cpus): workaround for Cortex-X925 erratum 3324334
fix(cpus): workaround for Cortex-X925 erratum 2933290
fix(cpus): workaround for Cortex-X925 erratum 2922378
fix(cpus): workaround for Cortex-X925 erratum 2921199

show more ...

fix(cpus): workaround for Cortex-X925 erratum 3865185

Cortex-X925 erratum 3865185 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

Load issued to Non-Cacheable or De

fix(cpus): workaround for Cortex-X925 erratum 3865185

Cortex-X925 erratum 3865185 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

Load issued to Non-Cacheable or Device GRE memory can
read stale data brought in by an earlier load to the
same cache-line thereby violating ordering requirements.
This erratum can be avoided by setting CPUACTLR2[22] to 1'b1,
which will disable linking multiple Non-Cacheable or Device
GRE loads to the same read request for the cache-line. This
might have a significant performance impact to Non-cacheable
and Device GRE read bandwidth for streaming scenarios.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: Iff224ef82bd1cb9aff8d6b11451e2ac1d048149f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-X925 erratum 3730893

Cortex-X925 erratum 3730893 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

PE executing a load instruction th

fix(cpus): workaround for Cortex-X925 erratum 3730893

Cortex-X925 erratum 3730893 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

PE executing a load instruction that accesses a memory
region which crosses a 4K boundary might cause a deadlock.
This erratum can be avoided by setting CPUACTLR_EL1[60:58]
to 3'b001, which has a small perf impact.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: I0245183669255afb0d3ec71cafa058aa72129de0
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X925 erratum 3692980

Cortex-X925 erratum 3692980 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

This erratum can be avoided by set

fix(cpus): workaround for Cortex-X925 erratum 3692980

Cortex-X925 erratum 3692980 is a Cat B erratum that
applies to revisions r0p0 and r0p1, it is fixed in r0p2.

This erratum can be avoided by setting CPUACTLR6_EL1[41] to 1.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: If2b88e3a23bda424ba17ab5cead07e7d701db2e3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X925 erratum 3324334

Cortex-X925 erratum 3324334 is a Cat B erratum that
applies to revisions r0p0, r0p1 and is fixed in r0p2.

This erratum can be avoided by adding

fix(cpus): workaround for Cortex-X925 erratum 3324334

Cortex-X925 erratum 3324334 is a Cat B erratum that
applies to revisions r0p0, r0p1 and is fixed in r0p2.

This erratum can be avoided by adding a speculation barrier
instruction following writes to the SSBS register to
ensure the new value of PSTATE.SSBS affects the subsequent
instructions in the execution stream under speculation.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: I57d2b306b0a3128f3786f4797e6765234ad429cf
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

fix(cpus): workaround for Cortex-X925 erratum 2933290

Cortex-X925 erratum 2933290 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

MTE Tag checking may not be performed if an access th

fix(cpus): workaround for Cortex-X925 erratum 2933290

Cortex-X925 erratum 2933290 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

MTE Tag checking may not be performed if an access that crosses
a 16-byte boundary encounters a poisoned Allocation tag. This
erratum can be avoided by setting CPUACTLR5_EL1[42] to 1.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: I6d5c680a3d5156b3b17d59de79f8b650d56deff3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X925 erratum 2922378

Cortex-X925 erratum 2922378 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

Branch prediction history is not suppressed when swit

fix(cpus): workaround for Cortex-X925 erratum 2922378

Cortex-X925 erratum 2922378 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

Branch prediction history is not suppressed when switching from low
to high EL, this erratum can be avoided by setting the CPUACTLR4[10]
to 1 and CPUACTLR4[11] to 1.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: Ieb5fe278821d85382af60be25e9546e65ba9a629
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-X925 erratum 2921199

Cortex-X925 erratum 2921199 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

Under certain rare microarchitectural conditions, two

fix(cpus): workaround for Cortex-X925 erratum 2921199

Cortex-X925 erratum 2921199 is a Cat B erratum that
applies to r0p0 and is fixed in r0p1.

Under certain rare microarchitectural conditions, two or more STG
instructions that access the same cache line but different 32-bytes
might not write the MTE allocation tag to memory. This erratum can
be avoided by setting CPUACTLR5_EL1[14] to 1.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: I8eb8bbdd6f99f69c8713400191ac66f55ffedc8b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge changes from topic "xl/c1nano-errata" into integration

* changes:
fix(cpus): workaround for C1-Nano erratum 3754876
fix(cpus): workaround for C1-Nano erratum 3419531
fix(cpus): workaroun

Merge changes from topic "xl/c1nano-errata" into integration

* changes:
fix(cpus): workaround for C1-Nano erratum 3754876
fix(cpus): workaround for C1-Nano erratum 3419531
fix(cpus): workaround for C1-Nano erratum 3630925
fix(cpus): workaround for C1-Nano erratum 3616450
fix(cpus): workaround for C1-Nano erratum 3516455
fix(cpus): workaround for C1-Nano erratum 3437202
fix(cpus): workaround for C1-Nano erratum 3392149

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Merge changes from topic "v3_errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V3 erratum 3312417
fix(cpus): workaround for Neoverse V3 erratum 3878291
fix(cpus): workarou

Merge changes from topic "v3_errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V3 erratum 3312417
fix(cpus): workaround for Neoverse V3 erratum 3878291
fix(cpus): workaround for Neoverse V3 erratum 3864536
fix(cpus): workaround for Neoverse V3 erratum 3782181
fix(cpus): workaround for Neoverse V3 erratum 3734562
fix(cpus): workaround for Neoverse V3 erratum 3696307

show more ...