fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://de

fix(cpus): workaround for Cortex-A720 erratum 3711910

Cortex-A720 erratum 3711910 is a Cat B erratum that applies to
revisions r0p0, r0p1 and r0p2, and is still open.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421

Change-Id: Id65d5ba41b96648b07c09df77fb25cc4bdb50800
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

Merge changes from topic "ar/v2_errata" into integration

* changes:
fix(cpus): workaround for Neoverse-V2 erratum 3701771
fix(cpus): workaround for Neoverse-V2 erratum 3841324

fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/resto

fix(cpus): workaround for Neoverse-V2 erratum 3701771

Neoverse-V2 erratum 3701771 that applies to r0p0, r0p1, r0p2 is
still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

The mitigation is implemented in commit 7455cd172 and this patch should be applied on top of it.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ic0ad68f7bd393bdc03343d5ba815adb23bf6a24d

show more ...

fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUAC

fix(cpus): workaround for Neoverse-V2 erratum 3841324

Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.

This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9b3a5266103e5000d207c7a270c65455d0646102

show more ...

feat(dsu): enable PMU registers access at EL1

- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
co

feat(dsu): enable PMU registers access at EL1

- Disable trapping of write accesses to DSU cluster PMU registers
at EL3 and EL2.
- Clear the SPME bit in CLUSTERPMMDCR_EL3 to prohibit PMU event
counting in the secure state.

Change-Id: If3eb6e997330ae86f45760e0e862c003861f3d66
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>

show more ...

docs(rdaspen): introduce rdaspen docs

RD-Aspen platform is formally introduced into the
documentation.

Refactors RD platforms separately, and a generic
Automotive RD index doc file is created.

Mai

docs(rdaspen): introduce rdaspen docs

RD-Aspen platform is formally introduced into the
documentation.

Refactors RD platforms separately, and a generic
Automotive RD index doc file is created.

Maintainers list updated for platform maintainer
of rdaspen.

Change-Id: I289a8caaa6f0e34e953f4101ee2814f1500bc9c8
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

show more ...

feat(docs): platform hook to log GPT corruption

The log GPT corruption add several platform hook for log GPT
corruption. Update the documentation for the functions.

Change-Id: Ia2ec3654c869801aece9

feat(docs): platform hook to log GPT corruption

The log GPT corruption add several platform hook for log GPT
corruption. Update the documentation for the functions.

Change-Id: Ia2ec3654c869801aece95b19ae5a5020cb01f905
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

show more ...

Merge "feat(mbedtls): update mbedtls to version 3.6.4" into integration

feat(lfa): add platform hook for activation notification

Introduce a new platform API, plat_lfa_notify_activate(), which allows
the platform to notify its security engine to begin component
activati

feat(lfa): add platform hook for activation notification

Introduce a new platform API, plat_lfa_notify_activate(), which allows
the platform to notify its security engine to begin component
activation. The function accepts a component identifier and should
return 0 on success or an error code on failure.

Documentation and header files are updated accordingly, and the call is
integrated into the LFA activation path.

Change-Id: Ic66aa675bba62633cc92992b965d144a6f9ef129
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

feat(mbedtls): update mbedtls to version 3.6.4

In order to successfully update mbedtls to version 3.6.4, the
redundant-decls warning must be disabled to accomodate a change in the
definition locatio

feat(mbedtls): update mbedtls to version 3.6.4

In order to successfully update mbedtls to version 3.6.4, the
redundant-decls warning must be disabled to accomodate a change in the
definition locations of some helper functions. This is currently an open
issue for mbedtls: https://github.com/Mbed-TLS/mbedtls/issues/10376

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I57c9c14aabe75a51c74dcf2a33faf59f95ce2386

show more ...

Merge "docs(drtm): update to latest specification and remove build/run section" into integration

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being

feat(cpufeat): enable FEAT_CPA2 for EL3

FEAT_CPA2 enables checked pointer arithmetic, which in the event
of an arithmetic overflow in pointer generation will result in a
non-canonical pointer being generated and subsequent address fault.

Note that FEAT_CPA is a trivial implementation that exists in
some hardware purely so it can run CPA2-enabled instructions
without crashing but they don't actually have checked arithmetic,
so FEAT_CPA is not explicitly enabled in TF-A.

Change-Id: I6d2ca7a7e4b986bb9e917aa8baf8091a271c168b
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

Merge "chore(handoff)!: remove in-tree TLC implementation" into integration

Merge changes I2c7c8da9,I9786ab88,Ia76ba243,Ifec40dee,Ifdd59c09, ... into integration

* changes:
fix(cpus): workaround for Cortex-A510 erratum 3704847
fix(cpus): workaround for Cortex-A510 errat

Merge changes I2c7c8da9,I9786ab88,Ia76ba243,Ifec40dee,Ifdd59c09, ... into integration

* changes:
fix(cpus): workaround for Cortex-A510 erratum 3704847
fix(cpus): workaround for Cortex-A510 erratum 3672349
fix(cpus): workaround for Cortex-A510 erratum 2420992
fix(cpus): workaround for Cortex-A510 erratum 2218134
fix(cpus): workaround for Cortex-A510 erratum 2169012
fix(cpus): workaround for Cortex-A510 erratum 2008766

show more ...

Merge "docs(tegra): add note that clang is not supported" into integration

fix(cpus): workaround for Cortex-A510 erratum 3704847

Cortex-A510 erratum 3704847 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

fix(cpus): workaround for Cortex-A510 erratum 3704847

Cortex-A510 erratum 3704847 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

The workaround is to set bit 9 in CPUACTLR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: I2c7c8da9c66471115b5bf8fb5c87d4de46ca265c
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 3672349

Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

fix(cpus): workaround for Cortex-A510 erratum 3672349

Cortex-A510 erratum 3672349 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

The workaround is to clear the WFE_RET_CTRL and WFI_RET_CTRL fields
in CPUPWRCTLR_EL1 to disable full retention.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: I9786ab8843a2eab45e650c6af50b6933481527ec
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 2420992

Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.

The workaround is to set bit

fix(cpus): workaround for Cortex-A510 erratum 2420992

Cortex-A510 erratum 2420992 is a Cat B erratum that applies only to
revisions r1p0 and r1p1, and is fixed in r1p1.

The workaround is to set bit 3 in CPUACTLR3_EL1 which will have no
performance impact, but will increase power consumption by 0.3-0.5%.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Ia76ba2431d76f14c08b95a998806986190d682c3
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 2218134

Cortex-A510 erratum 2218134 is a Cat B erratum that applies only to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit 43 in CPUA

fix(cpus): workaround for Cortex-A510 erratum 2218134

Cortex-A510 erratum 2218134 is a Cat B erratum that applies only to
revision r1p0 and is fixed in r1p1.

The workaround is to set bit 43 in CPUACTLR2_EL1 which will correct
the instruction fetch stream with no performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Ifec40dee2f7e42c56c9ed447b6b1997b170f9453
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 2169012

Cortex-A510 erratum 2169012 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.

This erratum ha

fix(cpus): workaround for Cortex-A510 erratum 2169012

Cortex-A510 erratum 2169012 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.

This erratum has an identical workaround to 1922240 and resolves
a similar issue, but that erratum only applies to r0p0 which is
not used in any production hardware, so it has been removed.

This workaround has a negligible performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Ifdd59c09e84252dc292600630d81d32986fd6c0c
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cpus): workaround for Cortex-A510 erratum 2008766

Cortex-A510 erratum 2008766 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

fix(cpus): workaround for Cortex-A510 erratum 2008766

Cortex-A510 erratum 2008766 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.

The workaround is to clear the ERXCTLR_EL1.ED bit before power
down, which will cause any detected errors during power down to
be ignored.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/

Change-Id: Id1aa0f2c518a055363c962f9abdb27e1ee8bff18
Signed-off-by: John Powell <john.powell@arm.com>

show more ...

fix(cm): deprecate use of NS_TIMER_SWITCH

On AArch64, secure world has it's own EL3 physical timer registers
accessible to secure EL1 in absence of S-EL2. With S-EL2 there is
virtualized view availa

fix(cm): deprecate use of NS_TIMER_SWITCH

On AArch64, secure world has it's own EL3 physical timer registers
accessible to secure EL1 in absence of S-EL2. With S-EL2 there is
virtualized view available for EL1 timer registers. So it is
unreasonable for secure world to use non-secure EL1 physical timer
registers. Moreover, the non-secure operating system (Linux in our case)
relies heavily on these EL1 physical timer registers for scheduling
decisions. If NS_TIMER_SWITCH is enabled, it simply breaks the preemption
model of the non-secure world by disabling non-secure timer interrupts
leading to RCU stalls being observed on long running secure world tasks.

The only arch timer register which will benefit from context management
is cntkctl_el1: Counter-timer Kernel Control Register. This enables the
secure and non-secure worlds to independently control accesses to EL0
for counter-timer registers. This is something that OP-TEE uses to
enable ftrace feature for Trusted Applications and SPM_MM uses for EL0
access as well.

Lets enable context management of cntkctl_el1 by default and deprecate
conditional context management of non-secure EL1 physical timer
registers for whom there isn't any upstream user. With that deprecate
this NS_TIMER_SWITCH build option which just adds confusion for the
platform maintainers. It will be eventually dropped following
deprecation policy of TF-A.

Reported-by: Stauffer Thomas MTANA <thomas.stauffer@mt.com>
Reported-by: Andrew Davis <afd@ti.com>
Change-Id: Ifb3a919dc0bf8c05c38895352de5fe94b4f4387e
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

show more ...

docs(drtm): update to latest specification and remove build/run section

- Updated reference to the latest Arm DRTM Architecture
Specification (DEN0113).
- Removed the outdated "Build and Run" sect

docs(drtm): update to latest specification and remove build/run section

- Updated reference to the latest Arm DRTM Architecture
Specification (DEN0113).
- Removed the outdated "Build and Run" section to avoid
duplication, since this test is already covered in the
TF-A CI run.

Change-Id: I33f080711872c8b07df02d835b5c5c6b652e557c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

chore(handoff)!: remove in-tree TLC implementation

Remove the TLC implementation from this repository. TLC now
resides with the C implementation of the Transfer List Library,
making it easier to con

chore(handoff)!: remove in-tree TLC implementation

Remove the TLC implementation from this repository. TLC now
resides with the C implementation of the Transfer List Library,
making it easier to consume in other projects.

BREAKING-CHANGE: Projects/scripts relying on the in-tree TLC tool will
need to use the new, externalized location or workflow.

Change-Id: Ib34ff207292ab5523f4464419c51cfe816834fd4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

show more ...

fix(rme): fix incorrect shift operation in rmmd

This patch fixes the shift operation in rmmd_mecid_key_update().
Also, a function name fix is made to the platform porting guide.

Change-Id: I80f0e26

fix(rme): fix incorrect shift operation in rmmd

This patch fixes the shift operation in rmmd_mecid_key_update().
Also, a function name fix is made to the platform porting guide.

Change-Id: I80f0e2653dcb5cdd7b5937506ca040b2105ca3ce
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

show more ...