1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_neoverse_v2_3701771 26 27cpu_reset_prologue neoverse_v2 28 29workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597 30 /* Disable retention control for WFI and WFE. */ 31 mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 32 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 33 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 34 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 35 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 36 msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 37workaround_reset_end neoverse_v2, ERRATUM(2618597) 38 39check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1) 40 41workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553 42 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \ 43 NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH 44workaround_reset_end neoverse_v2, ERRATUM(2662553) 45 46check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1) 47 48workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 49 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 50workaround_reset_end neoverse_v2, ERRATUM(2719105) 51 52check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 53 54workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 55 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 56 sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 57workaround_reset_end neoverse_v2, ERRATUM(2743011) 58 59check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 60 61workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 62 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 63workaround_reset_end neoverse_v2, ERRATUM(2779510) 64 65check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 66 67workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 68 /* dsb before isb of power down sequence */ 69 dsb sy 70workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 71 72check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 73 74add_erratum_entry neoverse_v2, ERRATUM(3701771), ERRATA_V2_3701771 75 76check_erratum_ls neoverse_v2, ERRATUM(3701771), CPU_REV(0, 2) 77 78workaround_reset_start neoverse_v2, ERRATUM(3841324), ERRATA_V2_3841324 79 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, BIT(1) 80workaround_reset_end neoverse_v2, ERRATUM(3841324) 81 82check_erratum_ls neoverse_v2, ERRATUM(3841324), CPU_REV(0, 1) 83 84workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 85#if IMAGE_BL31 86 /* 87 * The Neoverse-V2 generic vectors are overridden to apply errata 88 * mitigation on exception entry from lower ELs. 89 */ 90 override_vector_table wa_cve_vbar_neoverse_v2 91#endif /* IMAGE_BL31 */ 92workaround_reset_end neoverse_v2, CVE(2022,23960) 93 94check_erratum_ls neoverse_v2, CVE(2022, 23960), CPU_REV(0, 0) 95 96/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 97workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 98 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46) 99workaround_reset_end neoverse_v2, CVE(2024, 5660) 100 101check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2) 102 103#if WORKAROUND_CVE_2022_23960 104 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 105#endif /* WORKAROUND_CVE_2022_23960 */ 106 107 /* ---------------------------------------------------------------- 108 * CVE-2024-7881 is mitigated for Neoverse-V2 using erratum 3696445 109 * workaround by disabling the affected prefetcher setting 110 * CPUACTLR6_EL1[41]. 111 * ---------------------------------------------------------------- 112 */ 113workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 114 sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) 115workaround_reset_end neoverse_v2, CVE(2024, 7881) 116 117check_erratum_ls neoverse_v2, CVE(2024, 7881), CPU_REV(0, 2) 118 119 /* ---------------------------------------------------- 120 * HW will do the cache maintenance while powering down 121 * ---------------------------------------------------- 122 */ 123func neoverse_v2_core_pwr_dwn 124 /* --------------------------------------------------- 125 * Enable CPU power down bit in power control register 126 * --------------------------------------------------- 127 */ 128 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 129 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 130 131 isb 132 ret 133endfunc neoverse_v2_core_pwr_dwn 134 135cpu_reset_func_start neoverse_v2 136 /* Disable speculative loads */ 137 msr SSBS, xzr 138 139#if NEOVERSE_Vx_EXTERNAL_LLC 140 /* Some systems may have External LLC, core needs to be made aware */ 141 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT 142#endif 143cpu_reset_func_end neoverse_v2 144 145 /* --------------------------------------------- 146 * This function provides Neoverse V2- 147 * specific register information for crash 148 * reporting. It needs to return with x6 149 * pointing to a list of register names in ascii 150 * and x8 - x15 having values of registers to be 151 * reported. 152 * --------------------------------------------- 153 */ 154.section .rodata.neoverse_v2_regs, "aS" 155neoverse_v2_regs: /* The ascii list of register names to be reported */ 156 .asciz "cpuectlr_el1", "" 157 158func neoverse_v2_cpu_reg_dump 159 adr x6, neoverse_v2_regs 160 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 161 ret 162endfunc neoverse_v2_cpu_reg_dump 163 164declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 165 neoverse_v2_reset_func, \ 166 neoverse_v2_core_pwr_dwn 167