1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v2.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_neoverse_v2_3701771 26 27cpu_reset_prologue neoverse_v2 28 29workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597 30 /* Disable retention control for WFI and WFE. */ 31 mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 32 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 33 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 34 bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 35 #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 36 msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 37workaround_reset_end neoverse_v2, ERRATUM(2618597) 38 39/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */ 40add_erratum_entry neoverse_v2, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960 41 42check_erratum_ls neoverse_v2, ERRATUM(ARCH_WORKAROUND_3), CPU_REV(0, 0) 43 44check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1) 45 46workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553 47 sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \ 48 NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH 49workaround_reset_end neoverse_v2, ERRATUM(2662553) 50 51check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1) 52 53workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 54 sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 55workaround_reset_end neoverse_v2, ERRATUM(2719105) 56 57check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) 58 59workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 60 sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 61 sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 62workaround_reset_end neoverse_v2, ERRATUM(2743011) 63 64check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) 65 66workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 67 sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 68workaround_reset_end neoverse_v2, ERRATUM(2779510) 69 70check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) 71 72workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 73 /* dsb before isb of power down sequence */ 74 dsb sy 75workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 76 77check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) 78 79add_erratum_entry neoverse_v2, ERRATUM(3701771), ERRATA_V2_3701771 80 81check_erratum_ls neoverse_v2, ERRATUM(3701771), CPU_REV(0, 2) 82 83workaround_reset_start neoverse_v2, ERRATUM(3841324), ERRATA_V2_3841324 84 sysreg_bit_set NEOVERSE_V2_CPUACTLR_EL1, BIT(1) 85workaround_reset_end neoverse_v2, ERRATUM(3841324) 86 87check_erratum_ls neoverse_v2, ERRATUM(3841324), CPU_REV(0, 1) 88 89workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 90#if IMAGE_BL31 91 /* 92 * The Neoverse-V2 generic vectors are overridden to apply errata 93 * mitigation on exception entry from lower ELs. 94 */ 95 override_vector_table wa_cve_vbar_neoverse_v2 96#endif /* IMAGE_BL31 */ 97workaround_reset_end neoverse_v2, CVE(2022,23960) 98 99check_erratum_ls neoverse_v2, CVE(2022, 23960), CPU_REV(0, 0) 100 101/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 102workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 103 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46) 104workaround_reset_end neoverse_v2, CVE(2024, 5660) 105 106check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2) 107 108#if WORKAROUND_CVE_2022_23960 109 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 110#endif /* WORKAROUND_CVE_2022_23960 */ 111 112 /* ---------------------------------------------------------------- 113 * CVE-2024-7881 is mitigated for Neoverse-V2 using erratum 3696445 114 * workaround by disabling the affected prefetcher setting 115 * CPUACTLR6_EL1[41]. 116 * ---------------------------------------------------------------- 117 */ 118workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 119 sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41) 120workaround_reset_end neoverse_v2, CVE(2024, 7881) 121 122check_erratum_ls neoverse_v2, CVE(2024, 7881), CPU_REV(0, 2) 123 124 /* ---------------------------------------------------- 125 * HW will do the cache maintenance while powering down 126 * ---------------------------------------------------- 127 */ 128func neoverse_v2_core_pwr_dwn 129 /* --------------------------------------------------- 130 * Enable CPU power down bit in power control register 131 * --------------------------------------------------- 132 */ 133 sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 134 apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 135 136 isb 137 ret 138endfunc neoverse_v2_core_pwr_dwn 139 140cpu_reset_func_start neoverse_v2 141 /* Disable speculative loads */ 142 msr SSBS, xzr 143 144#if NEOVERSE_Vx_EXTERNAL_LLC 145 /* Some systems may have External LLC, core needs to be made aware */ 146 sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT 147#endif 148cpu_reset_func_end neoverse_v2 149 150 /* --------------------------------------------- 151 * This function provides Neoverse V2- 152 * specific register information for crash 153 * reporting. It needs to return with x6 154 * pointing to a list of register names in ascii 155 * and x8 - x15 having values of registers to be 156 * reported. 157 * --------------------------------------------- 158 */ 159.section .rodata.neoverse_v2_regs, "aS" 160neoverse_v2_regs: /* The ascii list of register names to be reported */ 161 .asciz "cpuectlr_el1", "" 162 163func neoverse_v2_cpu_reg_dump 164 adr x6, neoverse_v2_regs 165 mrs x8, NEOVERSE_V2_CPUECTLR_EL1 166 ret 167endfunc neoverse_v2_cpu_reg_dump 168 169declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ 170 neoverse_v2_reset_func, \ 171 neoverse_v2_core_pwr_dwn 172