1# 2# Copyright (c) 2021-2025 Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Making sure the corstone1000 platform type is specified 8ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),) 9 $(error TARGET_PLATFORM must be fpga or fvp) 10endif 11 12ifeq ($(CORSTONE1000_CORTEX_A320), 1) 13CORSTONE1000_CPU_LIBS +=lib/cpus/aarch64/cortex_a320.S 14$(eval $(call add_define,CORSTONE1000_CORTEX_A320)) 15GIC_ENABLE_V4_EXTN := 1 16GICV3_SUPPORT_GIC600 := 1 17else 18CORSTONE1000_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S 19endif 20 21PLAT_INCLUDES := -Iplat/arm/board/corstone1000/common/include \ 22 -Iplat/arm/board/corstone1000/include \ 23 -Iinclude/plat/arm/common \ 24 -Iinclude/plat/arm/css/common/aarch64 25 26override ARM_PLAT_PROVIDES_BL2_MEM_PARAMS := 1 27 28CORSTONE1000_FW_NVCTR_VAL := 255 29TFW_NVCTR_VAL := ${CORSTONE1000_FW_NVCTR_VAL} 30NTFW_NVCTR_VAL := ${CORSTONE1000_FW_NVCTR_VAL} 31 32override NEED_BL1 := no 33 34override NEED_BL2 := yes 35FIP_BL2_ARGS := tb-fw 36 37override NEED_BL2U := no 38override NEED_BL31 := yes 39NEED_BL32 ?= yes 40override NEED_BL33 := yes 41 42# Add CORSTONE1000_WITH_BL32 as a preprocessor define (-D option) 43ifeq (${NEED_BL32},yes) 44$(eval $(call add_define,CORSTONE1000_WITH_BL32)) 45endif 46 47ENABLE_MULTICORE := 0 48ifneq ($(filter ${TARGET_PLATFORM}, fvp),) 49ifeq (${ENABLE_MULTICORE},1) 50$(eval $(call add_define,CORSTONE1000_FVP_MULTICORE)) 51endif 52endif 53 54ifeq ($(CORSTONE1000_CORTEX_A320), 1) 55USE_GIC_DRIVER := 3 56else 57USE_GIC_DRIVER := 2 58endif 59 60BL2_SOURCES += plat/arm/board/corstone1000/common/corstone1000_security.c \ 61 plat/arm/board/corstone1000/common/corstone1000_err.c \ 62 plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c \ 63 lib/utils/mem_region.c \ 64 lib/cpus/aarch64/cpu_helpers.S \ 65 plat/arm/board/corstone1000/common/corstone1000_helpers.S \ 66 plat/arm/board/corstone1000/common/corstone1000_plat.c \ 67 plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \ 68 ${CORSTONE1000_CPU_LIBS} \ 69 70 71BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 72 lib/utils/mem_region.c \ 73 plat/arm/board/corstone1000/common/corstone1000_helpers.S \ 74 plat/arm/board/corstone1000/common/corstone1000_topology.c \ 75 plat/arm/board/corstone1000/common/corstone1000_security.c \ 76 plat/arm/board/corstone1000/common/corstone1000_plat.c \ 77 plat/arm/board/corstone1000/common/corstone1000_pm.c \ 78 plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c \ 79 ${CORSTONE1000_CPU_LIBS} 80 81ifneq (${ENABLE_STACK_PROTECTOR},0) 82 ifneq (${ENABLE_STACK_PROTECTOR},none) 83 CORSTONE1000_SECURITY_SOURCES := plat/arm/board/corstone1000/common/corstone1000_stack_protector.c 84 BL2_SOURCES += ${CORSTONE1000_SECURITY_SOURCES} 85 BL31_SOURCES += ${CORSTONE1000_SECURITY_SOURCES} 86 endif 87endif 88 89FDT_SOURCES += plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts 90CORSTONE1000_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/corstone1000_spmc_manifest.dtb 91 92# Add the SPMC manifest to FIP and specify the same to certtool 93$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE1000_TOS_FW_CONFIG},--tos-fw-config,${CORSTONE1000_TOS_FW_CONFIG})) 94 95# Adding TARGET_PLATFORM as a GCC define (-D option) 96$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM}))) 97 98# Adding CORSTONE1000_FW_NVCTR_VAL as a GCC define (-D option) 99$(eval $(call add_define,CORSTONE1000_FW_NVCTR_VAL)) 100 101include plat/arm/common/arm_common.mk 102include plat/arm/board/common/board_common.mk 103