1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <context.h> 15 #include <drivers/arm/gic.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 #include <lib/el3_runtime/cpu_data.h> 18 #include <lib/el3_runtime/pubsub_events.h> 19 #include <lib/pmf/pmf.h> 20 #include <lib/runtime_instr.h> 21 #include <plat/common/platform.h> 22 23 #include "psci_private.h" 24 25 /******************************************************************************* 26 * This function does generic and platform specific operations after a wake-up 27 * from standby/retention states at multiple power levels. 28 ******************************************************************************/ 29 static void psci_cpu_suspend_to_standby_finish(unsigned int end_pwrlvl, 30 psci_power_state_t *state_info) 31 { 32 /* 33 * Plat. management: Allow the platform to do operations 34 * on waking up from retention. 35 */ 36 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 37 38 /* This loses its meaning when not suspending, reset so it's correct for OFF */ 39 psci_set_suspend_pwrlvl(PLAT_MAX_PWR_LVL); 40 } 41 42 /******************************************************************************* 43 * This function does generic and platform specific suspend to power down 44 * operations. 45 ******************************************************************************/ 46 static void psci_suspend_to_pwrdown_start(unsigned int idx, 47 unsigned int end_pwrlvl, 48 unsigned int max_off_lvl, 49 const psci_power_state_t *state_info) 50 { 51 PUBLISH_EVENT_ARG(psci_suspend_pwrdown_start, &idx); 52 53 #if PSCI_OS_INIT_MODE 54 if (psci_suspend_mode == OS_INIT) { 55 #ifdef PLAT_MAX_CPU_SUSPEND_PWR_LVL 56 end_pwrlvl = PLAT_MAX_CPU_SUSPEND_PWR_LVL; 57 #else 58 end_pwrlvl = PLAT_MAX_PWR_LVL; 59 #endif 60 } 61 #endif 62 63 /* Save PSCI target power level for the suspend finisher handler */ 64 psci_set_suspend_pwrlvl(end_pwrlvl); 65 66 /* 67 * Flush the target power level as it might be accessed on power up with 68 * Data cache disabled. 69 */ 70 psci_flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); 71 72 /* 73 * Call the cpu suspend handler registered by the Secure Payload 74 * Dispatcher to let it do any book-keeping. If the handler encounters an 75 * error, it's expected to assert within 76 */ 77 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_suspend != NULL)) { 78 psci_spd_pm->svc_suspend(max_off_lvl); 79 } 80 81 #if !HW_ASSISTED_COHERENCY 82 /* 83 * Plat. management: Allow the platform to perform any early 84 * actions required to power down the CPU. This might be useful for 85 * HW_ASSISTED_COHERENCY = 0 platforms that can safely perform these 86 * actions with data caches enabled. 87 */ 88 if (psci_plat_pm_ops->pwr_domain_suspend_pwrdown_early != NULL) { 89 psci_plat_pm_ops->pwr_domain_suspend_pwrdown_early(state_info); 90 } 91 #endif 92 /* 93 * Arch. management. Initiate power down sequence. 94 */ 95 psci_pwrdown_cpu_start(max_off_lvl); 96 } 97 98 /******************************************************************************* 99 * Top level handler which is called when a cpu wants to suspend its execution. 100 * It is assumed that along with suspending the cpu power domain, power domains 101 * at higher levels until the target power level will be suspended as well. It 102 * coordinates with the platform to negotiate the target state for each of 103 * the power domain level till the target power domain level. It then performs 104 * generic, architectural, platform setup and state management required to 105 * suspend that power domain level and power domain levels below it. 106 * e.g. For a cpu that's to be suspended, it could mean programming the 107 * power controller whereas for a cluster that's to be suspended, it will call 108 * the platform specific code which will disable coherency at the interconnect 109 * level if the cpu is the last in the cluster and also the program the power 110 * controller. 111 * 112 * All the required parameter checks are performed at the beginning and after 113 * the state transition has been done, no further error is expected and it is 114 * not possible to undo any of the actions taken beyond that point. 115 ******************************************************************************/ 116 int psci_cpu_suspend_start(unsigned int idx, 117 unsigned int end_pwrlvl, 118 psci_power_state_t *state_info, 119 unsigned int is_power_down_state) 120 { 121 int rc = PSCI_E_SUCCESS; 122 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; 123 unsigned int max_off_lvl = 0; 124 125 /* 126 * This function must only be called on platforms where the 127 * CPU_SUSPEND platform hooks have been implemented. 128 */ 129 assert((psci_plat_pm_ops->pwr_domain_suspend != NULL) && 130 (psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)); 131 132 /* Get the parent nodes */ 133 psci_get_parent_pwr_domain_nodes(idx, end_pwrlvl, parent_nodes); 134 135 /* 136 * This function acquires the lock corresponding to each power 137 * level so that by the time all locks are taken, the system topology 138 * is snapshot and state management can be done safely. 139 */ 140 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); 141 142 /* 143 * We check if there are any pending interrupts after the delay 144 * introduced by lock contention to increase the chances of early 145 * detection that a wake-up interrupt has fired. 146 */ 147 if (read_isr_el1() != 0U) { 148 goto suspend_exit; 149 } 150 151 #if PSCI_OS_INIT_MODE 152 if (psci_suspend_mode == OS_INIT) { 153 /* 154 * This function validates the requested state info for 155 * OS-initiated mode. 156 */ 157 rc = psci_validate_state_coordination(idx, end_pwrlvl, state_info); 158 if (rc != PSCI_E_SUCCESS) { 159 goto suspend_exit; 160 } 161 } else { 162 #endif 163 /* 164 * This function is passed the requested state info and 165 * it returns the negotiated state info for each power level upto 166 * the end level specified. 167 */ 168 psci_do_state_coordination(idx, end_pwrlvl, state_info); 169 #if PSCI_OS_INIT_MODE 170 } 171 #endif 172 173 #if PSCI_OS_INIT_MODE 174 if (psci_plat_pm_ops->pwr_domain_validate_suspend != NULL) { 175 rc = psci_plat_pm_ops->pwr_domain_validate_suspend(state_info); 176 if (rc != PSCI_E_SUCCESS) { 177 goto suspend_exit; 178 } 179 } 180 #endif 181 182 /* Update the target state in the power domain nodes */ 183 psci_set_target_local_pwr_states(idx, end_pwrlvl, state_info); 184 185 #if ENABLE_PSCI_STAT 186 /* Update the last cpu for each level till end_pwrlvl */ 187 psci_stats_update_pwr_down(idx, end_pwrlvl, state_info); 188 #endif 189 190 if (is_power_down_state != 0U) { 191 max_off_lvl = psci_find_max_off_lvl(state_info); 192 psci_suspend_to_pwrdown_start(idx, end_pwrlvl, end_pwrlvl, state_info); 193 } 194 195 #if USE_GIC_DRIVER 196 /* turn the GIC off before we hand off to the platform */ 197 gic_cpuif_disable(idx); 198 #endif /* USE_GIC_DRIVER */ 199 200 /* 201 * Plat. management: Allow the platform to perform the 202 * necessary actions to turn off this cpu e.g. set the 203 * platform defined mailbox with the psci entrypoint, 204 * program the power controller etc. 205 */ 206 psci_plat_pm_ops->pwr_domain_suspend(state_info); 207 208 #if ENABLE_PSCI_STAT 209 plat_psci_stat_accounting_start(state_info); 210 #endif 211 212 /* 213 * Release the locks corresponding to each power level in the 214 * reverse order to which they were acquired. 215 */ 216 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); 217 218 #if ENABLE_RUNTIME_INSTRUMENTATION 219 /* 220 * Update the timestamp with cache off. We assume this 221 * timestamp can only be read from the current CPU and the 222 * timestamp cache line will be flushed before return to 223 * normal world on wakeup. 224 */ 225 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 226 RT_INSTR_ENTER_HW_LOW_PWR, 227 PMF_NO_CACHE_MAINT); 228 #endif 229 230 if (is_power_down_state != 0U) { 231 if (psci_plat_pm_ops->pwr_domain_pwr_down != NULL) { 232 /* This function may not return */ 233 psci_plat_pm_ops->pwr_domain_pwr_down(state_info); 234 } 235 236 psci_pwrdown_cpu_end_wakeup(max_off_lvl); 237 } else { 238 /* 239 * We will reach here if only retention/standby states have been 240 * requested at multiple power levels. This means that the cpu 241 * context will be preserved. 242 */ 243 wfi(); 244 } 245 246 #if ENABLE_RUNTIME_INSTRUMENTATION 247 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 248 RT_INSTR_EXIT_HW_LOW_PWR, 249 PMF_NO_CACHE_MAINT); 250 #endif 251 252 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); 253 /* 254 * Find out which retention states this CPU has exited from until the 255 * 'end_pwrlvl'. The exit retention state could be deeper than the entry 256 * state as a result of state coordination amongst other CPUs post wfi. 257 */ 258 psci_get_target_local_pwr_states(idx, end_pwrlvl, state_info); 259 260 #if ENABLE_PSCI_STAT 261 plat_psci_stat_accounting_stop(state_info); 262 psci_stats_update_pwr_up(idx, end_pwrlvl, state_info); 263 #endif 264 265 /* 266 * Waking up means we've retained all context. Call the finishers to put 267 * the system back to a usable state. 268 */ 269 if (is_power_down_state != 0U) { 270 psci_cpu_suspend_to_powerdown_finish(idx, max_off_lvl, state_info, true); 271 } else { 272 psci_cpu_suspend_to_standby_finish(end_pwrlvl, state_info); 273 } 274 275 #if USE_GIC_DRIVER 276 /* Turn GIC on after platform has had a chance to do state management */ 277 gic_cpuif_enable(idx); 278 #endif /* USE_GIC_DRIVER */ 279 280 /* 281 * Set the requested and target state of this CPU and all the higher 282 * power domain levels for this CPU to run. 283 */ 284 psci_set_pwr_domains_to_run(idx, end_pwrlvl); 285 286 suspend_exit: 287 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); 288 289 return rc; 290 } 291 292 /******************************************************************************* 293 * The following functions finish an earlier suspend request. They 294 * are called by the common finisher routine in psci_common.c. The `state_info` 295 * is the psci_power_state from which this CPU has woken up from. 296 ******************************************************************************/ 297 void psci_cpu_suspend_to_powerdown_finish(unsigned int cpu_idx, unsigned int max_off_lvl, const psci_power_state_t *state_info, bool abandon) 298 { 299 unsigned int counter_freq; 300 301 /* Ensure we have been woken up from a suspended state */ 302 assert((psci_get_aff_info_state() == AFF_STATE_ON) && 303 (is_local_state_off( 304 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]) != 0)); 305 306 /* 307 * Plat. management: Perform the platform specific actions 308 * before we change the state of the cpu e.g. enabling the 309 * gic or zeroing the mailbox register. If anything goes 310 * wrong then assert as there is no way to recover from this 311 * situation. 312 */ 313 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); 314 315 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 316 /* Arch. management: Enable the data cache, stack memory maintenance. */ 317 psci_do_pwrup_cache_maintenance(); 318 #endif 319 320 #if USE_GIC_DRIVER 321 /* GIC on after platform has had its say and MMU is on */ 322 gic_cpuif_enable(cpu_idx); 323 #endif /* USE_GIC_DRIVER */ 324 325 if (!abandon) { 326 /* Re-init the cntfrq_el0 register */ 327 counter_freq = plat_get_syscnt_freq2(); 328 write_cntfrq_el0(counter_freq); 329 } 330 331 /* 332 * Call the cpu suspend finish handler registered by the Secure Payload 333 * Dispatcher to let it do any bookeeping. If the handler encounters an 334 * error, it's expected to assert within 335 */ 336 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_suspend_finish != NULL)) { 337 psci_spd_pm->svc_suspend_finish(max_off_lvl, abandon); 338 } 339 340 /* This loses its meaning when not suspending, reset so it's correct for OFF */ 341 psci_set_suspend_pwrlvl(PLAT_MAX_PWR_LVL); 342 343 PUBLISH_EVENT_ARG(psci_suspend_pwrdown_finish, &cpu_idx); 344 } 345