1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/cpa2.h> 30 #include <lib/extensions/debug_v8p9.h> 31 #include <lib/extensions/fgt2.h> 32 #include <lib/extensions/idte3.h> 33 #include <lib/extensions/mpam.h> 34 #include <lib/extensions/pauth.h> 35 #include <lib/extensions/pmuv3.h> 36 #include <lib/extensions/sme.h> 37 #include <lib/extensions/spe.h> 38 #include <lib/extensions/sve.h> 39 #include <lib/extensions/sysreg128.h> 40 #include <lib/extensions/sys_reg_trace.h> 41 #include <lib/extensions/tcr2.h> 42 #include <lib/extensions/trbe.h> 43 #include <lib/extensions/trf.h> 44 #include <lib/utils.h> 45 46 #if ENABLE_FEAT_TWED 47 /* Make sure delay value fits within the range(0-15) */ 48 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 49 #endif /* ENABLE_FEAT_TWED */ 50 51 per_world_context_t per_world_context[CPU_CONTEXT_NUM]; 52 53 static void manage_extensions_nonsecure(cpu_context_t *ctx); 54 static void manage_extensions_secure(cpu_context_t *ctx); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 } 153 154 #if ENABLE_RME && IMAGE_BL31 155 /****************************************************************************** 156 * This function performs initializations that are specific to REALM state 157 * and updates the cpu context specified by 'ctx'. 158 * 159 * NOTE: any changes to this function must be verified by an RMMD maintainer. 160 *****************************************************************************/ 161 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 162 { 163 u_register_t scr_el3; 164 el3_state_t *state; 165 el2_sysregs_t *el2_ctx; 166 167 state = get_el3state_ctx(ctx); 168 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 169 el2_ctx = get_el2_sysregs_ctx(ctx); 170 171 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 172 173 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM); 174 175 /* CSV2 version 2 and above */ 176 if (is_feat_csv2_2_supported()) { 177 /* Enable access to the SCXTNUM_ELx registers. */ 178 scr_el3 |= SCR_EnSCXT_BIT; 179 } 180 181 if (is_feat_sctlr2_supported()) { 182 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 183 * SCTLR2_ELx registers. 184 */ 185 scr_el3 |= SCR_SCTLR2En_BIT; 186 } 187 188 if (is_feat_d128_supported()) { 189 /* 190 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 191 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 192 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 193 */ 194 scr_el3 |= SCR_D128En_BIT; 195 } 196 197 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 198 199 if (is_feat_fgt2_supported()) { 200 fgt2_enable(ctx); 201 } 202 203 if (is_feat_debugv8p9_supported()) { 204 debugv8p9_extended_bp_wp_enable(ctx); 205 } 206 207 if (is_feat_brbe_supported()) { 208 brbe_enable(ctx); 209 } 210 211 /* 212 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 213 */ 214 if (is_feat_sme_supported()) { 215 sme_enable(ctx); 216 } 217 218 if (is_feat_spe_supported()) { 219 spe_disable_realm(ctx); 220 } 221 222 if (is_feat_trbe_supported()) { 223 trbe_disable_realm(ctx); 224 } 225 } 226 #endif /* ENABLE_RME && IMAGE_BL31 */ 227 228 /****************************************************************************** 229 * This function performs initializations that are specific to NON-SECURE state 230 * and updates the cpu context specified by 'ctx'. 231 *****************************************************************************/ 232 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 233 { 234 u_register_t scr_el3; 235 el3_state_t *state; 236 237 state = get_el3state_ctx(ctx); 238 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 239 240 /* SCR_NS: Set the NS bit */ 241 scr_el3 |= SCR_NS_BIT; 242 243 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 244 if (is_feat_mte2_supported()) { 245 scr_el3 |= SCR_ATA_BIT; 246 } 247 248 /* 249 * Pointer Authentication feature, if present, is always enabled by 250 * default for Non secure lower exception levels. We do not have an 251 * explicit flag to set it. To prevent the leakage between the worlds 252 * during world switch, we enable it only for the non-secure world. 253 * 254 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 255 * exception levels of secure and realm worlds. 256 * 257 * If the Secure/realm world wants to use pointer authentication, 258 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 259 * it will be enabled globally for all the contexts. 260 * 261 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 262 * other than EL3 263 * 264 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 265 * than EL3 266 */ 267 if (!is_ctx_pauth_supported()) { 268 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 269 } 270 271 #if HANDLE_EA_EL3_FIRST_NS 272 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 273 scr_el3 |= SCR_EA_BIT; 274 #endif 275 276 #if RAS_TRAP_NS_ERR_REC_ACCESS 277 /* 278 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 279 * and RAS ERX registers from EL1 and EL2(from any security state) 280 * are trapped to EL3. 281 * Set here to trap only for NS EL1/EL2 282 */ 283 scr_el3 |= SCR_TERR_BIT; 284 #endif 285 286 /* CSV2 version 2 and above */ 287 if (is_feat_csv2_2_supported()) { 288 /* Enable access to the SCXTNUM_ELx registers. */ 289 scr_el3 |= SCR_EnSCXT_BIT; 290 } 291 292 #ifdef IMAGE_BL31 293 /* 294 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 295 * indicated by the interrupt routing model for BL31. 296 */ 297 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 298 #endif 299 300 if (is_feat_the_supported()) { 301 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 302 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 303 */ 304 scr_el3 |= SCR_RCWMASKEn_BIT; 305 } 306 307 if (is_feat_sctlr2_supported()) { 308 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 309 * SCTLR2_ELx registers. 310 */ 311 scr_el3 |= SCR_SCTLR2En_BIT; 312 } 313 314 if (is_feat_d128_supported()) { 315 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 316 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 317 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 318 */ 319 scr_el3 |= SCR_D128En_BIT; 320 } 321 322 if (is_feat_fpmr_supported()) { 323 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 324 * register. 325 */ 326 scr_el3 |= SCR_EnFPM_BIT; 327 } 328 329 if (is_feat_aie_supported()) { 330 /* Set the AIEn bit in SCR_EL3 to enable access to (A)MAIR2 331 * system registers from NS world. 332 */ 333 scr_el3 |= SCR_AIEn_BIT; 334 } 335 336 if (is_feat_pfar_supported()) { 337 /* Set the PFAREn bit in SCR_EL3 to enable access to the PFAR 338 * system registers from NS world. 339 */ 340 scr_el3 |= SCR_PFAREn_BIT; 341 } 342 343 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 344 345 /* Initialize EL2 context registers */ 346 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 347 if (is_feat_hcx_supported()) { 348 /* 349 * Initialize register HCRX_EL2 with its init value. 350 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 351 * chance that this can lead to unexpected behavior in lower 352 * ELs that have not been updated since the introduction of 353 * this feature if not properly initialized, especially when 354 * it comes to those bits that enable/disable traps. 355 */ 356 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 357 HCRX_EL2_INIT_VAL); 358 } 359 360 if (is_feat_fgt_supported()) { 361 /* 362 * Initialize HFG*_EL2 registers with a default value so legacy 363 * systems unaware of FEAT_FGT do not get trapped due to their lack 364 * of initialization for this feature. 365 */ 366 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 367 HFGITR_EL2_INIT_VAL); 368 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 369 HFGRTR_EL2_INIT_VAL); 370 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 371 HFGWTR_EL2_INIT_VAL); 372 } 373 #else 374 /* Initialize EL1 context registers */ 375 setup_el1_context(ctx, ep); 376 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 377 378 manage_extensions_nonsecure(ctx); 379 } 380 381 /******************************************************************************* 382 * The following function performs initialization of the cpu_context 'ctx' 383 * for first use that is common to all security states, and sets the 384 * initial entrypoint state as specified by the entry_point_info structure. 385 * 386 * The EE and ST attributes are used to configure the endianness and secure 387 * timer availability for the new execution context. 388 ******************************************************************************/ 389 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 390 { 391 u_register_t scr_el3; 392 u_register_t mdcr_el3; 393 el3_state_t *state; 394 gp_regs_t *gp_regs; 395 396 state = get_el3state_ctx(ctx); 397 398 /* Clear any residual register values from the context */ 399 zeromem(ctx, sizeof(*ctx)); 400 401 /* 402 * The lower-EL context is zeroed so that no stale values leak to a world. 403 * It is assumed that an all-zero lower-EL context is good enough for it 404 * to boot correctly. However, there are very few registers where this 405 * is not true and some values need to be recreated. 406 */ 407 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 408 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 409 410 /* 411 * These bits are set in the gicv3 driver. Losing them (especially the 412 * SRE bit) is problematic for all worlds. Henceforth recreate them. 413 */ 414 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 415 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 416 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 417 418 /* 419 * The actlr_el2 register can be initialized in platform's reset handler 420 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 421 */ 422 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 423 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 424 425 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 426 scr_el3 = SCR_RESET_VAL; 427 428 /* 429 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 430 * EL2, EL1 and EL0 are not trapped to EL3. 431 * 432 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 433 * EL2, EL1 and EL0 are not trapped to EL3. 434 * 435 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 436 * both Security states and both Execution states. 437 * 438 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 439 * Non-secure memory. 440 */ 441 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 442 443 scr_el3 |= SCR_SIF_BIT; 444 445 /* 446 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 447 * Exception level as specified by SPSR. 448 */ 449 if (GET_RW(ep->spsr) == MODE_RW_64) { 450 scr_el3 |= SCR_RW_BIT; 451 } 452 453 /* 454 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 455 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 456 * next mode is Hyp. 457 */ 458 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 459 || ((GET_RW(ep->spsr) != MODE_RW_64) 460 && (GET_M32(ep->spsr) == MODE32_hyp))) { 461 scr_el3 |= SCR_HCE_BIT; 462 } 463 464 /* 465 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 466 * Secure timer registers to EL3, from AArch64 state only, if specified 467 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 468 * bit always behaves as 1 (i.e. secure physical timer register access 469 * is not trapped) 470 */ 471 if (EP_GET_ST(ep->h.attr) != 0U) { 472 scr_el3 |= SCR_ST_BIT; 473 } 474 475 /* 476 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 477 * SCR_EL3.HXEn. 478 */ 479 if (is_feat_hcx_supported()) { 480 scr_el3 |= SCR_HXEn_BIT; 481 } 482 483 /* 484 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 485 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 486 * SCR_EL3.EnAS0. 487 */ 488 if (is_feat_ls64_accdata_supported()) { 489 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 490 } 491 492 /* 493 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 494 * registers are trapped to EL3. 495 */ 496 if (is_feat_rng_trap_supported()) { 497 scr_el3 |= SCR_TRNDR_BIT; 498 } 499 500 #if FAULT_INJECTION_SUPPORT 501 /* Enable fault injection from lower ELs */ 502 scr_el3 |= SCR_FIEN_BIT; 503 #endif 504 505 /* 506 * Enable Pointer Authentication globally for all the worlds. 507 * 508 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 509 * other than EL3 510 * 511 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 512 * than EL3 513 */ 514 if (is_ctx_pauth_supported()) { 515 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 516 } 517 518 /* 519 * SCR_EL3.PIEN: Enable permission indirection and overlay 520 * registers for AArch64 if present. 521 */ 522 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 523 scr_el3 |= SCR_PIEN_BIT; 524 } 525 526 /* SCR_EL3.GCSEn: Enable GCS registers. */ 527 if (is_feat_gcs_supported()) { 528 scr_el3 |= SCR_GCSEn_BIT; 529 } 530 531 /* SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps */ 532 if (is_feat_fgt_supported()) { 533 scr_el3 |= SCR_FGTEN_BIT; 534 } 535 536 /* SCR_EL3.ECVEn: Do not trap the CNTPOFF_EL2 register */ 537 if (is_feat_ecv_supported()) { 538 scr_el3 |= SCR_ECVEN_BIT; 539 } 540 541 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 542 if (is_feat_twed_supported()) { 543 /* Set delay in SCR_EL3 */ 544 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 545 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 546 << SCR_TWEDEL_SHIFT); 547 548 /* Enable WFE delay */ 549 scr_el3 |= SCR_TWEDEn_BIT; 550 } 551 552 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 553 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 554 if (is_feat_sel2_supported()) { 555 scr_el3 |= SCR_EEL2_BIT; 556 } 557 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 558 559 if (is_feat_mec_supported()) { 560 scr_el3 |= SCR_MECEn_BIT; 561 } 562 563 /* 564 * Populate EL3 state so that we've the right context 565 * before doing ERET 566 */ 567 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 568 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 569 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 570 571 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 572 mdcr_el3 = MDCR_EL3_RESET_VAL; 573 574 /* --------------------------------------------------------------------- 575 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 576 * Some fields are architecturally UNKNOWN on reset. 577 * 578 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 579 * Debug exceptions, other than Breakpoint Instruction exceptions, are 580 * disabled from all ELs in Secure state. 581 * 582 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 583 * privileged debug from S-EL1. 584 * 585 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 586 * access to the powerdown debug registers do not trap to EL3. 587 * 588 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 589 * debug registers, other than those registers that are controlled by 590 * MDCR_EL3.TDOSA. 591 */ 592 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 593 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 594 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 595 596 #if IMAGE_BL31 597 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 598 if (is_feat_trf_supported()) { 599 trf_enable(ctx); 600 } 601 602 if (is_feat_tcr2_supported()) { 603 tcr2_enable(ctx); 604 } 605 606 pmuv3_enable(ctx); 607 608 if (is_feat_idte3_supported()) { 609 idte3_enable(ctx); 610 } 611 612 #if CTX_INCLUDE_EL2_REGS && IMAGE_BL31 613 /* 614 * Initialize SCTLR_EL2 context register with reset value. 615 */ 616 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 617 #endif /* CTX_INCLUDE_EL2_REGS */ 618 #endif /* IMAGE_BL31 */ 619 620 /* 621 * Store the X0-X7 value from the entrypoint into the context 622 * Use memcpy as we are in control of the layout of the structures 623 */ 624 gp_regs = get_gpregs_ctx(ctx); 625 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 626 } 627 628 /******************************************************************************* 629 * Context management library initialization routine. This library is used by 630 * runtime services to share pointers to 'cpu_context' structures for secure 631 * non-secure and realm states. Management of the structures and their associated 632 * memory is not done by the context management library e.g. the PSCI service 633 * manages the cpu context used for entry from and exit to the non-secure state. 634 * The Secure payload dispatcher service manages the context(s) corresponding to 635 * the secure state. It also uses this library to get access to the non-secure 636 * state cpu context pointers. 637 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 638 * which will be used for programming an entry into a lower EL. The same context 639 * will be used to save state upon exception entry from that EL. 640 ******************************************************************************/ 641 void __init cm_init(void) 642 { 643 /* 644 * The context management library has only global data to initialize, but 645 * that will be done when the BSS is zeroed out. 646 */ 647 } 648 649 /******************************************************************************* 650 * This is the high-level function used to initialize the cpu_context 'ctx' for 651 * first use. It performs initializations that are common to all security states 652 * and initializations specific to the security state specified in 'ep' 653 ******************************************************************************/ 654 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 655 { 656 size_t security_state; 657 658 assert(ctx != NULL); 659 660 /* 661 * Perform initializations that are common 662 * to all security states 663 */ 664 setup_context_common(ctx, ep); 665 666 security_state = GET_SECURITY_STATE(ep->h.attr); 667 668 /* Perform security state specific initializations */ 669 switch (security_state) { 670 case SECURE: 671 setup_secure_context(ctx, ep); 672 break; 673 #if ENABLE_RME && IMAGE_BL31 674 case REALM: 675 setup_realm_context(ctx, ep); 676 break; 677 #endif 678 case NON_SECURE: 679 setup_ns_context(ctx, ep); 680 break; 681 default: 682 ERROR("Invalid security state\n"); 683 panic(); 684 break; 685 } 686 } 687 688 /******************************************************************************* 689 * Enable architecture extensions for EL3 execution. This function only updates 690 * registers in-place which are expected to either never change or be 691 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 692 ******************************************************************************/ 693 void __no_pauth cm_manage_extensions_el3(unsigned int my_idx) 694 { 695 if (is_feat_pauth_supported()) { 696 pauth_init_enable_el3(); 697 } 698 699 #if IMAGE_BL31 700 if (is_feat_sve_supported()) { 701 sve_init_el3(); 702 } 703 704 if (is_feat_amu_supported()) { 705 amu_init_el3(my_idx); 706 } 707 708 if (is_feat_sme_supported()) { 709 sme_init_el3(); 710 } 711 712 if (is_feat_fgwte3_supported()) { 713 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 714 } 715 716 if (is_feat_mpam_supported()) { 717 mpam_init_el3(); 718 } 719 720 if (is_feat_cpa2_supported()) { 721 cpa2_enable_el3(); 722 } 723 724 pmuv3_init_el3(); 725 #endif /* IMAGE_BL31 */ 726 } 727 728 /****************************************************************************** 729 * Function to initialise the registers with the RESET values in the context 730 * memory, which are maintained per world. 731 ******************************************************************************/ 732 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 733 { 734 per_world_ctx->ctx_cptr_el3 = CPTR_EL3_RESET_VAL; 735 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 736 } 737 738 /******************************************************************************* 739 * Initialise per_world_context for Non-Secure world. 740 * This function enables the architecture extensions, which have same value 741 * across the cores for the non-secure world. 742 ******************************************************************************/ 743 static void manage_extensions_nonsecure_per_world(void) 744 { 745 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 746 747 #if IMAGE_BL31 748 if (is_feat_sme_supported()) { 749 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 750 } 751 752 if (is_feat_sve_supported()) { 753 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 754 } 755 756 if (is_feat_amu_supported()) { 757 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 758 } 759 760 if (is_feat_sys_reg_trace_supported()) { 761 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 762 } 763 764 if (is_feat_mpam_supported()) { 765 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 766 } 767 768 if (is_feat_idte3_supported()) { 769 idte3_init_cached_idregs_per_world(CPU_CONTEXT_NS); 770 } 771 #endif /* IMAGE_BL31 */ 772 } 773 774 /******************************************************************************* 775 * Initialise per_world_context for Secure world. 776 * This function enables the architecture extensions, which have same value 777 * across the cores for the secure world. 778 ******************************************************************************/ 779 static void manage_extensions_secure_per_world(void) 780 { 781 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 782 783 #if IMAGE_BL31 784 if (is_feat_sme_supported()) { 785 786 if (ENABLE_SME_FOR_SWD) { 787 /* 788 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 789 * SME, SVE, and FPU/SIMD context properly managed. 790 */ 791 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 792 } else { 793 /* 794 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 795 * world can safely use the associated registers. 796 */ 797 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 798 } 799 } 800 if (is_feat_sve_supported()) { 801 if (ENABLE_SVE_FOR_SWD) { 802 /* 803 * Enable SVE and FPU in secure context, SPM must ensure 804 * that the SVE and FPU register contexts are properly managed. 805 */ 806 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 807 } else { 808 /* 809 * Disable SVE and FPU in secure context so non-secure world 810 * can safely use them. 811 */ 812 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 813 } 814 } 815 816 /* NS can access this but Secure shouldn't */ 817 if (is_feat_sys_reg_trace_supported()) { 818 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 819 } 820 821 if (is_feat_idte3_supported()) { 822 idte3_init_cached_idregs_per_world(CPU_CONTEXT_SECURE); 823 } 824 #endif /* IMAGE_BL31 */ 825 } 826 827 static void manage_extensions_realm_per_world(void) 828 { 829 #if ENABLE_RME && IMAGE_BL31 830 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 831 832 if (is_feat_sve_supported()) { 833 /* 834 * Enable SVE and FPU in realm context when it is enabled for NS. 835 * Realm manager must ensure that the SVE and FPU register 836 * contexts are properly managed. 837 */ 838 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 839 } 840 841 /* NS can access this but Realm shouldn't */ 842 if (is_feat_sys_reg_trace_supported()) { 843 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 844 } 845 846 /* 847 * If SME/SME2 is supported and enabled for NS world, then disable trapping 848 * of SME instructions for Realm world. RMM will save/restore required 849 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 850 */ 851 if (is_feat_sme_supported()) { 852 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 853 } 854 855 /* 856 * If FEAT_MPAM is supported and enabled, then disable trapping access 857 * to the MPAM registers for Realm world. Instead, RMM will configure 858 * the access to be trapped by itself so it can inject undefined aborts 859 * back to the Realm. 860 */ 861 if (is_feat_mpam_supported()) { 862 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 863 } 864 865 if (is_feat_idte3_supported()) { 866 idte3_init_cached_idregs_per_world(CPU_CONTEXT_REALM); 867 } 868 #endif /* ENABLE_RME && IMAGE_BL31 */ 869 } 870 871 void cm_manage_extensions_per_world(void) 872 { 873 manage_extensions_nonsecure_per_world(); 874 manage_extensions_secure_per_world(); 875 manage_extensions_realm_per_world(); 876 } 877 878 void cm_init_percpu_once_regs(void) 879 { 880 #if IMAGE_BL31 881 if (is_feat_idte3_supported()) { 882 idte3_init_percpu_once_regs(CPU_CONTEXT_NS); 883 idte3_init_percpu_once_regs(CPU_CONTEXT_SECURE); 884 #if ENABLE_RME 885 idte3_init_percpu_once_regs(CPU_CONTEXT_REALM); 886 #endif /* ENABLE_RME */ 887 } 888 #endif /* IMAGE_BL31 */ 889 } 890 891 /******************************************************************************* 892 * Enable architecture extensions on first entry to Non-secure world. 893 ******************************************************************************/ 894 static void manage_extensions_nonsecure(cpu_context_t *ctx) 895 { 896 #if IMAGE_BL31 897 /* NOTE: registers are not context switched */ 898 if (is_feat_amu_supported()) { 899 amu_enable(ctx); 900 } 901 902 if (is_feat_sme_supported()) { 903 sme_enable(ctx); 904 } 905 906 if (is_feat_fgt2_supported()) { 907 fgt2_enable(ctx); 908 } 909 910 if (is_feat_debugv8p9_supported()) { 911 debugv8p9_extended_bp_wp_enable(ctx); 912 } 913 914 if (is_feat_spe_supported()) { 915 spe_enable_ns(ctx); 916 } 917 918 if (is_feat_trbe_supported()) { 919 if (check_if_trbe_disable_affected_core()) { 920 trbe_disable_ns(ctx); 921 } else { 922 trbe_enable_ns(ctx); 923 } 924 } 925 926 if (is_feat_brbe_supported()) { 927 brbe_enable(ctx); 928 } 929 #endif /* IMAGE_BL31 */ 930 } 931 932 #if INIT_UNUSED_NS_EL2 933 /******************************************************************************* 934 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 935 * world when EL2 is empty and unused. 936 ******************************************************************************/ 937 static void manage_extensions_nonsecure_el2_unused(void) 938 { 939 #if IMAGE_BL31 940 if (is_feat_spe_supported()) { 941 spe_init_el2_unused(); 942 } 943 944 if (is_feat_amu_supported()) { 945 amu_init_el2_unused(); 946 } 947 948 if (is_feat_mpam_supported()) { 949 mpam_init_el2_unused(); 950 } 951 952 if (is_feat_trbe_supported()) { 953 trbe_init_el2_unused(); 954 } 955 956 if (is_feat_sys_reg_trace_supported()) { 957 sys_reg_trace_init_el2_unused(); 958 } 959 960 if (is_feat_trf_supported()) { 961 trf_init_el2_unused(); 962 } 963 964 pmuv3_init_el2_unused(); 965 966 if (is_feat_sve_supported()) { 967 sve_init_el2_unused(); 968 } 969 970 if (is_feat_sme_supported()) { 971 sme_init_el2_unused(); 972 } 973 974 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 975 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 976 } 977 978 if (is_feat_pauth_supported()) { 979 pauth_enable_el2(); 980 } 981 #endif /* IMAGE_BL31 */ 982 } 983 #endif /* INIT_UNUSED_NS_EL2 */ 984 985 /******************************************************************************* 986 * Enable architecture extensions on first entry to Secure world. 987 ******************************************************************************/ 988 static void manage_extensions_secure(cpu_context_t *ctx) 989 { 990 #if IMAGE_BL31 991 if (is_feat_sme_supported()) { 992 if (ENABLE_SME_FOR_SWD) { 993 /* 994 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 995 * must ensure SME, SVE, and FPU/SIMD context properly managed. 996 */ 997 sme_init_el3(); 998 sme_enable(ctx); 999 } else { 1000 /* 1001 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 1002 * world can safely use the associated registers. 1003 */ 1004 sme_disable(ctx); 1005 } 1006 } 1007 1008 if (is_feat_spe_supported()) { 1009 spe_disable_secure(ctx); 1010 } 1011 1012 if (is_feat_trbe_supported()) { 1013 trbe_disable_secure(ctx); 1014 } 1015 #endif /* IMAGE_BL31 */ 1016 } 1017 1018 /******************************************************************************* 1019 * The following function initializes the cpu_context for the current CPU 1020 * for first use, and sets the initial entrypoint state as specified by the 1021 * entry_point_info structure. 1022 ******************************************************************************/ 1023 void cm_init_my_context(const entry_point_info_t *ep) 1024 { 1025 cpu_context_t *ctx; 1026 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 1027 cm_setup_context(ctx, ep); 1028 } 1029 1030 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 1031 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 1032 { 1033 #if INIT_UNUSED_NS_EL2 1034 u_register_t hcr_el2 = HCR_RESET_VAL; 1035 u_register_t mdcr_el2; 1036 u_register_t scr_el3; 1037 1038 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1039 1040 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1041 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1042 hcr_el2 |= HCR_RW_BIT; 1043 } 1044 1045 write_hcr_el2(hcr_el2); 1046 1047 /* 1048 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1049 * All fields have architecturally UNKNOWN reset values. 1050 */ 1051 write_cptr_el2(CPTR_EL2_RESET_VAL); 1052 1053 /* 1054 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1055 * reset and are set to zero except for field(s) listed below. 1056 * 1057 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1058 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1059 * 1060 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1061 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1062 */ 1063 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1064 1065 /* 1066 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1067 * UNKNOWN value. 1068 */ 1069 write_cntvoff_el2(0); 1070 1071 /* 1072 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1073 * respectively. 1074 */ 1075 write_vpidr_el2(read_midr_el1()); 1076 write_vmpidr_el2(read_mpidr_el1()); 1077 1078 /* 1079 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1080 * 1081 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1082 * translation is disabled, cache maintenance operations depend on the 1083 * VMID. 1084 * 1085 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1086 * disabled. 1087 */ 1088 write_vttbr_el2(VTTBR_RESET_VAL & 1089 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1090 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1091 1092 /* 1093 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1094 * Some fields are architecturally UNKNOWN on reset. 1095 * 1096 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1097 * register accesses to the Debug ROM registers are not trapped to EL2. 1098 * 1099 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1100 * accesses to the powerdown debug registers are not trapped to EL2. 1101 * 1102 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1103 * debug registers do not trap to EL2. 1104 * 1105 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1106 * EL2. 1107 */ 1108 mdcr_el2 = MDCR_EL2_RESET_VAL & 1109 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1110 MDCR_EL2_TDE_BIT); 1111 1112 write_mdcr_el2(mdcr_el2); 1113 1114 /* 1115 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1116 * 1117 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1118 * EL1 accesses to System registers do not trap to EL2. 1119 */ 1120 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1121 1122 /* 1123 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1124 * reset. 1125 * 1126 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1127 * and prevent timer interrupts. 1128 */ 1129 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1130 1131 manage_extensions_nonsecure_el2_unused(); 1132 #endif /* INIT_UNUSED_NS_EL2 */ 1133 } 1134 1135 /******************************************************************************* 1136 * Prepare the CPU system registers for first entry into realm, secure, or 1137 * normal world. 1138 * 1139 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1140 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1141 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1142 * For all entries, the EL1 registers are initialized from the cpu_context 1143 ******************************************************************************/ 1144 void cm_prepare_el3_exit(size_t security_state) 1145 { 1146 u_register_t sctlr_el2, scr_el3; 1147 cpu_context_t *ctx = cm_get_context(security_state); 1148 1149 assert(ctx != NULL); 1150 1151 if (security_state == NON_SECURE) { 1152 uint64_t el2_implemented = el_implemented(2); 1153 1154 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1155 CTX_SCR_EL3); 1156 1157 if (el2_implemented != EL_IMPL_NONE) { 1158 1159 /* 1160 * If context is not being used for EL2, initialize 1161 * HCRX_EL2 with its init value here. 1162 */ 1163 if (is_feat_hcx_supported()) { 1164 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1165 } 1166 1167 /* 1168 * Initialize Fine-grained trap registers introduced 1169 * by FEAT_FGT so all traps are initially disabled when 1170 * switching to EL2 or a lower EL, preventing undesired 1171 * behavior. 1172 */ 1173 if (is_feat_fgt_supported()) { 1174 /* 1175 * Initialize HFG*_EL2 registers with a default 1176 * value so legacy systems unaware of FEAT_FGT 1177 * do not get trapped due to their lack of 1178 * initialization for this feature. 1179 */ 1180 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1181 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1182 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1183 } 1184 1185 /* Condition to ensure EL2 is being used. */ 1186 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1187 /* Initialize SCTLR_EL2 register with reset value. */ 1188 sctlr_el2 = SCTLR_EL2_RES1; 1189 1190 /* 1191 * If workaround of errata 764081 for Cortex-A75 1192 * is used then set SCTLR_EL2.IESB to enable 1193 * Implicit Error Synchronization Barrier. 1194 */ 1195 if (errata_a75_764081_applies()) { 1196 sctlr_el2 |= SCTLR_IESB_BIT; 1197 } 1198 1199 write_sctlr_el2(sctlr_el2); 1200 } else { 1201 /* 1202 * (scr_el3 & SCR_HCE_BIT==0) 1203 * EL2 implemented but unused. 1204 */ 1205 init_nonsecure_el2_unused(ctx); 1206 } 1207 } 1208 1209 if (is_feat_fgwte3_supported()) { 1210 /* 1211 * TCR_EL3 and ACTLR_EL3 could be overwritten 1212 * by platforms and hence is locked a bit late. 1213 */ 1214 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1215 } 1216 } 1217 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1 1218 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1219 cm_el1_sysregs_context_restore(security_state); 1220 #endif 1221 cm_set_next_eret_context(security_state); 1222 } 1223 1224 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1225 1226 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1227 { 1228 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1229 if (is_feat_amu_supported()) { 1230 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1231 } 1232 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1233 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1234 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1235 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1236 } 1237 1238 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1239 { 1240 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1241 if (is_feat_amu_supported()) { 1242 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1243 } 1244 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1245 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1246 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1247 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1248 } 1249 1250 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1251 { 1252 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1253 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1254 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1255 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1256 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1257 } 1258 1259 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1260 { 1261 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1262 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1263 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1264 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1265 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1266 } 1267 1268 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1269 { 1270 u_register_t mpam_idr = read_mpamidr_el1(); 1271 1272 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1273 1274 /* 1275 * The context registers that we intend to save would be part of the 1276 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1277 */ 1278 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1279 return; 1280 } 1281 1282 /* 1283 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1284 * MPAMIDR_HAS_HCR_BIT == 1. 1285 */ 1286 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1287 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1288 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1289 1290 /* 1291 * The number of MPAMVPM registers is implementation defined, their 1292 * number is stored in the MPAMIDR_EL1 register. 1293 */ 1294 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1295 case 7: 1296 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1297 __fallthrough; 1298 case 6: 1299 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1300 __fallthrough; 1301 case 5: 1302 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1303 __fallthrough; 1304 case 4: 1305 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1306 __fallthrough; 1307 case 3: 1308 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1309 __fallthrough; 1310 case 2: 1311 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1312 __fallthrough; 1313 case 1: 1314 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1315 break; 1316 } 1317 } 1318 1319 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1320 { 1321 u_register_t mpam_idr = read_mpamidr_el1(); 1322 1323 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1324 1325 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1326 return; 1327 } 1328 1329 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1330 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1331 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1332 1333 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1334 case 7: 1335 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1336 __fallthrough; 1337 case 6: 1338 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1339 __fallthrough; 1340 case 5: 1341 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1342 __fallthrough; 1343 case 4: 1344 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1345 __fallthrough; 1346 case 3: 1347 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1348 __fallthrough; 1349 case 2: 1350 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1351 __fallthrough; 1352 case 1: 1353 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1354 break; 1355 } 1356 } 1357 1358 /* --------------------------------------------------------------------------- 1359 * The following registers are not added: 1360 * ICH_AP0R<n>_EL2 1361 * ICH_AP1R<n>_EL2 1362 * ICH_LR<n>_EL2 1363 * 1364 * NOTE: For a system with S-EL2 present but not enabled, accessing 1365 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1366 * SCR_EL3.NS = 1 before accessing this register. 1367 * --------------------------------------------------------------------------- 1368 */ 1369 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1370 { 1371 u_register_t scr_el3 = read_scr_el3(); 1372 1373 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1374 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1375 #else 1376 write_scr_el3(scr_el3 | SCR_NS_BIT); 1377 isb(); 1378 1379 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1380 1381 write_scr_el3(scr_el3); 1382 isb(); 1383 #endif 1384 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1385 1386 if (errata_ich_vmcr_el2_applies()) { 1387 if (security_state == SECURE) { 1388 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1389 } else { 1390 write_scr_el3(scr_el3 | SCR_NS_BIT); 1391 } 1392 isb(); 1393 } 1394 1395 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1396 1397 if (errata_ich_vmcr_el2_applies()) { 1398 write_scr_el3(scr_el3); 1399 isb(); 1400 } 1401 } 1402 1403 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1404 { 1405 u_register_t scr_el3 = read_scr_el3(); 1406 1407 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1408 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1409 #else 1410 write_scr_el3(scr_el3 | SCR_NS_BIT); 1411 isb(); 1412 1413 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1414 1415 write_scr_el3(scr_el3); 1416 isb(); 1417 #endif 1418 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1419 1420 if (errata_ich_vmcr_el2_applies()) { 1421 if (security_state == SECURE) { 1422 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1423 } else { 1424 write_scr_el3(scr_el3 | SCR_NS_BIT); 1425 } 1426 isb(); 1427 } 1428 1429 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1430 1431 if (errata_ich_vmcr_el2_applies()) { 1432 write_scr_el3(scr_el3); 1433 isb(); 1434 } 1435 } 1436 1437 /* ----------------------------------------------------- 1438 * The following registers are not added: 1439 * AMEVCNTVOFF0<n>_EL2 1440 * AMEVCNTVOFF1<n>_EL2 1441 * ----------------------------------------------------- 1442 */ 1443 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1444 { 1445 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1446 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1447 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1448 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1449 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1450 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1451 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1452 if (CTX_INCLUDE_AARCH32_REGS) { 1453 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1454 } 1455 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1456 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1457 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1458 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1459 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1460 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1461 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1462 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1463 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1464 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1465 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1466 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1467 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1468 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1469 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1470 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1471 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1472 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1473 1474 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1475 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1476 } 1477 1478 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1479 { 1480 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1481 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1482 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1483 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1484 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1485 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1486 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1487 if (CTX_INCLUDE_AARCH32_REGS) { 1488 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1489 } 1490 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1491 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1492 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1493 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1494 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1495 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1496 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1497 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1498 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1499 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1500 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1501 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1502 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1503 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1504 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1505 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1506 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1507 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1508 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1509 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1510 } 1511 1512 /******************************************************************************* 1513 * Save EL2 sysreg context 1514 ******************************************************************************/ 1515 void cm_el2_sysregs_context_save(uint32_t security_state) 1516 { 1517 cpu_context_t *ctx; 1518 el2_sysregs_t *el2_sysregs_ctx; 1519 1520 ctx = cm_get_context(security_state); 1521 assert(ctx != NULL); 1522 1523 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1524 1525 el2_sysregs_context_save_common(el2_sysregs_ctx); 1526 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1527 1528 if (is_feat_mte2_supported()) { 1529 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1530 } 1531 1532 if (is_feat_mpam_supported()) { 1533 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1534 } 1535 1536 if (is_feat_fgt_supported()) { 1537 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1538 } 1539 1540 if (is_feat_fgt2_supported()) { 1541 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1542 } 1543 1544 if (is_feat_ecv_v2_supported()) { 1545 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1546 } 1547 1548 if (is_feat_vhe_supported()) { 1549 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1550 read_contextidr_el2()); 1551 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1552 } 1553 1554 if (is_feat_ras_supported()) { 1555 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1556 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1557 } 1558 1559 if (is_feat_nv2_supported()) { 1560 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1561 } 1562 1563 if (is_feat_trf_supported()) { 1564 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1565 } 1566 1567 if (is_feat_csv2_2_supported()) { 1568 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1569 read_scxtnum_el2()); 1570 } 1571 1572 if (is_feat_hcx_supported()) { 1573 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1574 } 1575 1576 if (is_feat_tcr2_supported()) { 1577 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1578 } 1579 1580 if (is_feat_s1pie_supported()) { 1581 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1582 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1583 } 1584 1585 if (is_feat_s1poe_supported()) { 1586 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1587 } 1588 1589 if (is_feat_brbe_supported()) { 1590 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1591 } 1592 1593 if (is_feat_s2pie_supported()) { 1594 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1595 } 1596 1597 if (is_feat_gcs_supported()) { 1598 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1599 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1600 } 1601 1602 if (is_feat_sctlr2_supported()) { 1603 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1604 } 1605 } 1606 1607 /******************************************************************************* 1608 * Restore EL2 sysreg context 1609 ******************************************************************************/ 1610 void cm_el2_sysregs_context_restore(uint32_t security_state) 1611 { 1612 cpu_context_t *ctx; 1613 el2_sysregs_t *el2_sysregs_ctx; 1614 1615 ctx = cm_get_context(security_state); 1616 assert(ctx != NULL); 1617 1618 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1619 1620 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1621 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1622 1623 if (is_feat_mte2_supported()) { 1624 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1625 } 1626 1627 if (is_feat_mpam_supported()) { 1628 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1629 } 1630 1631 if (is_feat_fgt_supported()) { 1632 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1633 } 1634 1635 if (is_feat_fgt2_supported()) { 1636 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1637 } 1638 1639 if (is_feat_ecv_v2_supported()) { 1640 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1641 } 1642 1643 if (is_feat_vhe_supported()) { 1644 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1645 contextidr_el2)); 1646 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1647 } 1648 1649 if (is_feat_ras_supported()) { 1650 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1651 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1652 } 1653 1654 if (is_feat_nv2_supported()) { 1655 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1656 } 1657 1658 if (is_feat_trf_supported()) { 1659 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1660 } 1661 1662 if (is_feat_csv2_2_supported()) { 1663 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1664 scxtnum_el2)); 1665 } 1666 1667 if (is_feat_hcx_supported()) { 1668 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1669 } 1670 1671 if (is_feat_tcr2_supported()) { 1672 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1673 } 1674 1675 if (is_feat_s1pie_supported()) { 1676 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1677 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1678 } 1679 1680 if (is_feat_s1poe_supported()) { 1681 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1682 } 1683 1684 if (is_feat_s2pie_supported()) { 1685 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1686 } 1687 1688 if (is_feat_gcs_supported()) { 1689 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1690 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1691 } 1692 1693 if (is_feat_sctlr2_supported()) { 1694 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1695 } 1696 1697 if (is_feat_brbe_supported()) { 1698 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1699 } 1700 } 1701 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1702 1703 /******************************************************************************* 1704 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1705 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1706 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1707 * cm_prepare_el3_exit function. 1708 ******************************************************************************/ 1709 void cm_prepare_el3_exit_ns(void) 1710 { 1711 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1712 #if ENABLE_ASSERTIONS 1713 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1714 assert(ctx != NULL); 1715 1716 /* Assert that EL2 is used. */ 1717 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1718 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1719 (el_implemented(2U) != EL_IMPL_NONE)); 1720 #endif /* ENABLE_ASSERTIONS */ 1721 1722 /* Restore EL2 sysreg contexts */ 1723 cm_el2_sysregs_context_restore(NON_SECURE); 1724 cm_set_next_eret_context(NON_SECURE); 1725 #else 1726 cm_prepare_el3_exit(NON_SECURE); 1727 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1728 } 1729 1730 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1731 /******************************************************************************* 1732 * The next set of six functions are used by runtime services to save and restore 1733 * EL1 context on the 'cpu_context' structure for the specified security state. 1734 ******************************************************************************/ 1735 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1736 { 1737 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1738 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1739 1740 #if (!ERRATA_SPECULATIVE_AT) 1741 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1742 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1743 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1744 1745 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1746 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1747 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1748 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1749 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1750 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1751 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1752 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1753 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1754 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1755 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1756 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1757 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1758 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1759 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1760 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1761 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1762 1763 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1764 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1765 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1766 1767 if (CTX_INCLUDE_AARCH32_REGS) { 1768 /* Save Aarch32 registers */ 1769 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1770 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1771 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1772 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1773 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1774 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1775 } 1776 1777 /* Save counter-timer kernel control register */ 1778 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1779 #if NS_TIMER_SWITCH 1780 /* Save NS Timer registers */ 1781 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1782 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1783 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1784 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1785 #endif 1786 1787 if (is_feat_mte2_supported()) { 1788 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1789 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1790 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1791 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1792 } 1793 1794 if (is_feat_ras_supported()) { 1795 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1796 } 1797 1798 if (is_feat_s1pie_supported()) { 1799 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1800 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1801 } 1802 1803 if (is_feat_s1poe_supported()) { 1804 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1805 } 1806 1807 if (is_feat_s2poe_supported()) { 1808 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1809 } 1810 1811 if (is_feat_tcr2_supported()) { 1812 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1813 } 1814 1815 if (is_feat_trf_supported()) { 1816 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1817 } 1818 1819 if (is_feat_csv2_2_supported()) { 1820 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1821 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1822 } 1823 1824 if (is_feat_gcs_supported()) { 1825 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1826 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1827 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1828 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1829 } 1830 1831 if (is_feat_the_supported()) { 1832 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1833 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1834 } 1835 1836 if (is_feat_sctlr2_supported()) { 1837 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1838 } 1839 1840 if (is_feat_ls64_accdata_supported()) { 1841 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1842 } 1843 } 1844 1845 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1846 { 1847 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1848 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1849 1850 #if (!ERRATA_SPECULATIVE_AT) 1851 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1852 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1853 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1854 1855 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1856 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1857 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1858 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1859 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1860 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1861 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1862 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1863 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1864 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1865 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1866 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1867 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1868 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1869 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1870 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1871 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1872 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1873 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1874 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1875 1876 if (CTX_INCLUDE_AARCH32_REGS) { 1877 /* Restore Aarch32 registers */ 1878 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1879 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1880 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1881 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1882 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1883 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1884 } 1885 1886 /* Restore counter-timer kernel control register */ 1887 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1888 #if NS_TIMER_SWITCH 1889 /* Restore NS Timer registers */ 1890 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1891 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1892 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1893 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1894 #endif 1895 1896 if (is_feat_mte2_supported()) { 1897 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1898 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1899 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1900 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1901 } 1902 1903 if (is_feat_ras_supported()) { 1904 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1905 } 1906 1907 if (is_feat_s1pie_supported()) { 1908 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1909 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1910 } 1911 1912 if (is_feat_s1poe_supported()) { 1913 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1914 } 1915 1916 if (is_feat_s2poe_supported()) { 1917 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1918 } 1919 1920 if (is_feat_tcr2_supported()) { 1921 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1922 } 1923 1924 if (is_feat_trf_supported()) { 1925 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1926 } 1927 1928 if (is_feat_csv2_2_supported()) { 1929 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1930 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1931 } 1932 1933 if (is_feat_gcs_supported()) { 1934 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1935 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1936 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1937 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1938 } 1939 1940 if (is_feat_the_supported()) { 1941 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1942 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1943 } 1944 1945 if (is_feat_sctlr2_supported()) { 1946 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1947 } 1948 1949 if (is_feat_ls64_accdata_supported()) { 1950 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1951 } 1952 } 1953 1954 /******************************************************************************* 1955 * The next couple of functions are used by runtime services to save and restore 1956 * EL1 context on the 'cpu_context' structure for the specified security state. 1957 ******************************************************************************/ 1958 void cm_el1_sysregs_context_save(uint32_t security_state) 1959 { 1960 cpu_context_t *ctx; 1961 1962 ctx = cm_get_context(security_state); 1963 assert(ctx != NULL); 1964 1965 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1966 1967 #if IMAGE_BL31 1968 if (security_state == SECURE) { 1969 PUBLISH_EVENT(cm_exited_secure_world); 1970 } else { 1971 PUBLISH_EVENT(cm_exited_normal_world); 1972 } 1973 #endif 1974 } 1975 1976 void cm_el1_sysregs_context_restore(uint32_t security_state) 1977 { 1978 cpu_context_t *ctx; 1979 1980 ctx = cm_get_context(security_state); 1981 assert(ctx != NULL); 1982 1983 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1984 1985 #if IMAGE_BL31 1986 if (security_state == SECURE) { 1987 PUBLISH_EVENT(cm_entering_secure_world); 1988 } else { 1989 PUBLISH_EVENT(cm_entering_normal_world); 1990 } 1991 #endif 1992 } 1993 1994 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1995 1996 /******************************************************************************* 1997 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1998 * given security state with the given entrypoint 1999 ******************************************************************************/ 2000 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 2001 { 2002 cpu_context_t *ctx; 2003 el3_state_t *state; 2004 2005 ctx = cm_get_context(security_state); 2006 assert(ctx != NULL); 2007 2008 /* Populate EL3 state so that ERET jumps to the correct entry */ 2009 state = get_el3state_ctx(ctx); 2010 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2011 } 2012 2013 /******************************************************************************* 2014 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2015 * pertaining to the given security state 2016 ******************************************************************************/ 2017 void cm_set_elr_spsr_el3(uint32_t security_state, 2018 uintptr_t entrypoint, uint32_t spsr) 2019 { 2020 cpu_context_t *ctx; 2021 el3_state_t *state; 2022 2023 ctx = cm_get_context(security_state); 2024 assert(ctx != NULL); 2025 2026 /* Populate EL3 state so that ERET jumps to the correct entry */ 2027 state = get_el3state_ctx(ctx); 2028 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2029 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2030 } 2031 2032 /******************************************************************************* 2033 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2034 * pertaining to the given security state using the value and bit position 2035 * specified in the parameters. It preserves all other bits. 2036 ******************************************************************************/ 2037 void cm_write_scr_el3_bit(uint32_t security_state, 2038 uint32_t bit_pos, 2039 uint32_t value) 2040 { 2041 cpu_context_t *ctx; 2042 el3_state_t *state; 2043 u_register_t scr_el3; 2044 2045 ctx = cm_get_context(security_state); 2046 assert(ctx != NULL); 2047 2048 /* Ensure that the bit position is a valid one */ 2049 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2050 2051 /* Ensure that the 'value' is only a bit wide */ 2052 assert(value <= 1U); 2053 2054 /* 2055 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2056 * and set it to its new value. 2057 */ 2058 state = get_el3state_ctx(ctx); 2059 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2060 scr_el3 &= ~(1UL << bit_pos); 2061 scr_el3 |= (u_register_t)value << bit_pos; 2062 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2063 } 2064 2065 /******************************************************************************* 2066 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2067 * given security state. 2068 ******************************************************************************/ 2069 u_register_t cm_get_scr_el3(uint32_t security_state) 2070 { 2071 const cpu_context_t *ctx; 2072 const el3_state_t *state; 2073 2074 ctx = cm_get_context(security_state); 2075 assert(ctx != NULL); 2076 2077 /* Populate EL3 state so that ERET jumps to the correct entry */ 2078 state = get_el3state_ctx(ctx); 2079 return read_ctx_reg(state, CTX_SCR_EL3); 2080 } 2081 2082 /******************************************************************************* 2083 * This function is used to program the context that's used for exception 2084 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2085 * the required security state 2086 ******************************************************************************/ 2087 void cm_set_next_eret_context(uint32_t security_state) 2088 { 2089 cpu_context_t *ctx; 2090 2091 ctx = cm_get_context(security_state); 2092 assert(ctx != NULL); 2093 2094 cm_set_next_context(ctx); 2095 } 2096