| e1c5026a | 13-Mar-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Use proper note and warning annotations
The documentation contains plenty of notes and warnings. Enable
special rendering of these blocks by converting the note prefix
into a .. note:: annotati
doc: Use proper note and warning annotations
The documentation contains plenty of notes and warnings. Enable
special rendering of these blocks by converting the note prefix
into a .. note:: annotation.
Change-Id: I34e26ca6bf313d335672ab6c2645741900338822
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 29c02529 | 13-Mar-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Set correct syntax highlighting style
Several code blocks do not specify a language for syntax
highlighting. This results in Sphinx using a default highlighter
which is Python.
This patch adds
doc: Set correct syntax highlighting style
Several code blocks do not specify a language for syntax
highlighting. This results in Sphinx using a default highlighter
which is Python.
This patch adds the correct language to each code block that doesn't
already specify it.
Change-Id: Icce1949aabfdc11a334a42d49edf55fa673cddc3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 57354abb | 07-Mar-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Remove per-page contents lists
These are no longer needed as there will always be a table of contents
rendered to the left of every page.
Some of these lists can be quite long and, when openin
doc: Remove per-page contents lists
These are no longer needed as there will always be a table of contents
rendered to the left of every page.
Some of these lists can be quite long and, when opening a page, the
reader sees nothing but a huge list of contents! After this patch,
the document contents are front-and-centre and the contents are
nicely rendered in the sidebar without duplication.
Change-Id: I444754d548ec91d00f2b04e861de8dde8856aa62
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 24dba2b3 | 22-May-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Reformat platform port documents
The platform port documents are not very standardised right now and
they don't integrate properly into the document tree so:
1) Make sure each port has a prope
doc: Reformat platform port documents
The platform port documents are not very standardised right now and
they don't integrate properly into the document tree so:
1) Make sure each port has a proper name and title (incl. owner)
2) Correct use of headings, subheadings, etc in each port
3) Resolve any naming conflicts between documents
Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 40d553cf | 11-Feb-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Move documents into subdirectories
This change creates the following directories under docs/
in order to provide a grouping for the content:
- components
- design
- getting_started
- perf
- pr
doc: Move documents into subdirectories
This change creates the following directories under docs/
in order to provide a grouping for the content:
- components
- design
- getting_started
- perf
- process
In each of these directories an index.rst file is created
and this serves as an index / landing page for each of the
groups when the pages are compiled. Proper layout of the
top-level table of contents relies on this directory/index
structure.
Without this patch it is possible to build the documents
correctly with Sphinx but the output looks messy because
there is no overall hierarchy.
Change-Id: I3c9f4443ec98571a56a6edf775f2c8d74d7f429f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 3fa9dec4 | 10-Apr-2019 |
kenny liang <kenny.liang@mediatek.com> |
Initialize platform for MediaTek mt8183
- Add basic platform setup
- Add generic CPU helper functions
- Add delay timer platform implementation
- Use TI 16550 uart driver
Change-Id: I1c29569c68fe9f
Initialize platform for MediaTek mt8183
- Add basic platform setup
- Add generic CPU helper functions
- Add delay timer platform implementation
- Use TI 16550 uart driver
Change-Id: I1c29569c68fe9fca5e10e88a22a29690bab7141f
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
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| f15e7adb | 29-Apr-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "avenger96" into integration
* changes:
fdts: Fix DTC warnings for STM32MP1 platform
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
stm32mp1: Add A
Merge changes from topic "avenger96" into integration
* changes:
fdts: Fix DTC warnings for STM32MP1 platform
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
stm32mp1: Add Avenger96 board support
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| f657fa99 | 26-Apr-2019 |
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
Since STM32MP1 platform supports different boards, it is necessary
to build for a particular board. With the current instructions,
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
Since STM32MP1 platform supports different boards, it is necessary
to build for a particular board. With the current instructions, the
user has to modify the DTB_FILE_NAME variable in platform.mk for
building for a particular board, but this can be avoided by passing
the appropriate board DTB name via DTB_FILE_NAME make variable.
Hence document the same in platform doc.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: I16797e7256c7eb699a7b8846356fe430d0fe0aa1
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| 55617251 | 19-Apr-2019 |
Heiko Stuebner <heiko@sntech.de> |
rockchip: document platform
This adds a rockchip.rst to docs/plat documenting the general
approach to using the Rockchip ATF platforms together with the
supported bootloaders and also adds myself as
rockchip: document platform
This adds a rockchip.rst to docs/plat documenting the general
approach to using the Rockchip ATF platforms together with the
supported bootloaders and also adds myself as maintainer after
making sure Tony Xie is ok with that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Idce53d15eff4ac6de05bbb35d86e57ed50d0cbb9
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| 1989a19c | 19-Apr-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: add OP-TEE support
Support booting OP-TEE as BL32 boot stage and secure runtime
service.
OP-TEE executes in internal RAM and uses a secure DDR area to store
the pager pagestore. Memory ma
stm32mp1: add OP-TEE support
Support booting OP-TEE as BL32 boot stage and secure runtime
service.
OP-TEE executes in internal RAM and uses a secure DDR area to store
the pager pagestore. Memory mapping and TZC are configured accordingly
prior OP-TEE boot. OP-TEE image is expected in OP-TEE v2 format where
a header file describes the effective boot images. This change
post processes header file content to get OP-TEE load addresses
and set OP-TEE boot arguments.
Change-Id: I02ef8b915e4be3e95b27029357d799d70e01cd44
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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|
| 9b5a8aa5 | 01-Apr-2019 |
Remi Pommarel <repk@triplefau.lt> |
plat: gxl: Add documentation on building GXL image
Also adds a maintainer for GXL.
Signed-off-by: Remi Pommarel <repk@triplefau.lt> |
| 179f82a2 | 06-Mar-2019 |
Jacky Bai <ping.bai@nxp.com> |
plat: imx8m: Add the basic support for imx8mm
The i.MX8M Mini is new SOC of the i.MX8M family. it is
focused on delivering the latest and greatest video and
audio experience combining state-of-the-a
plat: imx8m: Add the basic support for imx8mm
The i.MX8M Mini is new SOC of the i.MX8M family. it is
focused on delivering the latest and greatest video and
audio experience combining state-of-the-art media-specific
features with high-performance processing while optimized
for lowest power consumption. The i.MX 8M Mini Media Applications
Processor is 14nm FinFET product of the growing i.MX8M family
targeting the consumer & industrial market. It is built in 14LPP
to achieve both high performance and low power consumption
and relies on a powerful fully coherent core complex based on
a quad Cortex-A53 cluster with video and graphics accelerators
this patch add the basic support for i.MX8MM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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|
| a4acc7f1 | 01-Mar-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1751 from vwadekar/tegra-scatter-file-support
Tegra scatter file support |
| c2ad38ce | 11-Jan-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: Support for scatterfile for the BL31 image
This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.
In order to enable
Tegra: Support for scatterfile for the BL31 image
This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.
In order to enable the scatterfile usage the following changes
have been made:
* provide mapping for ld.S symbols in bl_common.h
* include bl_common.h from all the affected files
* update the makefile rules to use the scatterfile and armlink
to compile BL31
* update pubsub.h to add sections to the scatterfile
NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.
Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 39718ea5 | 27-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1834 from thloh85-intel/s10_bl31
plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform |
| 1cf55aba | 26-Feb-2019 |
Tien Hock, Loh <tien.hock.loh@intel.com> |
plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox
plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
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|
| ab3d2247 | 22-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1836 from Yann-lms/docs_and_m4
Update documentation for STM32MP1 and add Cortex-M4 support |
| 774b4a81 | 20-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
docs: stm32mp1: add links to documentation
A link to st.com page describing STM32MP1 is added.
Add the information about Cortex-M4 embedded in STM32MP1.
Correct typo for u-boot command.
Change-Id:
docs: stm32mp1: add links to documentation
A link to st.com page describing STM32MP1 is added.
Add the information about Cortex-M4 embedded in STM32MP1.
Correct typo for u-boot command.
Change-Id: Ie900f6ee59461c5e7ad8a8b06854abaf41fca3ce
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| 5dbc783a | 05-Feb-2019 |
Usama Arif <usama.arif@arm.com> |
Documentation for Versatile Express Fixed Virtual Platforms
This documentation contains information about the boot sequence,
code location and build procedure for fvp_ve platform.
Change-Id: I33990
Documentation for Versatile Express Fixed Virtual Platforms
This documentation contains information about the boot sequence,
code location and build procedure for fvp_ve platform.
Change-Id: I339903f663cc625cfabc75ed8e4accb8b2c3917c
Signed-off-by: Usama Arif <usama.arif@arm.com>
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| dd4e9a7d | 08-Feb-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Fix broken external links
Using Sphinx linkcheck on the TF-A docs revealed some broken
or permanently-redirected links. These have been updated where
possible.
Change-Id: Ie1fead47972ede333197
doc: Fix broken external links
Using Sphinx linkcheck on the TF-A docs revealed some broken
or permanently-redirected links. These have been updated where
possible.
Change-Id: Ie1fead47972ede3331973759b50ee466264bd2ee
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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|
| a474d3d7 | 03-Jan-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
docs: add Tegra186 information to nvidia-tegra.rst
This patch adds information about the Tegra186 platforms to the
docs.
Change-Id: I69525c60a0126030dc15505ec7f02ccf8250be6f
Signed-off-by: Varun Wa
docs: add Tegra186 information to nvidia-tegra.rst
This patch adds information about the Tegra186 platforms to the
docs.
Change-Id: I69525c60a0126030dc15505ec7f02ccf8250be6f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| ae478c26 | 23-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1768 from bryanodonoghue/integration+linaro_warp7-tbb
Integration+linaro warp7 tbb |
| 087cf68a | 21-Jul-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: lib: library for profiling the cold boot path
The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) i
Tegra: lib: library for profiling the cold boot path
The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) is allocated and the base address is passed to
the EL3 firmware.
This patch adds a library to allow the platform code to store the
tag:timestamp pair to the shared memory. The tegra platform code
then uses the `record` method to add timestamps.
Original change by Akshay Sharan <asharan@nvidia.com>
Change-Id: Idbbef9c83ed84a508b04d85a6637775960dc94ba
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 31e4c20d | 26-Oct-2018 |
Bryan O'Donoghue <bryan.odonoghue@linaro.org> |
docs: warp7: Update WaRP7 description for TBB
This patch updates the WaRP7 build descriptions for booting WaRP7 in
Trusted Board Boot mode. TBB is the only mode we really intend to support
for this
docs: warp7: Update WaRP7 description for TBB
This patch updates the WaRP7 build descriptions for booting WaRP7 in
Trusted Board Boot mode. TBB is the only mode we really intend to support
for this board so rather than maintain documentation for the old way of
doing it, this patch updates the description for TBB mode only.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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| b495791b | 23-Nov-2016 |
Harvey Hsieh <hhsieh@nvidia.com> |
Tegra: support to set the L2 ECC and Parity enable bit
This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader se
Tegra: support to set the L2 ECC and Parity enable bit
This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader sets this flag value for the platform.
* with some coverity fix:
MISRA C-2012 Directive 4.6
MISRA C-2012 Rule 2.5
MISRA C-2012 Rule 10.3
MISRA C-2012 Rule 10.4
Change-Id: Id7303bbbdc290b52919356c31625847b8904b073
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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