1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stddef.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <bl31/bl31.h> 17 #include <common/bl_common.h> 18 #include <common/debug.h> 19 #include <cortex_a53.h> 20 #include <cortex_a57.h> 21 #include <denver.h> 22 #include <drivers/console.h> 23 #include <lib/mmio.h> 24 #include <lib/utils.h> 25 #include <lib/utils_def.h> 26 #include <plat/common/platform.h> 27 28 #include <memctrl.h> 29 #include <profiler.h> 30 #include <tegra_def.h> 31 #include <tegra_platform.h> 32 #include <tegra_private.h> 33 34 /* length of Trusty's input parameters (in bytes) */ 35 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 36 37 extern void memcpy16(void *dest, const void *src, unsigned int length); 38 39 /******************************************************************************* 40 * Declarations of linker defined symbols which will help us find the layout 41 * of trusted SRAM 42 ******************************************************************************/ 43 44 IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); 45 IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END); 46 IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE); 47 IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END); 48 IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START); 49 IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END); 50 51 extern uint64_t tegra_bl31_phys_base; 52 extern uint64_t tegra_console_base; 53 54 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 55 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 56 .tzdram_size = TZDRAM_SIZE 57 }; 58 static unsigned long bl32_mem_size; 59 static unsigned long bl32_boot_params; 60 61 /******************************************************************************* 62 * This variable holds the non-secure image entry address 63 ******************************************************************************/ 64 extern uint64_t ns_image_entrypoint; 65 66 /******************************************************************************* 67 * The following platform setup functions are weakly defined. They 68 * provide typical implementations that will be overridden by a SoC. 69 ******************************************************************************/ 70 #pragma weak plat_early_platform_setup 71 #pragma weak plat_get_bl31_params 72 #pragma weak plat_get_bl31_plat_params 73 74 void plat_early_platform_setup(void) 75 { 76 ; /* do nothing */ 77 } 78 79 struct tegra_bl31_params *plat_get_bl31_params(void) 80 { 81 return NULL; 82 } 83 84 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 85 { 86 return NULL; 87 } 88 89 /******************************************************************************* 90 * Return a pointer to the 'entry_point_info' structure of the next image for 91 * security state specified. BL33 corresponds to the non-secure image type 92 * while BL32 corresponds to the secure image type. 93 ******************************************************************************/ 94 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 95 { 96 entry_point_info_t *ep = NULL; 97 98 /* return BL32 entry point info if it is valid */ 99 if (type == NON_SECURE) { 100 ep = &bl33_image_ep_info; 101 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) { 102 ep = &bl32_image_ep_info; 103 } 104 105 return ep; 106 } 107 108 /******************************************************************************* 109 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 110 * passes this platform specific information. 111 ******************************************************************************/ 112 plat_params_from_bl2_t *bl31_get_plat_params(void) 113 { 114 return &plat_bl31_params_from_bl2; 115 } 116 117 /******************************************************************************* 118 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 119 * info. 120 ******************************************************************************/ 121 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 122 u_register_t arg2, u_register_t arg3) 123 { 124 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; 125 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; 126 image_info_t bl32_img_info = { {0} }; 127 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 128 uint32_t console_clock; 129 int32_t ret; 130 131 /* 132 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 133 * there's no argument to relay from a previous bootloader. Platforms 134 * might use custom ways to get arguments, so provide handlers which 135 * they can override. 136 */ 137 if (arg_from_bl2 == NULL) { 138 arg_from_bl2 = plat_get_bl31_params(); 139 } 140 if (plat_params == NULL) { 141 plat_params = plat_get_bl31_plat_params(); 142 } 143 144 /* 145 * Copy BL3-3, BL3-2 entry point information. 146 * They are stored in Secure RAM, in BL2's address space. 147 */ 148 assert(arg_from_bl2 != NULL); 149 assert(arg_from_bl2->bl33_ep_info != NULL); 150 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 151 152 if (arg_from_bl2->bl32_ep_info != NULL) { 153 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 154 bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0; 155 bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2; 156 } 157 158 /* 159 * Parse platform specific parameters - TZDRAM aperture base and size 160 */ 161 assert(plat_params != NULL); 162 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 163 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 164 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 165 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis; 166 167 /* 168 * It is very important that we run either from TZDRAM or TZSRAM base. 169 * Add an explicit check here. 170 */ 171 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && 172 (TEGRA_TZRAM_BASE != BL31_BASE)) { 173 panic(); 174 } 175 176 /* 177 * Reference clock used by the FPGAs is a lot slower. 178 */ 179 if (tegra_platform_is_fpga()) { 180 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ; 181 } else { 182 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ; 183 } 184 185 /* 186 * Get the base address of the UART controller to be used for the 187 * console 188 */ 189 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 190 191 if (tegra_console_base != 0U) { 192 /* 193 * Configure the UART port to be used as the console 194 */ 195 (void)console_init(tegra_console_base, console_clock, 196 TEGRA_CONSOLE_BAUDRATE); 197 } 198 199 /* 200 * The previous bootloader passes the base address of the shared memory 201 * location to store the boot profiler logs. Sanity check the 202 * address and initilise the profiler library, if it looks ok. 203 */ 204 if (plat_params->boot_profiler_shmem_base != 0ULL) { 205 206 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base, 207 PROFILER_SIZE_BYTES); 208 if (ret == (int32_t)0) { 209 210 /* store the membase for the profiler lib */ 211 plat_bl31_params_from_bl2.boot_profiler_shmem_base = 212 plat_params->boot_profiler_shmem_base; 213 214 /* initialise the profiler library */ 215 boot_profiler_init(plat_params->boot_profiler_shmem_base, 216 TEGRA_TMRUS_BASE); 217 } 218 } 219 220 /* 221 * Add timestamp for platform early setup entry. 222 */ 223 boot_profiler_add_record("[TF] early setup entry"); 224 225 /* 226 * Initialize delay timer 227 */ 228 tegra_delay_timer_init(); 229 230 /* 231 * Do initial security configuration to allow DRAM/device access. 232 */ 233 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 234 (uint32_t)plat_bl31_params_from_bl2.tzdram_size); 235 236 /* 237 * The previous bootloader might not have placed the BL32 image 238 * inside the TZDRAM. We check the BL32 image info to find out 239 * the base/PC values and relocate the image if necessary. 240 */ 241 if (arg_from_bl2->bl32_image_info != NULL) { 242 243 bl32_img_info = *arg_from_bl2->bl32_image_info; 244 245 /* Relocate BL32 if it resides outside of the TZDRAM */ 246 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 247 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 248 plat_bl31_params_from_bl2.tzdram_size; 249 bl32_start = bl32_img_info.image_base; 250 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 251 252 assert(tzdram_end > tzdram_start); 253 assert(bl32_end > bl32_start); 254 assert(bl32_image_ep_info.pc > tzdram_start); 255 assert(bl32_image_ep_info.pc < tzdram_end); 256 257 /* relocate BL32 */ 258 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) { 259 260 INFO("Relocate BL32 to TZDRAM\n"); 261 262 (void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 263 (void *)(uintptr_t)bl32_start, 264 bl32_img_info.image_size); 265 266 /* clean up non-secure intermediate buffer */ 267 zeromem((void *)(uintptr_t)bl32_start, 268 bl32_img_info.image_size); 269 } 270 } 271 272 /* Early platform setup for Tegra SoCs */ 273 plat_early_platform_setup(); 274 275 /* 276 * Add timestamp for platform early setup exit. 277 */ 278 boot_profiler_add_record("[TF] early setup exit"); 279 280 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", 281 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) 282 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); 283 } 284 285 #ifdef SPD_trusty 286 void plat_trusty_set_boot_args(aapcs64_params_t *args) 287 { 288 args->arg0 = bl32_mem_size; 289 args->arg1 = bl32_boot_params; 290 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 291 292 /* update EKS size */ 293 if (args->arg4 != 0U) { 294 args->arg2 = args->arg4; 295 } 296 } 297 #endif 298 299 /******************************************************************************* 300 * Initialize the gic, configure the SCR. 301 ******************************************************************************/ 302 void bl31_platform_setup(void) 303 { 304 /* 305 * Add timestamp for platform setup entry. 306 */ 307 boot_profiler_add_record("[TF] plat setup entry"); 308 309 /* Initialize the gic cpu and distributor interfaces */ 310 plat_gic_setup(); 311 312 /* 313 * Setup secondary CPU POR infrastructure. 314 */ 315 plat_secondary_setup(); 316 317 /* 318 * Initial Memory Controller configuration. 319 */ 320 tegra_memctrl_setup(); 321 322 /* 323 * Set up the TZRAM memory aperture to allow only secure world 324 * access 325 */ 326 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 327 328 /* 329 * Add timestamp for platform setup exit. 330 */ 331 boot_profiler_add_record("[TF] plat setup exit"); 332 333 INFO("BL3-1: Tegra platform setup complete\n"); 334 } 335 336 /******************************************************************************* 337 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 338 ******************************************************************************/ 339 void bl31_plat_runtime_setup(void) 340 { 341 /* 342 * During boot, USB3 and flash media (SDMMC/SATA) devices need 343 * access to IRAM. Because these clients connect to the MC and 344 * do not have a direct path to the IRAM, the MC implements AHB 345 * redirection during boot to allow path to IRAM. In this mode 346 * accesses to a programmed memory address aperture are directed 347 * to the AHB bus, allowing access to the IRAM. This mode must be 348 * disabled before we jump to the non-secure world. 349 */ 350 tegra_memctrl_disable_ahb_redirection(); 351 352 /* 353 * Add final timestamp before exiting BL31. 354 */ 355 boot_profiler_add_record("[TF] bl31 exit"); 356 boot_profiler_deinit(); 357 } 358 359 /******************************************************************************* 360 * Perform the very early platform specific architectural setup here. At the 361 * moment this only intializes the mmu in a quick and dirty way. 362 ******************************************************************************/ 363 void bl31_plat_arch_setup(void) 364 { 365 uint64_t rw_start = BL31_RW_START; 366 uint64_t rw_size = BL31_RW_END - BL31_RW_START; 367 uint64_t rodata_start = BL31_RODATA_BASE; 368 uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 369 uint64_t code_base = TEXT_START; 370 uint64_t code_size = TEXT_END - TEXT_START; 371 const mmap_region_t *plat_mmio_map = NULL; 372 #if USE_COHERENT_MEM 373 uint32_t coh_start, coh_size; 374 #endif 375 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 376 377 /* 378 * Add timestamp for arch setup entry. 379 */ 380 boot_profiler_add_record("[TF] arch setup entry"); 381 382 /* add memory regions */ 383 mmap_add_region(rw_start, rw_start, 384 rw_size, 385 MT_MEMORY | MT_RW | MT_SECURE); 386 mmap_add_region(rodata_start, rodata_start, 387 rodata_size, 388 MT_RO_DATA | MT_SECURE); 389 mmap_add_region(code_base, code_base, 390 code_size, 391 MT_CODE | MT_SECURE); 392 393 /* map TZDRAM used by BL31 as coherent memory */ 394 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 395 mmap_add_region(params_from_bl2->tzdram_base, 396 params_from_bl2->tzdram_base, 397 BL31_SIZE, 398 MT_DEVICE | MT_RW | MT_SECURE); 399 } 400 401 #if USE_COHERENT_MEM 402 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 403 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 404 405 mmap_add_region(coh_start, coh_start, 406 coh_size, 407 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE); 408 #endif 409 410 /* map on-chip free running uS timer */ 411 mmap_add_region(page_align(TEGRA_TMRUS_BASE, 0), 412 page_align(TEGRA_TMRUS_BASE, 0), 413 TEGRA_TMRUS_SIZE, 414 (uint8_t)MT_DEVICE | (uint8_t)MT_RO | (uint8_t)MT_SECURE); 415 416 /* add MMIO space */ 417 plat_mmio_map = plat_get_mmio_map(); 418 if (plat_mmio_map != NULL) { 419 mmap_add(plat_mmio_map); 420 } else { 421 WARN("MMIO map not available\n"); 422 } 423 424 /* set up translation tables */ 425 init_xlat_tables(); 426 427 /* enable the MMU */ 428 enable_mmu_el3(0); 429 430 /* 431 * Add timestamp for arch setup exit. 432 */ 433 boot_profiler_add_record("[TF] arch setup exit"); 434 435 INFO("BL3-1: Tegra: MMU enabled\n"); 436 } 437 438 /******************************************************************************* 439 * Check if the given NS DRAM range is valid 440 ******************************************************************************/ 441 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 442 { 443 uint64_t end = base + size_in_bytes - U(1); 444 int32_t ret = 0; 445 446 /* 447 * Check if the NS DRAM address is valid 448 */ 449 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) || 450 (end > TEGRA_DRAM_END)) { 451 452 ERROR("NS address is out-of-bounds!\n"); 453 ret = -EFAULT; 454 } 455 456 /* 457 * TZDRAM aperture contains the BL31 and BL32 images, so we need 458 * to check if the NS DRAM range overlaps the TZDRAM aperture. 459 */ 460 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) { 461 ERROR("NS address overlaps TZDRAM!\n"); 462 ret = -ENOTSUP; 463 } 464 465 /* valid NS address */ 466 return ret; 467 } 468