1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/arm/board/common/v2m_def.h> 11 #include <plat/arm/common/arm_def.h> 12 #include <plat/arm/css/common/css_def.h> 13 14 /* UART related constants */ 15 #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 16 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 17 18 #define PLAT_ARM_RUN_UART_BASE 0x2A410000 19 #define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000 20 21 #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 22 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 23 24 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 25 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 26 27 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 28 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) 29 30 #if CSS_USE_SCMI_SDS_DRIVER 31 #define N1SDP_SCMI_PAYLOAD_BASE 0x45400000 32 #else 33 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 34 #endif 35 36 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 37 #define PLAT_ARM_MAX_BL31_SIZE 0X20000 38 39 40 /******************************************************************************* 41 * N1SDP topology related constants 42 ******************************************************************************/ 43 #define N1SDP_MAX_CPUS_PER_CLUSTER 2 44 #define PLAT_ARM_CLUSTER_COUNT 2 45 #define N1SDP_MAX_PE_PER_CPU 1 46 47 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ 48 N1SDP_MAX_CPUS_PER_CLUSTER * \ 49 N1SDP_MAX_PE_PER_CPU) 50 51 /* System power domain level */ 52 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 53 54 /* 55 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 56 * plat_arm_mmap array defined for each BL stage. 57 */ 58 #define PLAT_ARM_MMAP_ENTRIES 3 59 #define MAX_XLAT_TABLES 4 60 61 #define PLATFORM_STACK_SIZE 0x400 62 63 #define PLAT_ARM_NSTIMER_FRAME_ID 0 64 #define PLAT_CSS_MHU_BASE 0x45000000 65 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 66 #define PLAT_MAX_PWR_LVL 1 67 68 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 69 CSS_IRQ_MHU 70 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 71 72 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 73 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 74 75 76 #define N1SDP_DEVICE_BASE (0x20000000) 77 #define N1SDP_DEVICE_SIZE (0x30000000) 78 #define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ 79 N1SDP_DEVICE_BASE, \ 80 N1SDP_DEVICE_SIZE, \ 81 MT_DEVICE | MT_RW | MT_SECURE) 82 83 /* GIC related constants */ 84 #define PLAT_ARM_GICD_BASE 0x30000000 85 #define PLAT_ARM_GICC_BASE 0x2C000000 86 #define PLAT_ARM_GICR_BASE 0x300C0000 87 88 /* Platform ID address */ 89 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 90 91 /* Secure Watchdog Constants */ 92 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 93 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 94 95 #endif /* PLATFORM_DEF_H */ 96