1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MCE apertures used by the ARI interface 14 * 15 * Aperture 0 - Cpu0 (ARM Cortex A-57) 16 * Aperture 1 - Cpu1 (ARM Cortex A-57) 17 * Aperture 2 - Cpu2 (ARM Cortex A-57) 18 * Aperture 3 - Cpu3 (ARM Cortex A-57) 19 * Aperture 4 - Cpu4 (Denver15) 20 * Aperture 5 - Cpu5 (Denver15) 21 ******************************************************************************/ 22 #define MCE_ARI_APERTURE_0_OFFSET U(0x0) 23 #define MCE_ARI_APERTURE_1_OFFSET U(0x10000) 24 #define MCE_ARI_APERTURE_2_OFFSET U(0x20000) 25 #define MCE_ARI_APERTURE_3_OFFSET U(0x30000) 26 #define MCE_ARI_APERTURE_4_OFFSET U(0x40000) 27 #define MCE_ARI_APERTURE_5_OFFSET U(0x50000) 28 #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET 29 30 /* number of apertures */ 31 #define MCE_ARI_APERTURES_MAX U(6) 32 33 /* each ARI aperture is 64KB */ 34 #define MCE_ARI_APERTURE_SIZE U(0x10000) 35 36 /******************************************************************************* 37 * CPU core id macros for the MCE_ONLINE_CORE ARI 38 ******************************************************************************/ 39 #define MCE_CORE_ID_MAX U(8) 40 #define MCE_CORE_ID_MASK U(0x7) 41 42 /******************************************************************************* 43 * These values are used by the PSCI implementation during the `CPU_SUSPEND` 44 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 45 * parameter. 46 ******************************************************************************/ 47 #define PSTATE_ID_CORE_IDLE U(6) 48 #define PSTATE_ID_CORE_POWERDN U(7) 49 #define PSTATE_ID_SOC_POWERDN U(2) 50 51 /******************************************************************************* 52 * Platform power states (used by PSCI framework) 53 * 54 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 55 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 56 ******************************************************************************/ 57 #define PLAT_MAX_RET_STATE U(1) 58 #define PLAT_MAX_OFF_STATE U(8) 59 60 /******************************************************************************* 61 * Secure IRQ definitions 62 ******************************************************************************/ 63 #define TEGRA186_TOP_WDT_IRQ U(49) 64 #define TEGRA186_AON_WDT_IRQ U(50) 65 66 #define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */ 67 68 /******************************************************************************* 69 * Tegra Miscellanous register constants 70 ******************************************************************************/ 71 #define TEGRA_MISC_BASE U(0x00100000) 72 #define HARDWARE_REVISION_OFFSET U(0x4) 73 74 #define MISCREG_PFCFG U(0x200C) 75 76 /******************************************************************************* 77 * Tegra TSA Controller constants 78 ******************************************************************************/ 79 #define TEGRA_TSA_BASE U(0x02400000) 80 81 /******************************************************************************* 82 * TSA configuration registers 83 ******************************************************************************/ 84 #define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010) 85 #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100) 86 #define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038) 87 #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100) 88 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010) 89 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100) 90 #define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008) 91 #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100) 92 #define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008) 93 #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100) 94 #define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018) 95 #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100) 96 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018) 97 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100) 98 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028) 99 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100) 100 #define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018) 101 #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100) 102 #define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008) 103 #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100) 104 #define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018) 105 #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100) 106 #define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028) 107 #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100) 108 #define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038) 109 #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100) 110 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008) 111 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100) 112 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018) 113 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100) 114 115 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11) 116 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11) 117 118 /******************************************************************************* 119 * Tegra General Purpose Centralised DMA constants 120 ******************************************************************************/ 121 #define TEGRA_GPCDMA_BASE ULL(0x2610000) 122 123 /******************************************************************************* 124 * Tegra Memory Controller constants 125 ******************************************************************************/ 126 #define TEGRA_MC_STREAMID_BASE U(0x02C00000) 127 #define TEGRA_MC_BASE U(0x02C10000) 128 129 /* General Security Carveout register macros */ 130 #define MC_GSC_CONFIG_REGS_SIZE U(0x40) 131 #define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) 132 #define MC_GSC_ENABLE_TZ_LOCK_BIT (ULL(1) << 0) 133 #define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) 134 #define MC_GSC_BASE_LO_SHIFT U(12) 135 #define MC_GSC_BASE_LO_MASK U(0xFFFFF) 136 #define MC_GSC_BASE_HI_SHIFT U(0) 137 #define MC_GSC_BASE_HI_MASK U(3) 138 139 /* TZDRAM carveout configuration registers */ 140 #define MC_SECURITY_CFG0_0 U(0x70) 141 #define MC_SECURITY_CFG1_0 U(0x74) 142 #define MC_SECURITY_CFG3_0 U(0x9BC) 143 144 /* Video Memory carveout configuration registers */ 145 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 146 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 147 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64C) 148 149 /* 150 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 151 * non-overlapping Video memory region 152 */ 153 #define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) 154 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) 155 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) 156 #define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) 157 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) 158 159 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 160 #define MC_TZRAM_CARVEOUT_CFG U(0x2190) 161 #define MC_TZRAM_BASE_LO U(0x2194) 162 #define MC_TZRAM_BASE_HI U(0x2198) 163 #define MC_TZRAM_SIZE U(0x219C) 164 #define MC_TZRAM_CLIENT_ACCESS_CFG0 U(0x21A0) 165 166 /******************************************************************************* 167 * Tegra UART Controller constants 168 ******************************************************************************/ 169 #define TEGRA_UARTA_BASE U(0x03100000) 170 #define TEGRA_UARTB_BASE U(0x03110000) 171 #define TEGRA_UARTC_BASE U(0x0C280000) 172 #define TEGRA_UARTD_BASE U(0x03130000) 173 #define TEGRA_UARTE_BASE U(0x03140000) 174 #define TEGRA_UARTF_BASE U(0x03150000) 175 #define TEGRA_UARTG_BASE U(0x0C290000) 176 177 /******************************************************************************* 178 * Tegra Fuse Controller related constants 179 ******************************************************************************/ 180 #define TEGRA_FUSE_BASE U(0x03820000) 181 #define OPT_SUBREVISION U(0x248) 182 #define SUBREVISION_MASK U(0xFF) 183 184 /******************************************************************************* 185 * GICv2 & interrupt handling related constants 186 ******************************************************************************/ 187 #define TEGRA_GICD_BASE U(0x03881000) 188 #define TEGRA_GICC_BASE U(0x03882000) 189 190 /******************************************************************************* 191 * Security Engine related constants 192 ******************************************************************************/ 193 #define TEGRA_SE0_BASE U(0x03AC0000) 194 #define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) 195 #define TEGRA_PKA1_BASE U(0x03AD0000) 196 #define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144) 197 #define TEGRA_RNG1_BASE U(0x03AE0000) 198 #define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) 199 200 /******************************************************************************* 201 * Tegra Clock and Reset Controller constants 202 ******************************************************************************/ 203 #define TEGRA_CAR_RESET_BASE U(0x05000000) 204 #define TEGRA_GPU_RESET_REG_OFFSET U(0x30) 205 #define GPU_RESET_BIT (U(1) << 0) 206 #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) 207 #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) 208 209 /******************************************************************************* 210 * Tegra micro-seconds timer constants 211 ******************************************************************************/ 212 #define TEGRA_TMRUS_BASE U(0x0C2E0000) 213 #define TEGRA_TMRUS_SIZE U(0x1000) 214 215 /******************************************************************************* 216 * Tegra Power Mgmt Controller constants 217 ******************************************************************************/ 218 #define TEGRA_PMC_BASE U(0x0C360000) 219 220 /******************************************************************************* 221 * Tegra scratch registers constants 222 ******************************************************************************/ 223 #define TEGRA_SCRATCH_BASE U(0x0C390000) 224 #define SECURE_SCRATCH_RSV1_LO U(0x658) 225 #define SECURE_SCRATCH_RSV1_HI U(0x65C) 226 #define SECURE_SCRATCH_RSV6 U(0x680) 227 #define SECURE_SCRATCH_RSV11_LO U(0x6A8) 228 #define SECURE_SCRATCH_RSV11_HI U(0x6AC) 229 #define SECURE_SCRATCH_RSV53_LO U(0x7F8) 230 #define SECURE_SCRATCH_RSV53_HI U(0x7FC) 231 #define SECURE_SCRATCH_RSV54_HI U(0x804) 232 #define SECURE_SCRATCH_RSV55_LO U(0x808) 233 #define SECURE_SCRATCH_RSV55_HI U(0x80C) 234 235 /******************************************************************************* 236 * Tegra Memory Mapped Control Register Access constants 237 ******************************************************************************/ 238 #define TEGRA_MMCRAB_BASE U(0x0E000000) 239 240 /******************************************************************************* 241 * Tegra Memory Mapped Activity Monitor Register Access constants 242 ******************************************************************************/ 243 #define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000) 244 #define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000) 245 246 /******************************************************************************* 247 * Tegra SMMU Controller constants 248 ******************************************************************************/ 249 #define TEGRA_SMMU0_BASE U(0x12000000) 250 251 /******************************************************************************* 252 * Tegra TZRAM constants 253 ******************************************************************************/ 254 #define TEGRA_TZRAM_BASE U(0x30000000) 255 #define TEGRA_TZRAM_SIZE U(0x40000) 256 257 #endif /* TEGRA_DEF_H */ 258