1Trusted Firmware-A design 2========================= 3 4 5 6 7.. contents:: 8 9Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 10Requirements (TBBR) Platform Design Document (PDD) [1]_ for Arm reference 11platforms. The TBB sequence starts when the platform is powered on and runs up 12to the stage where it hands-off control to firmware running in the normal 13world in DRAM. This is the cold boot path. 14 15TF-A also implements the Power State Coordination Interface PDD [2]_ as a 16runtime service. PSCI is the interface from normal world software to firmware 17implementing power management use-cases (for example, secondary CPU boot, 18hotplug and idle). Normal world software can access TF-A runtime services via 19the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be 20used as mandated by the SMC Calling Convention [3]_. 21 22TF-A implements a framework for configuring and managing interrupts generated 23in either security state. The details of the interrupt management framework 24and its design can be found in TF-A Interrupt Management Design guide [4]_. 25 26TF-A also implements a library for setting up and managing the translation 27tables. The details of this library can be found in `Xlat_tables design`_. 28 29TF-A can be built to support either AArch64 or AArch32 execution state. 30 31Cold boot 32--------- 33 34The cold boot path starts when the platform is physically turned on. If 35``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 36primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 37CPU is chosen through platform-specific means. The cold boot path is mainly 38executed by the primary CPU, other than essential CPU initialization executed by 39all CPUs. The secondary CPUs are kept in a safe platform-specific state until 40the primary CPU has performed enough initialization to boot them. 41 42Refer to the `Reset Design`_ for more information on the effect of the 43``COLD_BOOT_SINGLE_CPU`` platform build option. 44 45The cold boot path in this implementation of TF-A depends on the execution 46state. For AArch64, it is divided into five steps (in order of execution): 47 48- Boot Loader stage 1 (BL1) *AP Trusted ROM* 49- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 50- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 51- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 52- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 53 54For AArch32, it is divided into four steps (in order of execution): 55 56- Boot Loader stage 1 (BL1) *AP Trusted ROM* 57- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 58- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 59- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 60 61Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 62combination of the following types of memory regions. Each bootloader stage uses 63one or more of these memory regions. 64 65- Regions accessible from both non-secure and secure states. For example, 66 non-trusted SRAM, ROM and DRAM. 67- Regions accessible from only the secure state. For example, trusted SRAM and 68 ROM. The FVPs also implement the trusted DRAM which is statically 69 configured. Additionally, the Base FVPs and Juno development platform 70 configure the TrustZone Controller (TZC) to create a region in the DRAM 71 which is accessible only from the secure state. 72 73The sections below provide the following details: 74 75- dynamic configuration of Boot Loader stages 76- initialization and execution of the first three stages during cold boot 77- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 78 AArch32) entrypoint requirements for use by alternative Trusted Boot 79 Firmware in place of the provided BL1 and BL2 80 81Dynamic Configuration during cold boot 82~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 83 84Each of the Boot Loader stages may be dynamically configured if required by the 85platform. The Boot Loader stage may optionally specify a firmware 86configuration file and/or hardware configuration file as listed below: 87 88- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 89 stages and also by the Normal World Rich OS. 90- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 91 and BL2. 92- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 93- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 94 (BL32). 95- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 96 firmware (BL33). 97 98The Arm development platforms use the Flattened Device Tree format for the 99dynamic configuration files. 100 101Each Boot Loader stage can pass up to 4 arguments via registers to the next 102stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 103Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 104arguments are platform defined. The Arm development platforms use the following 105convention: 106 107- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 108 structure contains the memory layout available to BL2. 109- When dynamic configuration files are present, the firmware configuration for 110 the next Boot Loader stage is populated in the first available argument and 111 the generic hardware configuration is passed the next available argument. 112 For example, 113 114 - If TB_FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` 115 to BL2. 116 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 117 BL2. Note, ``arg1`` is already used for meminfo_t. 118 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 119 to BL31. Note, ``arg0`` is used to pass the list of executable images. 120 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 121 passed in ``arg2`` to BL31. 122 - For other BL3x images, if the firmware configuration file is loaded by 123 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 124 then its address is passed in ``arg1``. 125 126BL1 127~~~ 128 129This stage begins execution from the platform's reset vector at EL3. The reset 130address is platform dependent but it is usually located in a Trusted ROM area. 131The BL1 data section is copied to trusted SRAM at runtime. 132 133On the Arm development platforms, BL1 code starts execution from the reset 134vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 135to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 136 137The functionality implemented by this stage is as follows. 138 139Determination of boot path 140^^^^^^^^^^^^^^^^^^^^^^^^^^ 141 142Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 143boot and a cold boot. This is done using platform-specific mechanisms (see the 144``plat_get_my_entrypoint()`` function in the `Porting Guide`_). In the case of a 145warm boot, a CPU is expected to continue execution from a separate 146entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 147platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 148the `Porting Guide`_) while the primary CPU executes the remaining cold boot path 149as described in the following sections. 150 151This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 152`Reset Design`_ for more information on the effect of the 153``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 154 155Architectural initialization 156^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 157 158BL1 performs minimal architectural initialization as follows. 159 160- Exception vectors 161 162 BL1 sets up simple exception vectors for both synchronous and asynchronous 163 exceptions. The default behavior upon receiving an exception is to populate 164 a status code in the general purpose register ``X0/R0`` and call the 165 ``plat_report_exception()`` function (see the `Porting Guide`_). The status 166 code is one of: 167 168 For AArch64: 169 170 :: 171 172 0x0 : Synchronous exception from Current EL with SP_EL0 173 0x1 : IRQ exception from Current EL with SP_EL0 174 0x2 : FIQ exception from Current EL with SP_EL0 175 0x3 : System Error exception from Current EL with SP_EL0 176 0x4 : Synchronous exception from Current EL with SP_ELx 177 0x5 : IRQ exception from Current EL with SP_ELx 178 0x6 : FIQ exception from Current EL with SP_ELx 179 0x7 : System Error exception from Current EL with SP_ELx 180 0x8 : Synchronous exception from Lower EL using aarch64 181 0x9 : IRQ exception from Lower EL using aarch64 182 0xa : FIQ exception from Lower EL using aarch64 183 0xb : System Error exception from Lower EL using aarch64 184 0xc : Synchronous exception from Lower EL using aarch32 185 0xd : IRQ exception from Lower EL using aarch32 186 0xe : FIQ exception from Lower EL using aarch32 187 0xf : System Error exception from Lower EL using aarch32 188 189 For AArch32: 190 191 :: 192 193 0x10 : User mode 194 0x11 : FIQ mode 195 0x12 : IRQ mode 196 0x13 : SVC mode 197 0x16 : Monitor mode 198 0x17 : Abort mode 199 0x1a : Hypervisor mode 200 0x1b : Undefined mode 201 0x1f : System mode 202 203 The ``plat_report_exception()`` implementation on the Arm FVP port programs 204 the Versatile Express System LED register in the following format to 205 indicate the occurrence of an unexpected exception: 206 207 :: 208 209 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 210 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 211 For AArch32 it is always 0x0 212 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 213 of the status code 214 215 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 216 CLCD window of the FVP. 217 218 BL1 does not expect to receive any exceptions other than the SMC exception. 219 For the latter, BL1 installs a simple stub. The stub expects to receive a 220 limited set of SMC types (determined by their function IDs in the general 221 purpose register ``X0/R0``): 222 223 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 224 to EL3 Runtime Software. 225 - All SMCs listed in section "BL1 SMC Interface" in the `Firmware Update`_ 226 Design Guide are supported for AArch64 only. These SMCs are currently 227 not supported when BL1 is built for AArch32. 228 229 Any other SMC leads to an assertion failure. 230 231- CPU initialization 232 233 BL1 calls the ``reset_handler()`` function which in turn calls the CPU 234 specific reset handler function (see the section: "CPU specific operations 235 framework"). 236 237- Control register setup (for AArch64) 238 239 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I`` 240 bit. Alignment and stack alignment checking is enabled by setting the 241 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to 242 little-endian by clearing the ``SCTLR_EL3.EE`` bit. 243 244 - ``SCR_EL3``. The register width of the next lower exception level is set 245 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap 246 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is 247 also set to disable instruction fetches from Non-secure memory when in 248 secure state. 249 250 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the 251 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by 252 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is 253 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit. 254 Instructions that access the registers associated with Floating Point 255 and Advanced SIMD execution are configured to not trap to EL3 by 256 clearing the ``CPTR_EL3.TFP`` bit. 257 258 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt 259 mask bit. 260 261 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and 262 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control 263 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by 264 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to 265 disable AArch32 Secure self-hosted privileged debug from S-EL1. 266 267- Control register setup (for AArch32) 268 269 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit. 270 Alignment checking is enabled by setting the ``SCTLR.A`` bit. 271 Exception endianness is set to little-endian by clearing the 272 ``SCTLR.EE`` bit. 273 274 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from 275 Non-secure memory when in secure state. 276 277 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1, 278 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality 279 is configured not to trap to undefined mode by clearing the 280 ``CPACR.TRCDIS`` bit. 281 282 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and 283 system register access to implemented trace registers. 284 285 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point 286 functionality from all Exception levels. 287 288 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing 289 the Asynchronous data abort interrupt mask bit. 290 291 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure 292 self-hosted privileged debug. 293 294Platform initialization 295^^^^^^^^^^^^^^^^^^^^^^^ 296 297On Arm platforms, BL1 performs the following platform initializations: 298 299- Enable the Trusted Watchdog. 300- Initialize the console. 301- Configure the Interconnect to enable hardware coherency. 302- Enable the MMU and map the memory it needs to access. 303- Configure any required platform storage to load the next bootloader image 304 (BL2). 305- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 306 load it to the platform defined address and make it available to BL2 via 307 ``arg0``. 308- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 309 and NS-BL2U firmware update images. 310 311Firmware Update detection and execution 312^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 313 314After performing platform setup, BL1 common code calls 315``bl1_plat_get_next_image_id()`` to determine if `Firmware Update`_ is required or 316to proceed with the normal boot process. If the platform code returns 317``BL2_IMAGE_ID`` then the normal boot sequence is executed as described in the 318next section, else BL1 assumes that `Firmware Update`_ is required and execution 319passes to the first image in the `Firmware Update`_ process. In either case, BL1 320retrieves a descriptor of the next image by calling ``bl1_plat_get_image_desc()``. 321The image descriptor contains an ``entry_point_info_t`` structure, which BL1 322uses to initialize the execution state of the next image. 323 324BL2 image load and execution 325^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 326 327In the normal boot flow, BL1 execution continues as follows: 328 329#. BL1 prints the following string from the primary CPU to indicate successful 330 execution of the BL1 stage: 331 332 :: 333 334 "Booting Trusted Firmware" 335 336#. BL1 loads a BL2 raw binary image from platform storage, at a 337 platform-specific base address. Prior to the load, BL1 invokes 338 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 339 use the image information. If the BL2 image file is not present or if 340 there is not enough free trusted SRAM the following error message is 341 printed: 342 343 :: 344 345 "Failed to load BL2 firmware." 346 347#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 348 for platforms to take further action after image load. This function must 349 populate the necessary arguments for BL2, which may also include the memory 350 layout. Further description of the memory layout can be found later 351 in this document. 352 353#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 354 Secure SVC mode (for AArch32), starting from its load address. 355 356BL2 357~~~ 358 359BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 360SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 361base address (more information can be found later in this document). 362The functionality implemented by BL2 is as follows. 363 364Architectural initialization 365^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 366 367For AArch64, BL2 performs the minimal architectural initialization required 368for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 369access to Floating Point and Advanced SIMD registers by clearing the 370``CPACR.FPEN`` bits. 371 372For AArch32, the minimal architectural initialization required for subsequent 373stages of TF-A and normal world software is taken care of in BL1 as both BL1 374and BL2 execute at PL1. 375 376Platform initialization 377^^^^^^^^^^^^^^^^^^^^^^^ 378 379On Arm platforms, BL2 performs the following platform initializations: 380 381- Initialize the console. 382- Configure any required platform storage to allow loading further bootloader 383 images. 384- Enable the MMU and map the memory it needs to access. 385- Perform platform security setup to allow access to controlled components. 386- Reserve some memory for passing information to the next bootloader image 387 EL3 Runtime Software and populate it. 388- Define the extents of memory available for loading each subsequent 389 bootloader image. 390- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 391 then parse it. 392 393Image loading in BL2 394^^^^^^^^^^^^^^^^^^^^ 395 396BL2 generic code loads the images based on the list of loadable images 397provided by the platform. BL2 passes the list of executable images 398provided by the platform to the next handover BL image. 399 400The list of loadable images provided by the platform may also contain 401dynamic configuration files. The files are loaded and can be parsed as 402needed in the ``bl2_plat_handle_post_image_load()`` function. These 403configuration files can be passed to next Boot Loader stages as arguments 404by updating the corresponding entrypoint information in this function. 405 406SCP_BL2 (System Control Processor Firmware) image load 407^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 408 409Some systems have a separate System Control Processor (SCP) for power, clock, 410reset and system control. BL2 loads the optional SCP_BL2 image from platform 411storage into a platform-specific region of secure memory. The subsequent 412handling of SCP_BL2 is platform specific. For example, on the Juno Arm 413development platform port the image is transferred into SCP's internal memory 414using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 415memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 416for BL2 execution to continue. 417 418EL3 Runtime Software image load 419^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 420 421BL2 loads the EL3 Runtime Software image from platform storage into a platform- 422specific address in trusted SRAM. If there is not enough memory to load the 423image or image is missing it leads to an assertion failure. 424 425AArch64 BL32 (Secure-EL1 Payload) image load 426^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 427 428BL2 loads the optional BL32 image from platform storage into a platform- 429specific region of secure memory. The image executes in the secure world. BL2 430relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 431populates a platform-specific area of memory with the entrypoint/load-address 432of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 433for entry into BL32 is not determined by BL2, it is initialized by the 434Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 435managing interaction with BL32. This information is passed to BL31. 436 437BL33 (Non-trusted Firmware) image load 438^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 439 440BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 441platform storage into non-secure memory as defined by the platform. 442 443BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 444initialization is complete. Hence, BL2 populates a platform-specific area of 445memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 446normal world software image. The entrypoint is the load address of the BL33 447image. The ``SPSR`` is determined as specified in Section 5.13 of the 448`PSCI PDD`_. This information is passed to the EL3 Runtime Software. 449 450AArch64 BL31 (EL3 Runtime Software) execution 451^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 452 453BL2 execution continues as follows: 454 455#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 456 BL31 entrypoint. The exception is handled by the SMC exception handler 457 installed by BL1. 458 459#. BL1 turns off the MMU and flushes the caches. It clears the 460 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 461 and invalidates the TLBs. 462 463#. BL1 passes control to BL31 at the specified entrypoint at EL3. 464 465Running BL2 at EL3 execution level 466~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 467 468Some platforms have a non-TF-A Boot ROM that expects the next boot stage 469to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 470as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 471this waste, a special mode enables BL2 to execute at EL3, which allows 472a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 473when the build flag BL2_AT_EL3 is enabled. The main differences in this 474mode are: 475 476#. BL2 includes the reset code and the mailbox mechanism to differentiate 477 cold boot and warm boot. It runs at EL3 doing the arch 478 initialization required for EL3. 479 480#. BL2 does not receive the meminfo information from BL1 anymore. This 481 information can be passed by the Boot ROM or be internal to the 482 BL2 image. 483 484#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 485 instead of invoking the RUN_IMAGE SMC call. 486 487 488We assume 3 different types of BootROM support on the platform: 489 490#. The Boot ROM always jumps to the same address, for both cold 491 and warm boot. In this case, we will need to keep a resident part 492 of BL2 whose memory cannot be reclaimed by any other image. The 493 linker script defines the symbols __TEXT_RESIDENT_START__ and 494 __TEXT_RESIDENT_END__ that allows the platform to configure 495 correctly the memory map. 496#. The platform has some mechanism to indicate the jump address to the 497 Boot ROM. Platform code can then program the jump address with 498 psci_warmboot_entrypoint during cold boot. 499#. The platform has some mechanism to program the reset address using 500 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 501 program the reset address with psci_warmboot_entrypoint during 502 cold boot, bypassing the boot ROM for warm boot. 503 504In the last 2 cases, no part of BL2 needs to remain resident at 505runtime. In the first 2 cases, we expect the Boot ROM to be able to 506differentiate between warm and cold boot, to avoid loading BL2 again 507during warm boot. 508 509This functionality can be tested with FVP loading the image directly 510in memory and changing the address where the system jumps at reset. 511For example: 512 513 -C cluster0.cpu0.RVBAR=0x4022000 514 --data cluster0.cpu0=bl2.bin@0x4022000 515 516With this configuration, FVP is like a platform of the first case, 517where the Boot ROM jumps always to the same address. For simplification, 518BL32 is loaded in DRAM in this case, to avoid other images reclaiming 519BL2 memory. 520 521 522AArch64 BL31 523~~~~~~~~~~~~ 524 525The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 526EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 527loaded at a platform-specific base address (more information can be found later 528in this document). The functionality implemented by BL31 is as follows. 529 530Architectural initialization 531^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 532 533Currently, BL31 performs a similar architectural initialization to BL1 as 534far as system register settings are concerned. Since BL1 code resides in ROM, 535architectural initialization in BL31 allows override of any previous 536initialization done by BL1. 537 538BL31 initializes the per-CPU data framework, which provides a cache of 539frequently accessed per-CPU data optimised for fast, concurrent manipulation 540on different CPUs. This buffer includes pointers to per-CPU contexts, crash 541buffer, CPU reset and power down operations, PSCI data, platform data and so on. 542 543It then replaces the exception vectors populated by BL1 with its own. BL31 544exception vectors implement more elaborate support for handling SMCs since this 545is the only mechanism to access the runtime services implemented by BL31 (PSCI 546for example). BL31 checks each SMC for validity as specified by the 547`SMC calling convention PDD`_ before passing control to the required SMC 548handler routine. 549 550BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 551counter, which is provided by the platform. 552 553Platform initialization 554^^^^^^^^^^^^^^^^^^^^^^^ 555 556BL31 performs detailed platform initialization, which enables normal world 557software to function correctly. 558 559On Arm platforms, this consists of the following: 560 561- Initialize the console. 562- Configure the Interconnect to enable hardware coherency. 563- Enable the MMU and map the memory it needs to access. 564- Initialize the generic interrupt controller. 565- Initialize the power controller device. 566- Detect the system topology. 567 568Runtime services initialization 569^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 570 571BL31 is responsible for initializing the runtime services. One of them is PSCI. 572 573As part of the PSCI initializations, BL31 detects the system topology. It also 574initializes the data structures that implement the state machine used to track 575the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 576``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 577that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 578initializes the locks that protect them. BL31 accesses the state of a CPU or 579cluster immediately after reset and before the data cache is enabled in the 580warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 581therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 582 583The runtime service framework and its initialization is described in more 584detail in the "EL3 runtime services framework" section below. 585 586Details about the status of the PSCI implementation are provided in the 587"Power State Coordination Interface" section below. 588 589AArch64 BL32 (Secure-EL1 Payload) image initialization 590^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 591 592If a BL32 image is present then there must be a matching Secure-EL1 Payload 593Dispatcher (SPD) service (see later for details). During initialization 594that service must register a function to carry out initialization of BL32 595once the runtime services are fully initialized. BL31 invokes such a 596registered function to initialize BL32 before running BL33. This initialization 597is not necessary for AArch32 SPs. 598 599Details on BL32 initialization and the SPD's role are described in the 600"Secure-EL1 Payloads and Dispatchers" section below. 601 602BL33 (Non-trusted Firmware) execution 603^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 604 605EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 606world cold boot, ensuring that no secure state information finds its way into 607the non-secure execution state. EL3 Runtime Software uses the entrypoint 608information provided by BL2 to jump to the Non-trusted firmware image (BL33) 609at the highest available Exception Level (EL2 if available, otherwise EL1). 610 611Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 612~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 613 614Some platforms have existing implementations of Trusted Boot Firmware that 615would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 616firmware architecture it is important to provide a fully documented and stable 617interface between the Trusted Boot Firmware and BL31. 618 619Future changes to the BL31 interface will be done in a backwards compatible 620way, and this enables these firmware components to be independently enhanced/ 621updated to develop and exploit new functionality. 622 623Required CPU state when calling ``bl31_entrypoint()`` during cold boot 624^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 625 626This function must only be called by the primary CPU. 627 628On entry to this function the calling primary CPU must be executing in AArch64 629EL3, little-endian data access, and all interrupt sources masked: 630 631:: 632 633 PSTATE.EL = 3 634 PSTATE.RW = 1 635 PSTATE.DAIF = 0xf 636 SCTLR_EL3.EE = 0 637 638X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 639platform code in BL31: 640 641:: 642 643 X0 : Reserved for common TF-A information 644 X1 : Platform specific information 645 646BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 647these will be zero filled prior to invoking platform setup code. 648 649Use of the X0 and X1 parameters 650''''''''''''''''''''''''''''''' 651 652The parameters are platform specific and passed from ``bl31_entrypoint()`` to 653``bl31_early_platform_setup()``. The value of these parameters is never directly 654used by the common BL31 code. 655 656The convention is that ``X0`` conveys information regarding the BL31, BL32 and 657BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 658platform specific purpose. This convention allows platforms which use TF-A's 659BL1 and BL2 images to transfer additional platform specific information from 660Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 661pass a ``bl31_params`` structure. 662 663BL31 common and SPD initialization code depends on image and entrypoint 664information about BL33 and BL32, which is provided via BL31 platform APIs. 665This information is required until the start of execution of BL33. This 666information can be provided in a platform defined manner, e.g. compiled into 667the platform code in BL31, or provided in a platform defined memory location 668by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 669Cold boot Initialization parameters. This data may need to be cleaned out of 670the CPU caches if it is provided by an earlier boot stage and then accessed by 671BL31 platform code before the caches are enabled. 672 673TF-A's BL2 implementation passes a ``bl31_params`` structure in 674``X0`` and the Arm development platforms interpret this in the BL31 platform 675code. 676 677MMU, Data caches & Coherency 678'''''''''''''''''''''''''''' 679 680BL31 does not depend on the enabled state of the MMU, data caches or 681interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 682on entry, these should be enabled during ``bl31_plat_arch_setup()``. 683 684Data structures used in the BL31 cold boot interface 685'''''''''''''''''''''''''''''''''''''''''''''''''''' 686 687These structures are designed to support compatibility and independent 688evolution of the structures and the firmware images. For example, a version of 689BL31 that can interpret the BL3x image information from different versions of 690BL2, a platform that uses an extended entry_point_info structure to convey 691additional register information to BL31, or a ELF image loader that can convey 692more details about the firmware images. 693 694To support these scenarios the structures are versioned and sized, which enables 695BL31 to detect which information is present and respond appropriately. The 696``param_header`` is defined to capture this information: 697 698.. code:: c 699 700 typedef struct param_header { 701 uint8_t type; /* type of the structure */ 702 uint8_t version; /* version of this structure */ 703 uint16_t size; /* size of this structure in bytes */ 704 uint32_t attr; /* attributes: unused bits SBZ */ 705 } param_header_t; 706 707The structures using this format are ``entry_point_info``, ``image_info`` and 708``bl31_params``. The code that allocates and populates these structures must set 709the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined 710to simplify this action. 711 712Required CPU state for BL31 Warm boot initialization 713^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 714 715When requesting a CPU power-on, or suspending a running CPU, TF-A provides 716the platform power management code with a Warm boot initialization 717entry-point, to be invoked by the CPU immediately after the reset handler. 718On entry to the Warm boot initialization function the calling CPU must be in 719AArch64 EL3, little-endian data access and all interrupt sources masked: 720 721:: 722 723 PSTATE.EL = 3 724 PSTATE.RW = 1 725 PSTATE.DAIF = 0xf 726 SCTLR_EL3.EE = 0 727 728The PSCI implementation will initialize the processor state and ensure that the 729platform power management code is then invoked as required to initialize all 730necessary system, cluster and CPU resources. 731 732AArch32 EL3 Runtime Software entrypoint interface 733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 734 735To enable this firmware architecture it is important to provide a fully 736documented and stable interface between the Trusted Boot Firmware and the 737AArch32 EL3 Runtime Software. 738 739Future changes to the entrypoint interface will be done in a backwards 740compatible way, and this enables these firmware components to be independently 741enhanced/updated to develop and exploit new functionality. 742 743Required CPU state when entering during cold boot 744^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 745 746This function must only be called by the primary CPU. 747 748On entry to this function the calling primary CPU must be executing in AArch32 749EL3, little-endian data access, and all interrupt sources masked: 750 751:: 752 753 PSTATE.AIF = 0x7 754 SCTLR.EE = 0 755 756R0 and R1 are used to pass information from the Trusted Boot Firmware to the 757platform code in AArch32 EL3 Runtime Software: 758 759:: 760 761 R0 : Reserved for common TF-A information 762 R1 : Platform specific information 763 764Use of the R0 and R1 parameters 765''''''''''''''''''''''''''''''' 766 767The parameters are platform specific and the convention is that ``R0`` conveys 768information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 769can be used for other platform specific purpose. This convention allows 770platforms which use TF-A's BL1 and BL2 images to transfer additional platform 771specific information from Secure Boot without conflicting with future 772evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 773 774The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 775information can be obtained in a platform defined manner, e.g. compiled into 776the AArch32 EL3 Runtime Software, or provided in a platform defined memory 777location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 778via the Cold boot Initialization parameters. This data may need to be cleaned 779out of the CPU caches if it is provided by an earlier boot stage and then 780accessed by AArch32 EL3 Runtime Software before the caches are enabled. 781 782When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 783``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 784Software platform code. 785 786MMU, Data caches & Coherency 787'''''''''''''''''''''''''''' 788 789AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 790data caches or interconnect coherency in its entrypoint. They must be explicitly 791enabled if required. 792 793Data structures used in cold boot interface 794''''''''''''''''''''''''''''''''''''''''''' 795 796The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 797of ``bl31_params``. The ``bl_params`` structure is based on the convention 798described in AArch64 BL31 cold boot interface section. 799 800Required CPU state for warm boot initialization 801^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 802 803When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 804Runtime Software must ensure execution of a warm boot initialization entrypoint. 805If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 806then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 807boot entrypoint by arranging for the BL1 platform function, 808plat_get_my_entrypoint(), to return a non-zero value. 809 810In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 811data access and all interrupt sources masked: 812 813:: 814 815 PSTATE.AIF = 0x7 816 SCTLR.EE = 0 817 818The warm boot entrypoint may be implemented by using TF-A 819``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 820the pre-requisites mentioned in the `PSCI Library integration guide`_. 821 822EL3 runtime services framework 823------------------------------ 824 825Software executing in the non-secure state and in the secure state at exception 826levels lower than EL3 will request runtime services using the Secure Monitor 827Call (SMC) instruction. These requests will follow the convention described in 828the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 829identifiers to each SMC request and describes how arguments are passed and 830returned. 831 832The EL3 runtime services framework enables the development of services by 833different providers that can be easily integrated into final product firmware. 834The following sections describe the framework which facilitates the 835registration, initialization and use of runtime services in EL3 Runtime 836Software (BL31). 837 838The design of the runtime services depends heavily on the concepts and 839definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 840Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 841conventions. Please refer to that document for more detailed explanation of 842these terms. 843 844The following runtime services are expected to be implemented first. They have 845not all been instantiated in the current implementation. 846 847#. Standard service calls 848 849 This service is for management of the entire system. The Power State 850 Coordination Interface (`PSCI`_) is the first set of standard service calls 851 defined by Arm (see PSCI section later). 852 853#. Secure-EL1 Payload Dispatcher service 854 855 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 856 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 857 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 858 The Secure Monitor will make these world switches in response to SMCs. The 859 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 860 Application Call OEN ranges. 861 862 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 863 not defined by the `SMCCC`_ or any other standard. As a result, each 864 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 865 service - within TF-A this service is referred to as the Secure-EL1 Payload 866 Dispatcher (SPD). 867 868 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 869 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 870 "Secure-EL1 Payloads and Dispatchers" section below. 871 872#. CPU implementation service 873 874 This service will provide an interface to CPU implementation specific 875 services for a given platform e.g. access to processor errata workarounds. 876 This service is currently unimplemented. 877 878Additional services for Arm Architecture, SiP and OEM calls can be implemented. 879Each implemented service handles a range of SMC function identifiers as 880described in the `SMCCC`_. 881 882Registration 883~~~~~~~~~~~~ 884 885A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 886the name of the service, the range of OENs covered, the type of service and 887initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 888This structure is allocated in a special ELF section ``rt_svc_descs``, enabling 889the framework to find all service descriptors included into BL31. 890 891The specific service for a SMC Function is selected based on the OEN and call 892type of the Function ID, and the framework uses that information in the service 893descriptor to identify the handler for the SMC Call. 894 895The service descriptors do not include information to identify the precise set 896of SMC function identifiers supported by this service implementation, the 897security state from which such calls are valid nor the capability to support 89864-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 899to these aspects of a SMC call is the responsibility of the service 900implementation, the framework is focused on integration of services from 901different providers and minimizing the time taken by the framework before the 902service handler is invoked. 903 904Details of the parameters, requirements and behavior of the initialization and 905call handling functions are provided in the following sections. 906 907Initialization 908~~~~~~~~~~~~~~ 909 910``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 911framework running on the primary CPU during cold boot as part of the BL31 912initialization. This happens prior to initializing a Trusted OS and running 913Normal world boot firmware that might in turn use these services. 914Initialization involves validating each of the declared runtime service 915descriptors, calling the service initialization function and populating the 916index used for runtime lookup of the service. 917 918The BL31 linker script collects all of the declared service descriptors into a 919single array and defines symbols that allow the framework to locate and traverse 920the array, and determine its size. 921 922The framework does basic validation of each descriptor to halt firmware 923initialization if service declaration errors are detected. The framework does 924not check descriptors for the following error conditions, and may behave in an 925unpredictable manner under such scenarios: 926 927#. Overlapping OEN ranges 928#. Multiple descriptors for the same range of OENs and ``call_type`` 929#. Incorrect range of owning entity numbers for a given ``call_type`` 930 931Once validated, the service ``init()`` callback is invoked. This function carries 932out any essential EL3 initialization before servicing requests. The ``init()`` 933function is only invoked on the primary CPU during cold boot. If the service 934uses per-CPU data this must either be initialized for all CPUs during this call, 935or be done lazily when a CPU first issues an SMC call to that service. If 936``init()`` returns anything other than ``0``, this is treated as an initialization 937error and the service is ignored: this does not cause the firmware to halt. 938 939The OEN and call type fields present in the SMC Function ID cover a total of 940128 distinct services, but in practice a single descriptor can cover a range of 941OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 942service handler, the framework uses an array of 128 indices that map every 943distinct OEN/call-type combination either to one of the declared services or to 944indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 945populated for all of the OENs covered by a service after the service ``init()`` 946function has reported success. So a service that fails to initialize will never 947have it's ``handle()`` function invoked. 948 949The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 950Function ID call type and OEN onto a specific service handler in the 951``rt_svc_descs[]`` array. 952 953|Image 1| 954 955Handling an SMC 956~~~~~~~~~~~~~~~ 957 958When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 959Function ID is passed in W0 from the lower exception level (as per the 960`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 961SMC Function which indicates the SMC64 calling convention: such calls are 962ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 963in R0/X0. 964 965Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 966Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 967resulting value might indicate a service that has no handler, in this case the 968framework will also report an Unknown SMC Function ID. Otherwise, the value is 969used as a further index into the ``rt_svc_descs[]`` array to locate the required 970service and handler. 971 972The service's ``handle()`` callback is provided with five of the SMC parameters 973directly, the others are saved into memory for retrieval (if needed) by the 974handler. The handler is also provided with an opaque ``handle`` for use with the 975supporting library for parameter retrieval, setting return values and context 976manipulation; and with ``flags`` indicating the security state of the caller. The 977framework finally sets up the execution stack for the handler, and invokes the 978services ``handle()`` function. 979 980On return from the handler the result registers are populated in X0-X3 before 981restoring the stack and CPU state and returning from the original SMC. 982 983Exception Handling Framework 984---------------------------- 985 986Please refer to the `Exception Handling Framework`_ document. 987 988Power State Coordination Interface 989---------------------------------- 990 991TODO: Provide design walkthrough of PSCI implementation. 992 993The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 994mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 995`Power State Coordination Interface PDD`_ are implemented. The table lists 996the PSCI v1.1 APIs and their support in generic code. 997 998An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 999requires the platform to export a part of the implementation. Hence the level 1000of support of the mandatory APIs depends upon the support exported by the 1001platform port as well. The Juno and FVP (all variants) platforms export all the 1002required support. 1003 1004+-----------------------------+-------------+-------------------------------+ 1005| PSCI v1.1 API | Supported | Comments | 1006+=============================+=============+===============================+ 1007| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 1008+-----------------------------+-------------+-------------------------------+ 1009| ``CPU_SUSPEND`` | Yes\* | | 1010+-----------------------------+-------------+-------------------------------+ 1011| ``CPU_OFF`` | Yes\* | | 1012+-----------------------------+-------------+-------------------------------+ 1013| ``CPU_ON`` | Yes\* | | 1014+-----------------------------+-------------+-------------------------------+ 1015| ``AFFINITY_INFO`` | Yes | | 1016+-----------------------------+-------------+-------------------------------+ 1017| ``MIGRATE`` | Yes\*\* | | 1018+-----------------------------+-------------+-------------------------------+ 1019| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 1020+-----------------------------+-------------+-------------------------------+ 1021| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 1022+-----------------------------+-------------+-------------------------------+ 1023| ``SYSTEM_OFF`` | Yes\* | | 1024+-----------------------------+-------------+-------------------------------+ 1025| ``SYSTEM_RESET`` | Yes\* | | 1026+-----------------------------+-------------+-------------------------------+ 1027| ``PSCI_FEATURES`` | Yes | | 1028+-----------------------------+-------------+-------------------------------+ 1029| ``CPU_FREEZE`` | No | | 1030+-----------------------------+-------------+-------------------------------+ 1031| ``CPU_DEFAULT_SUSPEND`` | No | | 1032+-----------------------------+-------------+-------------------------------+ 1033| ``NODE_HW_STATE`` | Yes\* | | 1034+-----------------------------+-------------+-------------------------------+ 1035| ``SYSTEM_SUSPEND`` | Yes\* | | 1036+-----------------------------+-------------+-------------------------------+ 1037| ``PSCI_SET_SUSPEND_MODE`` | No | | 1038+-----------------------------+-------------+-------------------------------+ 1039| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1040+-----------------------------+-------------+-------------------------------+ 1041| ``PSCI_STAT_COUNT`` | Yes\* | | 1042+-----------------------------+-------------+-------------------------------+ 1043| ``SYSTEM_RESET2`` | Yes\* | | 1044+-----------------------------+-------------+-------------------------------+ 1045| ``MEM_PROTECT`` | Yes\* | | 1046+-----------------------------+-------------+-------------------------------+ 1047| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1048+-----------------------------+-------------+-------------------------------+ 1049 1050\*Note : These PSCI APIs require platform power management hooks to be 1051registered with the generic PSCI code to be supported. 1052 1053\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1054hooks to be registered with the generic PSCI code to be supported. 1055 1056The PSCI implementation in TF-A is a library which can be integrated with 1057AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1058integrating PSCI library with AArch32 EL3 Runtime Software can be found 1059`here`_. 1060 1061Secure-EL1 Payloads and Dispatchers 1062----------------------------------- 1063 1064On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1065the Trusted OS is coupled with a companion runtime service in the BL31 1066firmware. This service is responsible for the initialisation of the Trusted 1067OS and all communications with it. The Trusted OS is the BL32 stage of the 1068boot flow in TF-A. The firmware will attempt to locate, load and execute a 1069BL32 image. 1070 1071TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1072the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1073 1074TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1075Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1076production system using the Runtime Services Framework. On such a system, the 1077Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1078service. The TF-A build system expects that the dispatcher will define the 1079build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1080as a binary or to compile from source depending on whether the ``BL32`` build 1081option is specified or not. 1082 1083The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1084communication with the normal-world software running in EL1/EL2. Communication 1085is initiated by the normal-world software 1086 1087- either directly through a Fast SMC (as defined in the `SMCCC`_) 1088 1089- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1090 informs the TSPD about the requested power management operation. This allows 1091 the TSP to prepare for or respond to the power state change 1092 1093The TSPD service is responsible for. 1094 1095- Initializing the TSP 1096 1097- Routing requests and responses between the secure and the non-secure 1098 states during the two types of communications just described 1099 1100Initializing a BL32 Image 1101~~~~~~~~~~~~~~~~~~~~~~~~~ 1102 1103The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1104the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1105so. This is provided by: 1106 1107.. code:: c 1108 1109 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1110 1111which returns a reference to the ``entry_point_info`` structure corresponding to 1112the image which will be run in the specified security state. The SPD uses this 1113API to get entry point information for the SECURE image, BL32. 1114 1115In the absence of a BL32 image, BL31 passes control to the normal world 1116bootloader image (BL33). When the BL32 image is present, it is typical 1117that the SPD wants control to be passed to BL32 first and then later to BL33. 1118 1119To do this the SPD has to register a BL32 initialization function during 1120initialization of the SPD service. The BL32 initialization function has this 1121prototype: 1122 1123.. code:: c 1124 1125 int32_t init(void); 1126 1127and is registered using the ``bl31_register_bl32_init()`` function. 1128 1129TF-A supports two approaches for the SPD to pass control to BL32 before 1130returning through EL3 and running the non-trusted firmware (BL33): 1131 1132#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1133 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1134 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1135 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1136 1137 When the BL32 has completed initialization at Secure-EL1, it returns to 1138 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1139 receipt of this SMC, the SPD service handler should switch the CPU context 1140 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1141 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1142 the normal world firmware BL33. On return from the handler the framework 1143 will exit to EL2 and run BL33. 1144 1145#. The BL32 setup function registers an initialization function using 1146 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1147 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1148 entrypoint. 1149 NOTE: The Test SPD service included with TF-A provides one implementation 1150 of such a mechanism. 1151 1152 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1153 SPD service handler invokes the synchronous call return mechanism to return 1154 to the BL32 initialization function. On return from this function, 1155 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1156 continue the boot process in the normal world. 1157 1158Crash Reporting in BL31 1159----------------------- 1160 1161BL31 implements a scheme for reporting the processor state when an unhandled 1162exception is encountered. The reporting mechanism attempts to preserve all the 1163register contents and report it via a dedicated UART (PL011 console). BL31 1164reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1165 1166A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1167the per-CPU pointer cache. The implementation attempts to minimise the memory 1168required for this feature. The file ``crash_reporting.S`` contains the 1169implementation for crash reporting. 1170 1171The sample crash output is shown below. 1172 1173:: 1174 1175 x0 :0x000000004F00007C 1176 x1 :0x0000000007FFFFFF 1177 x2 :0x0000000004014D50 1178 x3 :0x0000000000000000 1179 x4 :0x0000000088007998 1180 x5 :0x00000000001343AC 1181 x6 :0x0000000000000016 1182 x7 :0x00000000000B8A38 1183 x8 :0x00000000001343AC 1184 x9 :0x00000000000101A8 1185 x10 :0x0000000000000002 1186 x11 :0x000000000000011C 1187 x12 :0x00000000FEFDC644 1188 x13 :0x00000000FED93FFC 1189 x14 :0x0000000000247950 1190 x15 :0x00000000000007A2 1191 x16 :0x00000000000007A4 1192 x17 :0x0000000000247950 1193 x18 :0x0000000000000000 1194 x19 :0x00000000FFFFFFFF 1195 x20 :0x0000000004014D50 1196 x21 :0x000000000400A38C 1197 x22 :0x0000000000247950 1198 x23 :0x0000000000000010 1199 x24 :0x0000000000000024 1200 x25 :0x00000000FEFDC868 1201 x26 :0x00000000FEFDC86A 1202 x27 :0x00000000019EDEDC 1203 x28 :0x000000000A7CFDAA 1204 x29 :0x0000000004010780 1205 x30 :0x000000000400F004 1206 scr_el3 :0x0000000000000D3D 1207 sctlr_el3 :0x0000000000C8181F 1208 cptr_el3 :0x0000000000000000 1209 tcr_el3 :0x0000000080803520 1210 daif :0x00000000000003C0 1211 mair_el3 :0x00000000000004FF 1212 spsr_el3 :0x00000000800003CC 1213 elr_el3 :0x000000000400C0CC 1214 ttbr0_el3 :0x00000000040172A0 1215 esr_el3 :0x0000000096000210 1216 sp_el3 :0x0000000004014D50 1217 far_el3 :0x000000004F00007C 1218 spsr_el1 :0x0000000000000000 1219 elr_el1 :0x0000000000000000 1220 spsr_abt :0x0000000000000000 1221 spsr_und :0x0000000000000000 1222 spsr_irq :0x0000000000000000 1223 spsr_fiq :0x0000000000000000 1224 sctlr_el1 :0x0000000030C81807 1225 actlr_el1 :0x0000000000000000 1226 cpacr_el1 :0x0000000000300000 1227 csselr_el1 :0x0000000000000002 1228 sp_el1 :0x0000000004028800 1229 esr_el1 :0x0000000000000000 1230 ttbr0_el1 :0x000000000402C200 1231 ttbr1_el1 :0x0000000000000000 1232 mair_el1 :0x00000000000004FF 1233 amair_el1 :0x0000000000000000 1234 tcr_el1 :0x0000000000003520 1235 tpidr_el1 :0x0000000000000000 1236 tpidr_el0 :0x0000000000000000 1237 tpidrro_el0 :0x0000000000000000 1238 dacr32_el2 :0x0000000000000000 1239 ifsr32_el2 :0x0000000000000000 1240 par_el1 :0x0000000000000000 1241 far_el1 :0x0000000000000000 1242 afsr0_el1 :0x0000000000000000 1243 afsr1_el1 :0x0000000000000000 1244 contextidr_el1 :0x0000000000000000 1245 vbar_el1 :0x0000000004027000 1246 cntp_ctl_el0 :0x0000000000000000 1247 cntp_cval_el0 :0x0000000000000000 1248 cntv_ctl_el0 :0x0000000000000000 1249 cntv_cval_el0 :0x0000000000000000 1250 cntkctl_el1 :0x0000000000000000 1251 sp_el0 :0x0000000004010780 1252 1253Guidelines for Reset Handlers 1254----------------------------- 1255 1256TF-A implements a framework that allows CPU and platform ports to perform 1257actions very early after a CPU is released from reset in both the cold and warm 1258boot paths. This is done by calling the ``reset_handler()`` function in both 1259the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1260handling functions. 1261 1262Details for implementing a CPU specific reset handler can be found in 1263Section 8. Details for implementing a platform specific reset handler can be 1264found in the `Porting Guide`_ (see the ``plat_reset_handler()`` function). 1265 1266When adding functionality to a reset handler, keep in mind that if a different 1267reset handling behavior is required between the first and the subsequent 1268invocations of the reset handling code, this should be detected at runtime. 1269In other words, the reset handler should be able to detect whether an action has 1270already been performed and act as appropriate. Possible courses of actions are, 1271e.g. skip the action the second time, or undo/redo it. 1272 1273Configuring secure interrupts 1274----------------------------- 1275 1276The GIC driver is responsible for performing initial configuration of secure 1277interrupts on the platform. To this end, the platform is expected to provide the 1278GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1279interrupt configuration during the driver initialisation. 1280 1281Secure interrupt configuration are specified in an array of secure interrupt 1282properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1283``interrupt_props`` member points to an array of interrupt properties. Each 1284element of the array specifies the interrupt number and its attributes 1285(priority, group, configuration). Each element of the array shall be populated 1286by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1287 1288- 10-bit interrupt number, 1289 1290- 8-bit interrupt priority, 1291 1292- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1293 ``INTR_TYPE_NS``), 1294 1295- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1296 ``GIC_INTR_CFG_EDGE``). 1297 1298CPU specific operations framework 1299--------------------------------- 1300 1301Certain aspects of the Armv8-A architecture are implementation defined, 1302that is, certain behaviours are not architecturally defined, but must be 1303defined and documented by individual processor implementations. TF-A 1304implements a framework which categorises the common implementation defined 1305behaviours and allows a processor to export its implementation of that 1306behaviour. The categories are: 1307 1308#. Processor specific reset sequence. 1309 1310#. Processor specific power down sequences. 1311 1312#. Processor specific register dumping as a part of crash reporting. 1313 1314#. Errata status reporting. 1315 1316Each of the above categories fulfils a different requirement. 1317 1318#. allows any processor specific initialization before the caches and MMU 1319 are turned on, like implementation of errata workarounds, entry into 1320 the intra-cluster coherency domain etc. 1321 1322#. allows each processor to implement the power down sequence mandated in 1323 its Technical Reference Manual (TRM). 1324 1325#. allows a processor to provide additional information to the developer 1326 in the event of a crash, for example Cortex-A53 has registers which 1327 can expose the data cache contents. 1328 1329#. allows a processor to define a function that inspects and reports the status 1330 of all errata workarounds on that processor. 1331 1332Please note that only 2. is mandated by the TRM. 1333 1334The CPU specific operations framework scales to accommodate a large number of 1335different CPUs during power down and reset handling. The platform can specify 1336any CPU optimization it wants to enable for each CPU. It can also specify 1337the CPU errata workarounds to be applied for each CPU type during reset 1338handling by defining CPU errata compile time macros. Details on these macros 1339can be found in the `cpu-specific-build-macros.rst`_ file. 1340 1341The CPU specific operations framework depends on the ``cpu_ops`` structure which 1342needs to be exported for each type of CPU in the platform. It is defined in 1343``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1344``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1345``cpu_reg_dump()``. 1346 1347The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1348suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1349exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1350configuration, these CPU specific files must be included in the build by 1351the platform makefile. The generic CPU specific operations framework code exists 1352in ``lib/cpus/aarch64/cpu_helpers.S``. 1353 1354CPU specific Reset Handling 1355~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1356 1357After a reset, the state of the CPU when it calls generic reset handler is: 1358MMU turned off, both instruction and data caches turned off and not part 1359of any coherency domain. 1360 1361The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1362the platform to perform any system initialization required and any system 1363errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1364the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1365array and returns it. Note that only the part number and implementer fields 1366in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1367the returned ``cpu_ops`` is then invoked which executes the required reset 1368handling for that CPU and also any errata workarounds enabled by the platform. 1369This function must preserve the values of general purpose registers x20 to x29. 1370 1371Refer to Section "Guidelines for Reset Handlers" for general guidelines 1372regarding placement of code in a reset handler. 1373 1374CPU specific power down sequence 1375~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1376 1377During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1378entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly 1379retrieved during power down sequences. 1380 1381Various CPU drivers register handlers to perform power down at certain power 1382levels for that specific CPU. The PSCI service, upon receiving a power down 1383request, determines the highest power level at which to execute power down 1384sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1385pick the right power down handler for the requested level. The function 1386retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1387retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1388requested power level is higher than what a CPU driver supports, the handler 1389registered for highest level is invoked. 1390 1391At runtime the platform hooks for power down are invoked by the PSCI service to 1392perform platform specific operations during a power down sequence, for example 1393turning off CCI coherency during a cluster power down. 1394 1395CPU specific register reporting during crash 1396~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1397 1398If the crash reporting is enabled in BL31, when a crash occurs, the crash 1399reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1400``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1401``cpu_ops`` is invoked, which then returns the CPU specific register values to 1402be reported and a pointer to the ASCII list of register names in a format 1403expected by the crash reporting framework. 1404 1405CPU errata status reporting 1406~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1407 1408Errata workarounds for CPUs supported in TF-A are applied during both cold and 1409warm boots, shortly after reset. Individual Errata workarounds are enabled as 1410build options. Some errata workarounds have potential run-time implications; 1411therefore some are enabled by default, others not. Platform ports shall 1412override build options to enable or disable errata as appropriate. The CPU 1413drivers take care of applying errata workarounds that are enabled and applicable 1414to a given CPU. Refer to the section titled *CPU Errata Workarounds* in `CPUBM`_ 1415for more information. 1416 1417Functions in CPU drivers that apply errata workaround must follow the 1418conventions listed below. 1419 1420The errata workaround must be authored as two separate functions: 1421 1422- One that checks for errata. This function must determine whether that errata 1423 applies to the current CPU. Typically this involves matching the current 1424 CPUs revision and variant against a value that's known to be affected by the 1425 errata. If the function determines that the errata applies to this CPU, it 1426 must return ``ERRATA_APPLIES``; otherwise, it must return 1427 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and 1428 ``cpu_rev_var_ls`` functions may come in handy for this purpose. 1429 1430For an errata identified as ``E``, the check function must be named 1431``check_errata_E``. 1432 1433This function will be invoked at different times, both from assembly and from 1434C run time. Therefore it must follow AAPCS, and must not use stack. 1435 1436- Another one that applies the errata workaround. This function would call the 1437 check function described above, and applies errata workaround if required. 1438 1439CPU drivers that apply errata workaround can optionally implement an assembly 1440function that report the status of errata workarounds pertaining to that CPU. 1441For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops`` 1442macro, the errata reporting function, if it exists, must be named 1443``cpux_errata_report``. This function will always be called with MMU enabled; it 1444must follow AAPCS and may use stack. 1445 1446In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1447runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata 1448status reporting function, if one exists, for that type of CPU. 1449 1450To report the status of each errata workaround, the function shall use the 1451assembler macro ``report_errata``, passing it: 1452 1453- The build option that enables the errata; 1454 1455- The name of the CPU: this must be the same identifier that CPU driver 1456 registered itself with, using ``declare_cpu_ops``; 1457 1458- And the errata identifier: the identifier must match what's used in the 1459 errata's check function described above. 1460 1461The errata status reporting function will be called once per CPU type/errata 1462combination during the software's active life time. 1463 1464It's expected that whenever an errata workaround is submitted to TF-A, the 1465errata reporting function is appropriately extended to report its status as 1466well. 1467 1468Reporting the status of errata workaround is for informational purpose only; it 1469has no functional significance. 1470 1471Memory layout of BL images 1472-------------------------- 1473 1474Each bootloader image can be divided in 2 parts: 1475 1476- the static contents of the image. These are data actually stored in the 1477 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1478 sections; 1479 1480- the run-time contents of the image. These are data that don't occupy any 1481 space in the binary on the disk. The ELF binary just contains some 1482 metadata indicating where these data will be stored at run-time and the 1483 corresponding sections need to be allocated and initialized at run-time. 1484 In the ELF terminology, they are called ``NOBITS`` sections. 1485 1486All PROGBITS sections are grouped together at the beginning of the image, 1487followed by all NOBITS sections. This is true for all TF-A images and it is 1488governed by the linker scripts. This ensures that the raw binary images are 1489as small as possible. If a NOBITS section was inserted in between PROGBITS 1490sections then the resulting binary file would contain zero bytes in place of 1491this NOBITS section, making the image unnecessarily bigger. Smaller images 1492allow faster loading from the FIP to the main memory. 1493 1494Linker scripts and symbols 1495~~~~~~~~~~~~~~~~~~~~~~~~~~ 1496 1497Each bootloader stage image layout is described by its own linker script. The 1498linker scripts export some symbols into the program symbol table. Their values 1499correspond to particular addresses. TF-A code can refer to these symbols to 1500figure out the image memory layout. 1501 1502Linker symbols follow the following naming convention in TF-A. 1503 1504- ``__<SECTION>_START__`` 1505 1506 Start address of a given section named ``<SECTION>``. 1507 1508- ``__<SECTION>_END__`` 1509 1510 End address of a given section named ``<SECTION>``. If there is an alignment 1511 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1512 to the end address of the section's actual contents, rounded up to the right 1513 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1514 actual end address of the section's contents. 1515 1516- ``__<SECTION>_UNALIGNED_END__`` 1517 1518 End address of a given section named ``<SECTION>`` without any padding or 1519 rounding up due to some alignment constraint. 1520 1521- ``__<SECTION>_SIZE__`` 1522 1523 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1524 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1525 corresponds to the size of the section's actual contents, rounded up to the 1526 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1527 to know the actual size of the section's contents. 1528 1529- ``__<SECTION>_UNALIGNED_SIZE__`` 1530 1531 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1532 rounding up due to some alignment constraint. In other words, 1533 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1534 1535Some of the linker symbols are mandatory as TF-A code relies on them to be 1536defined. They are listed in the following subsections. Some of them must be 1537provided for each bootloader stage and some are specific to a given bootloader 1538stage. 1539 1540The linker scripts define some extra, optional symbols. They are not actually 1541used by any code but they help in understanding the bootloader images' memory 1542layout as they are easy to spot in the link map files. 1543 1544Common linker symbols 1545^^^^^^^^^^^^^^^^^^^^^ 1546 1547All BL images share the following requirements: 1548 1549- The BSS section must be zero-initialised before executing any C code. 1550- The coherent memory section (if enabled) must be zero-initialised as well. 1551- The MMU setup code needs to know the extents of the coherent and read-only 1552 memory regions to set the right memory attributes. When 1553 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1554 read-only memory region is divided between code and data. 1555 1556The following linker symbols are defined for this purpose: 1557 1558- ``__BSS_START__`` 1559- ``__BSS_SIZE__`` 1560- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1561- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1562- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1563- ``__RO_START__`` 1564- ``__RO_END__`` 1565- ``__TEXT_START__`` 1566- ``__TEXT_END__`` 1567- ``__RODATA_START__`` 1568- ``__RODATA_END__`` 1569 1570BL1's linker symbols 1571^^^^^^^^^^^^^^^^^^^^ 1572 1573BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1574it is entirely executed in place but it needs some read-write memory for its 1575mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1576relocated from ROM to RAM before executing any C code. 1577 1578The following additional linker symbols are defined for BL1: 1579 1580- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1581 and ``.data`` section in ROM. 1582- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1583 aligned on a 16-byte boundary. 1584- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1585 copied over. Must be aligned on a 16-byte boundary. 1586- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1587- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1588- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1589 1590How to choose the right base addresses for each bootloader stage image 1591~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1592 1593There is currently no support for dynamic image loading in TF-A. This means 1594that all bootloader images need to be linked against their ultimate runtime 1595locations and the base addresses of each image must be chosen carefully such 1596that images don't overlap each other in an undesired way. As the code grows, 1597the base addresses might need adjustments to cope with the new memory layout. 1598 1599The memory layout is completely specific to the platform and so there is no 1600general recipe for choosing the right base addresses for each bootloader image. 1601However, there are tools to aid in understanding the memory layout. These are 1602the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1603being the stage bootloader. They provide a detailed view of the memory usage of 1604each image. Among other useful information, they provide the end address of 1605each image. 1606 1607- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1608- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1609- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1610- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1611 1612For each bootloader image, the platform code must provide its start address 1613as well as a limit address that it must not overstep. The latter is used in the 1614linker scripts to check that the image doesn't grow past that address. If that 1615happens, the linker will issue a message similar to the following: 1616 1617:: 1618 1619 aarch64-none-elf-ld: BLx has exceeded its limit. 1620 1621Additionally, if the platform memory layout implies some image overlaying like 1622on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1623sections must not overstep. The platform code must provide those. 1624 1625TF-A does not provide any mechanism to verify at boot time that the memory 1626to load a new image is free to prevent overwriting a previously loaded image. 1627The platform must specify the memory available in the system for all the 1628relevant BL images to be loaded. 1629 1630For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1631return the region defined by the platform where BL1 intends to load BL2. The 1632``load_image()`` function performs bounds check for the image size based on the 1633base and maximum image size provided by the platforms. Platforms must take 1634this behaviour into account when defining the base/size for each of the images. 1635 1636Memory layout on Arm development platforms 1637^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1638 1639The following list describes the memory layout on the Arm development platforms: 1640 1641- A 4KB page of shared memory is used for communication between Trusted 1642 Firmware and the platform's power controller. This is located at the base of 1643 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1644 images is reduced by the size of the shared memory. 1645 1646 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1647 this is also used for the MHU payload when passing messages to and from the 1648 SCP. 1649 1650- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1651 and also the dynamic firmware configurations. 1652 1653- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1654 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1655 data are relocated to the top of Trusted SRAM at runtime. 1656 1657- BL2 is loaded below BL1 RW 1658 1659- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1660 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1661 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1662 remain valid only until execution reaches the EL3 Runtime Software entry 1663 point during a cold boot. 1664 1665- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1666 region and transfered to the SCP before being overwritten by EL3 Runtime 1667 Software. 1668 1669- BL32 (for AArch64) can be loaded in one of the following locations: 1670 1671 - Trusted SRAM 1672 - Trusted DRAM (FVP only) 1673 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1674 controller) 1675 1676 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1677 BL31. 1678 1679The location of the BL32 image will result in different memory maps. This is 1680illustrated for both FVP and Juno in the following diagrams, using the TSP as 1681an example. 1682 1683Note: Loading the BL32 image in TZC secured DRAM doesn't change the memory 1684layout of the other images in Trusted SRAM. 1685 1686CONFIG section in memory layouts shown below contains: 1687 1688:: 1689 1690 +--------------------+ 1691 |bl2_mem_params_descs| 1692 |--------------------| 1693 | fw_configs | 1694 +--------------------+ 1695 1696``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1697BL image during boot. 1698 1699``fw_configs`` includes soc_fw_config, tos_fw_config and tb_fw_config. 1700 1701**FVP with TSP in Trusted SRAM with firmware configs :** 1702(These diagrams only cover the AArch64 case) 1703 1704:: 1705 1706 DRAM 1707 0xffffffff +----------+ 1708 : : 1709 |----------| 1710 |HW_CONFIG | 1711 0x83000000 |----------| (non-secure) 1712 | | 1713 0x80000000 +----------+ 1714 1715 Trusted SRAM 1716 0x04040000 +----------+ loaded by BL2 +----------------+ 1717 | BL1 (rw) | <<<<<<<<<<<<< | | 1718 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1719 | BL2 | <<<<<<<<<<<<< | | 1720 |----------| <<<<<<<<<<<<< |----------------| 1721 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1722 | | <<<<<<<<<<<<< |----------------| 1723 | | <<<<<<<<<<<<< | BL32 | 1724 0x04002000 +----------+ +----------------+ 1725 | CONFIG | 1726 0x04001000 +----------+ 1727 | Shared | 1728 0x04000000 +----------+ 1729 1730 Trusted ROM 1731 0x04000000 +----------+ 1732 | BL1 (ro) | 1733 0x00000000 +----------+ 1734 1735**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1736 1737:: 1738 1739 DRAM 1740 0xffffffff +--------------+ 1741 : : 1742 |--------------| 1743 | HW_CONFIG | 1744 0x83000000 |--------------| (non-secure) 1745 | | 1746 0x80000000 +--------------+ 1747 1748 Trusted DRAM 1749 0x08000000 +--------------+ 1750 | BL32 | 1751 0x06000000 +--------------+ 1752 1753 Trusted SRAM 1754 0x04040000 +--------------+ loaded by BL2 +----------------+ 1755 | BL1 (rw) | <<<<<<<<<<<<< | | 1756 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1757 | BL2 | <<<<<<<<<<<<< | | 1758 |--------------| <<<<<<<<<<<<< |----------------| 1759 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1760 | | +----------------+ 1761 +--------------+ 1762 | CONFIG | 1763 0x04001000 +--------------+ 1764 | Shared | 1765 0x04000000 +--------------+ 1766 1767 Trusted ROM 1768 0x04000000 +--------------+ 1769 | BL1 (ro) | 1770 0x00000000 +--------------+ 1771 1772**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1773 1774:: 1775 1776 DRAM 1777 0xffffffff +----------+ 1778 | BL32 | (secure) 1779 0xff000000 +----------+ 1780 | | 1781 |----------| 1782 |HW_CONFIG | 1783 0x83000000 |----------| (non-secure) 1784 | | 1785 0x80000000 +----------+ 1786 1787 Trusted SRAM 1788 0x04040000 +----------+ loaded by BL2 +----------------+ 1789 | BL1 (rw) | <<<<<<<<<<<<< | | 1790 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1791 | BL2 | <<<<<<<<<<<<< | | 1792 |----------| <<<<<<<<<<<<< |----------------| 1793 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1794 | | +----------------+ 1795 0x04002000 +----------+ 1796 | CONFIG | 1797 0x04001000 +----------+ 1798 | Shared | 1799 0x04000000 +----------+ 1800 1801 Trusted ROM 1802 0x04000000 +----------+ 1803 | BL1 (ro) | 1804 0x00000000 +----------+ 1805 1806**Juno with BL32 in Trusted SRAM :** 1807 1808:: 1809 1810 Flash0 1811 0x0C000000 +----------+ 1812 : : 1813 0x0BED0000 |----------| 1814 | BL1 (ro) | 1815 0x0BEC0000 |----------| 1816 : : 1817 0x08000000 +----------+ BL31 is loaded 1818 after SCP_BL2 has 1819 Trusted SRAM been sent to SCP 1820 0x04040000 +----------+ loaded by BL2 +----------------+ 1821 | BL1 (rw) | <<<<<<<<<<<<< | | 1822 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1823 | BL2 | <<<<<<<<<<<<< | | 1824 |----------| <<<<<<<<<<<<< |----------------| 1825 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1826 |----------| <<<<<<<<<<<<< |----------------| 1827 | | <<<<<<<<<<<<< | BL32 | 1828 | | +----------------+ 1829 | | 1830 0x04001000 +----------+ 1831 | MHU | 1832 0x04000000 +----------+ 1833 1834**Juno with BL32 in TZC-secured DRAM :** 1835 1836:: 1837 1838 DRAM 1839 0xFFE00000 +----------+ 1840 | BL32 | (secure) 1841 0xFF000000 |----------| 1842 | | 1843 : : (non-secure) 1844 | | 1845 0x80000000 +----------+ 1846 1847 Flash0 1848 0x0C000000 +----------+ 1849 : : 1850 0x0BED0000 |----------| 1851 | BL1 (ro) | 1852 0x0BEC0000 |----------| 1853 : : 1854 0x08000000 +----------+ BL31 is loaded 1855 after SCP_BL2 has 1856 Trusted SRAM been sent to SCP 1857 0x04040000 +----------+ loaded by BL2 +----------------+ 1858 | BL1 (rw) | <<<<<<<<<<<<< | | 1859 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1860 | BL2 | <<<<<<<<<<<<< | | 1861 |----------| <<<<<<<<<<<<< |----------------| 1862 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1863 |----------| +----------------+ 1864 0x04001000 +----------+ 1865 | MHU | 1866 0x04000000 +----------+ 1867 1868Library at ROM 1869--------------- 1870 1871Please refer to the `ROMLIB Design`_ document. 1872 1873Firmware Image Package (FIP) 1874---------------------------- 1875 1876Using a Firmware Image Package (FIP) allows for packing bootloader images (and 1877potentially other payloads) into a single archive that can be loaded by TF-A 1878from non-volatile platform storage. A driver to load images from a FIP has 1879been added to the storage layer and allows a package to be read from supported 1880platform storage. A tool to create Firmware Image Packages is also provided 1881and described below. 1882 1883Firmware Image Package layout 1884~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1885 1886The FIP layout consists of a table of contents (ToC) followed by payload data. 1887The ToC itself has a header followed by one or more table entries. The ToC is 1888terminated by an end marker entry, and since the size of the ToC is 0 bytes, 1889the offset equals the total size of the FIP file. All ToC entries describe some 1890payload data that has been appended to the end of the binary package. With the 1891information provided in the ToC entry the corresponding payload data can be 1892retrieved. 1893 1894:: 1895 1896 ------------------ 1897 | ToC Header | 1898 |----------------| 1899 | ToC Entry 0 | 1900 |----------------| 1901 | ToC Entry 1 | 1902 |----------------| 1903 | ToC End Marker | 1904 |----------------| 1905 | | 1906 | Data 0 | 1907 | | 1908 |----------------| 1909 | | 1910 | Data 1 | 1911 | | 1912 ------------------ 1913 1914The ToC header and entry formats are described in the header file 1915``include/tools_share/firmware_image_package.h``. This file is used by both the 1916tool and TF-A. 1917 1918The ToC header has the following fields: 1919 1920:: 1921 1922 `name`: The name of the ToC. This is currently used to validate the header. 1923 `serial_number`: A non-zero number provided by the creation tool 1924 `flags`: Flags associated with this data. 1925 Bits 0-31: Reserved 1926 Bits 32-47: Platform defined 1927 Bits 48-63: Reserved 1928 1929A ToC entry has the following fields: 1930 1931:: 1932 1933 `uuid`: All files are referred to by a pre-defined Universally Unique 1934 IDentifier [UUID] . The UUIDs are defined in 1935 `include/tools_share/firmware_image_package.h`. The platform translates 1936 the requested image name into the corresponding UUID when accessing the 1937 package. 1938 `offset_address`: The offset address at which the corresponding payload data 1939 can be found. The offset is calculated from the ToC base address. 1940 `size`: The size of the corresponding payload data in bytes. 1941 `flags`: Flags associated with this entry. None are yet defined. 1942 1943Firmware Image Package creation tool 1944~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1945 1946The FIP creation tool can be used to pack specified images into a binary 1947package that can be loaded by TF-A from platform storage. The tool currently 1948only supports packing bootloader images. Additional image definitions can be 1949added to the tool as required. 1950 1951The tool can be found in ``tools/fiptool``. 1952 1953Loading from a Firmware Image Package (FIP) 1954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1955 1956The Firmware Image Package (FIP) driver can load images from a binary package on 1957non-volatile platform storage. For the Arm development platforms, this is 1958currently NOR FLASH. 1959 1960Bootloader images are loaded according to the platform policy as specified by 1961the function ``plat_get_image_source()``. For the Arm development platforms, this 1962means the platform will attempt to load images from a Firmware Image Package 1963located at the start of NOR FLASH0. 1964 1965The Arm development platforms' policy is to only allow loading of a known set of 1966images. The platform policy can be modified to allow additional images. 1967 1968Use of coherent memory in TF-A 1969------------------------------ 1970 1971There might be loss of coherency when physical memory with mismatched 1972shareability, cacheability and memory attributes is accessed by multiple CPUs 1973(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 1974in TF-A during power up/down sequences when coherency, MMU and caches are 1975turned on/off incrementally. 1976 1977TF-A defines coherent memory as a region of memory with Device nGnRE attributes 1978in the translation tables. The translation granule size in TF-A is 4KB. This 1979is the smallest possible size of the coherent memory region. 1980 1981By default, all data structures which are susceptible to accesses with 1982mismatched attributes from various CPUs are allocated in a coherent memory 1983region (refer to section 2.1 of `Porting Guide`_). The coherent memory region 1984accesses are Outer Shareable, non-cacheable and they can be accessed 1985with the Device nGnRE attributes when the MMU is turned on. Hence, at the 1986expense of at least an extra page of memory, TF-A is able to work around 1987coherency issues due to mismatched memory attributes. 1988 1989The alternative to the above approach is to allocate the susceptible data 1990structures in Normal WriteBack WriteAllocate Inner shareable memory. This 1991approach requires the data structures to be designed so that it is possible to 1992work around the issue of mismatched memory attributes by performing software 1993cache maintenance on them. 1994 1995Disabling the use of coherent memory in TF-A 1996~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1997 1998It might be desirable to avoid the cost of allocating coherent memory on 1999platforms which are memory constrained. TF-A enables inclusion of coherent 2000memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2001This flag is enabled by default. It can be disabled to choose the second 2002approach described above. 2003 2004The below sections analyze the data structures allocated in the coherent memory 2005region and the changes required to allocate them in normal memory. 2006 2007Coherent memory usage in PSCI implementation 2008~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2009 2010The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2011tree information for state management of power domains. By default, this data 2012structure is allocated in the coherent memory region in TF-A because it can be 2013accessed by multiple CPUs, either with caches enabled or disabled. 2014 2015.. code:: c 2016 2017 typedef struct non_cpu_pwr_domain_node { 2018 /* 2019 * Index of the first CPU power domain node level 0 which has this node 2020 * as its parent. 2021 */ 2022 unsigned int cpu_start_idx; 2023 2024 /* 2025 * Number of CPU power domains which are siblings of the domain indexed 2026 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2027 * -> cpu_start_idx + ncpus' have this node as their parent. 2028 */ 2029 unsigned int ncpus; 2030 2031 /* 2032 * Index of the parent power domain node. 2033 */ 2034 unsigned int parent_node; 2035 2036 plat_local_state_t local_state; 2037 2038 unsigned char level; 2039 2040 /* For indexing the psci_lock array*/ 2041 unsigned char lock_index; 2042 } non_cpu_pd_node_t; 2043 2044In order to move this data structure to normal memory, the use of each of its 2045fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2046``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2047them from coherent memory involves only doing a clean and invalidate of the 2048cache lines after these fields are written. 2049 2050The field ``local_state`` can be concurrently accessed by multiple CPUs in 2051different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2052mutual exclusion to this field and a clean and invalidate is needed after it 2053is written. 2054 2055Bakery lock data 2056~~~~~~~~~~~~~~~~ 2057 2058The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2059and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2060defined as follows: 2061 2062.. code:: c 2063 2064 typedef struct bakery_lock { 2065 /* 2066 * The lock_data is a bit-field of 2 members: 2067 * Bit[0] : choosing. This field is set when the CPU is 2068 * choosing its bakery number. 2069 * Bits[1 - 15] : number. This is the bakery number allocated. 2070 */ 2071 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2072 } bakery_lock_t; 2073 2074It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2075fields can be read by all CPUs but only written to by the owning CPU. 2076 2077Depending upon the data cache line size, the per-CPU fields of the 2078``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2079These per-CPU fields can be read and written during lock contention by multiple 2080CPUs with mismatched memory attributes. Since these fields are a part of the 2081lock implementation, they do not have access to any other locking primitive to 2082safeguard against the resulting coherency issues. As a result, simple software 2083cache maintenance is not enough to allocate them in coherent memory. Consider 2084the following example. 2085 2086CPU0 updates its per-CPU field with data cache enabled. This write updates a 2087local cache line which contains a copy of the fields for other CPUs as well. Now 2088CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2089disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2090its field in any other cache line in the system. This operation will invalidate 2091the update made by CPU0 as well. 2092 2093To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2094has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2095algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2096for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2097needed for a CPU into a section ``bakery_lock``. The linker allocates the memory 2098for other cores by using the total size allocated for the bakery_lock section 2099and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2100perform software cache maintenance on the lock data structure without running 2101into coherency issues associated with mismatched attributes. 2102 2103The bakery lock data structure ``bakery_info_t`` is defined for use when 2104``USE_COHERENT_MEM`` is disabled as follows: 2105 2106.. code:: c 2107 2108 typedef struct bakery_info { 2109 /* 2110 * The lock_data is a bit-field of 2 members: 2111 * Bit[0] : choosing. This field is set when the CPU is 2112 * choosing its bakery number. 2113 * Bits[1 - 15] : number. This is the bakery number allocated. 2114 */ 2115 volatile uint16_t lock_data; 2116 } bakery_info_t; 2117 2118The ``bakery_info_t`` represents a single per-CPU field of one lock and 2119the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2120system represents the complete bakery lock. The view in memory for a system 2121with n bakery locks are: 2122 2123:: 2124 2125 bakery_lock section start 2126 |----------------| 2127 | `bakery_info_t`| <-- Lock_0 per-CPU field 2128 | Lock_0 | for CPU0 2129 |----------------| 2130 | `bakery_info_t`| <-- Lock_1 per-CPU field 2131 | Lock_1 | for CPU0 2132 |----------------| 2133 | .... | 2134 |----------------| 2135 | `bakery_info_t`| <-- Lock_N per-CPU field 2136 | Lock_N | for CPU0 2137 ------------------ 2138 | XXXXX | 2139 | Padding to | 2140 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2141 | Granule | continuous memory for remaining CPUs. 2142 ------------------ 2143 | `bakery_info_t`| <-- Lock_0 per-CPU field 2144 | Lock_0 | for CPU1 2145 |----------------| 2146 | `bakery_info_t`| <-- Lock_1 per-CPU field 2147 | Lock_1 | for CPU1 2148 |----------------| 2149 | .... | 2150 |----------------| 2151 | `bakery_info_t`| <-- Lock_N per-CPU field 2152 | Lock_N | for CPU1 2153 ------------------ 2154 | XXXXX | 2155 | Padding to | 2156 | next Cache WB | 2157 | Granule | 2158 ------------------ 2159 2160Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2161operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2162``bakery_lock`` section need to be fetched and appropriate cache operations need 2163to be performed for each access. 2164 2165On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2166driver (``arm_lock``). 2167 2168Non Functional Impact of removing coherent memory 2169~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2170 2171Removal of the coherent memory region leads to the additional software overhead 2172of performing cache maintenance for the affected data structures. However, since 2173the memory where the data structures are allocated is cacheable, the overhead is 2174mostly mitigated by an increase in performance. 2175 2176There is however a performance impact for bakery locks, due to: 2177 2178- Additional cache maintenance operations, and 2179- Multiple cache line reads for each lock operation, since the bakery locks 2180 for each CPU are distributed across different cache lines. 2181 2182The implementation has been optimized to minimize this additional overhead. 2183Measurements indicate that when bakery locks are allocated in Normal memory, the 2184minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2185in Device memory the same is 2 micro seconds. The measurements were done on the 2186Juno Arm development platform. 2187 2188As mentioned earlier, almost a page of memory can be saved by disabling 2189``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2190whether coherent memory should be used. If a platform disables 2191``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2192optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2193`Porting Guide`_). Refer to the reference platform code for examples. 2194 2195Isolating code and read-only data on separate memory pages 2196---------------------------------------------------------- 2197 2198In the Armv8-A VMSA, translation table entries include fields that define the 2199properties of the target memory region, such as its access permissions. The 2200smallest unit of memory that can be addressed by a translation table entry is 2201a memory page. Therefore, if software needs to set different permissions on two 2202memory regions then it needs to map them using different memory pages. 2203 2204The default memory layout for each BL image is as follows: 2205 2206:: 2207 2208 | ... | 2209 +-------------------+ 2210 | Read-write data | 2211 +-------------------+ Page boundary 2212 | <Padding> | 2213 +-------------------+ 2214 | Exception vectors | 2215 +-------------------+ 2 KB boundary 2216 | <Padding> | 2217 +-------------------+ 2218 | Read-only data | 2219 +-------------------+ 2220 | Code | 2221 +-------------------+ BLx_BASE 2222 2223Note: The 2KB alignment for the exception vectors is an architectural 2224requirement. 2225 2226The read-write data start on a new memory page so that they can be mapped with 2227read-write permissions, whereas the code and read-only data below are configured 2228as read-only. 2229 2230However, the read-only data are not aligned on a page boundary. They are 2231contiguous to the code. Therefore, the end of the code section and the beginning 2232of the read-only data one might share a memory page. This forces both to be 2233mapped with the same memory attributes. As the code needs to be executable, this 2234means that the read-only data stored on the same memory page as the code are 2235executable as well. This could potentially be exploited as part of a security 2236attack. 2237 2238TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2239read-only data on separate memory pages. This in turn allows independent control 2240of the access permissions for the code and read-only data. In this case, 2241platform code gets a finer-grained view of the image layout and can 2242appropriately map the code region as executable and the read-only data as 2243execute-never. 2244 2245This has an impact on memory footprint, as padding bytes need to be introduced 2246between the code and read-only data to ensure the segregation of the two. To 2247limit the memory cost, this flag also changes the memory layout such that the 2248code and exception vectors are now contiguous, like so: 2249 2250:: 2251 2252 | ... | 2253 +-------------------+ 2254 | Read-write data | 2255 +-------------------+ Page boundary 2256 | <Padding> | 2257 +-------------------+ 2258 | Read-only data | 2259 +-------------------+ Page boundary 2260 | <Padding> | 2261 +-------------------+ 2262 | Exception vectors | 2263 +-------------------+ 2 KB boundary 2264 | <Padding> | 2265 +-------------------+ 2266 | Code | 2267 +-------------------+ BLx_BASE 2268 2269With this more condensed memory layout, the separation of read-only data will 2270add zero or one page to the memory footprint of each BL image. Each platform 2271should consider the trade-off between memory footprint and security. 2272 2273This build flag is disabled by default, minimising memory footprint. On Arm 2274platforms, it is enabled. 2275 2276Publish and Subscribe Framework 2277------------------------------- 2278 2279The Publish and Subscribe Framework allows EL3 components to define and publish 2280events, to which other EL3 components can subscribe. 2281 2282The following macros are provided by the framework: 2283 2284- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2285 the event name, which must be a valid C identifier. All calls to 2286 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2287 ``pubsub_events.h``. 2288 2289- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2290 subscribed handlers and calling them in turn. The handlers will be passed the 2291 parameter ``arg``. The expected use-case is to broadcast an event. 2292 2293- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2294 ``NULL`` is passed to subscribed handlers. 2295 2296- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2297 subscribe to ``event``. The handler will be executed whenever the ``event`` 2298 is published. 2299 2300- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2301 subscribed for ``event``. ``subscriber`` must be a local variable of type 2302 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2303 iteration. This macro can be used for those patterns that none of the 2304 ``PUBLISH_EVENT_*()`` macros cover. 2305 2306Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2307result in build error. Subscribing to an undefined event however won't. 2308 2309Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2310signature: 2311 2312:: 2313 2314 typedef void* (*pubsub_cb_t)(const void *arg); 2315 2316There may be arbitrary number of handlers registered to the same event. The 2317order in which subscribed handlers are notified when that event is published is 2318not defined. Subscribed handlers may be executed in any order; handlers should 2319not assume any relative ordering amongst them. 2320 2321Publishing an event on a PE will result in subscribed handlers executing on that 2322PE only; it won't cause handlers to execute on a different PE. 2323 2324Note that publishing an event on a PE blocks until all the subscribed handlers 2325finish executing on the PE. 2326 2327TF-A generic code publishes and subscribes to some events within. Platform 2328ports are discouraged from subscribing to them. These events may be withdrawn, 2329renamed, or have their semantics altered in the future. Platforms may however 2330register, publish, and subscribe to platform-specific events. 2331 2332Publish and Subscribe Example 2333~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2334 2335A publisher that wants to publish event ``foo`` would: 2336 2337- Define the event ``foo`` in the ``pubsub_events.h``. 2338 2339 :: 2340 2341 REGISTER_PUBSUB_EVENT(foo); 2342 2343- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2344 publish the event at the appropriate path and time of execution. 2345 2346A subscriber that wants to subscribe to event ``foo`` published above would 2347implement: 2348 2349.. code:: c 2350 2351 void *foo_handler(const void *arg) 2352 { 2353 void *result; 2354 2355 /* Do handling ... */ 2356 2357 return result; 2358 } 2359 2360 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2361 2362 2363Reclaiming the BL31 initialization code 2364~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2365 2366A significant amount of the code used for the initialization of BL31 is never 2367needed again after boot time. In order to reduce the runtime memory 2368footprint, the memory used for this code can be reclaimed after initialization 2369has finished and be used for runtime data. 2370 2371The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2372with a ``.text.init.*`` attribute which can be filtered and placed suitably 2373within the BL image for later reclamation by the platform. The platform can 2374specify the filter and the memory region for this init section in BL31 via the 2375plat.ld.S linker script. For example, on the FVP, this section is placed 2376overlapping the secondary CPU stacks so that after the cold boot is done, this 2377memory can be reclaimed for the stacks. The init memory section is initially 2378mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2379completed, the FVP changes the attributes of this section to ``RW``, 2380``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2381are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2382section section can be reclaimed for any data which is accessed after cold 2383boot initialization and it is upto the platform to make the decision. 2384 2385Performance Measurement Framework 2386--------------------------------- 2387 2388The Performance Measurement Framework (PMF) facilitates collection of 2389timestamps by registered services and provides interfaces to retrieve them 2390from within TF-A. A platform can choose to expose appropriate SMCs to 2391retrieve these collected timestamps. 2392 2393By default, the global physical counter is used for the timestamp 2394value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2395timestamps captured by other CPUs. 2396 2397Timestamp identifier format 2398~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2399 2400A PMF timestamp is uniquely identified across the system via the 2401timestamp ID or ``tid``. The ``tid`` is composed as follows: 2402 2403:: 2404 2405 Bits 0-7: The local timestamp identifier. 2406 Bits 8-9: Reserved. 2407 Bits 10-15: The service identifier. 2408 Bits 16-31: Reserved. 2409 2410#. The service identifier. Each PMF service is identified by a 2411 service name and a service identifier. Both the service name and 2412 identifier are unique within the system as a whole. 2413 2414#. The local timestamp identifier. This identifier is unique within a given 2415 service. 2416 2417Registering a PMF service 2418~~~~~~~~~~~~~~~~~~~~~~~~~ 2419 2420To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2421is used. The arguments required are the service name, the service ID, 2422the total number of local timestamps to be captured and a set of flags. 2423 2424The ``flags`` field can be specified as a bitwise-OR of the following values: 2425 2426:: 2427 2428 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2429 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2430 2431The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2432timestamps in a PMF specific linker section at build time. 2433Additionally, it defines necessary functions to capture and 2434retrieve a particular timestamp for the given service at runtime. 2435 2436The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2437from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2438``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2439accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2440macro but additionally supports retrieving timestamps using SMCs. 2441 2442Capturing a timestamp 2443~~~~~~~~~~~~~~~~~~~~~ 2444 2445PMF timestamps are stored in a per-service timestamp region. On a 2446system with multiple CPUs, each timestamp is captured and stored 2447in a per-CPU cache line aligned memory region. 2448 2449Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2450used to capture a timestamp at the location where it is used. The macro 2451takes the service name, a local timestamp identifier and a flag as arguments. 2452 2453The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2454instructs PMF to do cache maintenance following the capture. Cache 2455maintenance is required if any of the service's timestamps are captured 2456with data cache disabled. 2457 2458To capture a timestamp in assembly code, the caller should use 2459``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2460calculate the address of where the timestamp would be stored. The 2461caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2462and store it at the determined address for later retrieval. 2463 2464Retrieving a timestamp 2465~~~~~~~~~~~~~~~~~~~~~~ 2466 2467From within TF-A, timestamps for individual CPUs can be retrieved using either 2468``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2469These macros accept the CPU's MPIDR value, or its ordinal position 2470respectively. 2471 2472From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2473into ``pmf_smc_handler()``. 2474 2475.. code:: c 2476 2477 Interface : pmf_smc_handler() 2478 Argument : unsigned int smc_fid, u_register_t x1, 2479 u_register_t x2, u_register_t x3, 2480 u_register_t x4, void *cookie, 2481 void *handle, u_register_t flags 2482 Return : uintptr_t 2483 2484 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2485 when the caller of the SMC is running in AArch32 mode 2486 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2487 x1: Timestamp identifier. 2488 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2489 This can be the `mpidr` of a different core to the one initiating 2490 the SMC. In that case, service specific cache maintenance may be 2491 required to ensure the updated copy of the timestamp is returned. 2492 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2493 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2494 cache invalidate before reading the timestamp. This ensures 2495 an updated copy is returned. 2496 2497The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2498in this implementation. 2499 2500PMF code structure 2501~~~~~~~~~~~~~~~~~~ 2502 2503#. ``pmf_main.c`` consists of core functions that implement service registration, 2504 initialization, storing, dumping and retrieving timestamps. 2505 2506#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2507 2508#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2509 2510#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2511 assembly code. 2512 2513#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2514 2515Armv8-A Architecture Extensions 2516------------------------------- 2517 2518TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2519section lists the usage of Architecture Extensions, and build flags 2520controlling them. 2521 2522In general, and unless individually mentioned, the build options 2523``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to 2524target when building TF-A. Subsequent Arm Architecture Extensions are backward 2525compatible with previous versions. 2526 2527The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a 2528valid numeric value. These build options only control whether or not 2529Architecture Extension-specific code is included in the build. Otherwise, TF-A 2530targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8 2531and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values. 2532 2533See also the *Summary of build options* in `User Guide`_. 2534 2535For details on the Architecture Extension and available features, please refer 2536to the respective Architecture Extension Supplement. 2537 2538Armv8.1-A 2539~~~~~~~~~ 2540 2541This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2542``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2543 2544- The Compare and Swap instruction is used to implement spinlocks. Otherwise, 2545 the load-/store-exclusive instruction pair is used. 2546 2547Armv8.2-A 2548~~~~~~~~~ 2549 2550- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2551 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2552 Processing Elements in the same Inner Shareable domain use the same 2553 translation table entries for a given stage of translation for a particular 2554 translation regime. 2555 2556Armv8.3-A 2557~~~~~~~~~ 2558 2559- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2560 the Non-secure world so that lower ELs are allowed to use them without 2561 causing a trap to EL3. 2562 2563 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2564 must be set to 1. This will add all pointer authentication system registers 2565 to the context that is saved when doing a world switch. 2566 2567 The TF-A itself has support for pointer authentication at runtime 2568 that can be enabled by setting both options ``ENABLE_PAUTH`` and 2569 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2570 BL2, BL31, and the TSP if it is used. 2571 2572 These options are experimental features. 2573 2574 Note that Pointer Authentication is enabled for Non-secure world irrespective 2575 of the value of these build flags if the CPU supports it. 2576 2577 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2578 enabling PAuth is lower because the compiler will use the optimized 2579 PAuth instructions rather than the backwards-compatible ones. 2580 2581Armv7-A 2582~~~~~~~ 2583 2584This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2585 2586There are several Armv7-A extensions available. Obviously the TrustZone 2587extension is mandatory to support the TF-A bootloader and runtime services. 2588 2589Platform implementing an Armv7-A system can to define from its target 2590Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2591``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2592Cortex-A15 target. 2593 2594Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2595Note that using neon at runtime has constraints on non secure wolrd context. 2596TF-A does not yet provide VFP context management. 2597 2598Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2599the toolchain target architecture directive. 2600 2601Platform may choose to not define straight the toolchain target architecture 2602directive by defining ``MARCH32_DIRECTIVE``. 2603I.e: 2604 2605:: 2606 2607 MARCH32_DIRECTIVE := -mach=armv7-a 2608 2609Code Structure 2610-------------- 2611 2612TF-A code is logically divided between the three boot loader stages mentioned 2613in the previous sections. The code is also divided into the following 2614categories (present as directories in the source code): 2615 2616- **Platform specific.** Choice of architecture specific code depends upon 2617 the platform. 2618- **Common code.** This is platform and architecture agnostic code. 2619- **Library code.** This code comprises of functionality commonly used by all 2620 other code. The PSCI implementation and other EL3 runtime frameworks reside 2621 as Library components. 2622- **Stage specific.** Code specific to a boot stage. 2623- **Drivers.** 2624- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2625 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2626 2627Each boot loader stage uses code from one or more of the above mentioned 2628categories. Based upon the above, the code layout looks like this: 2629 2630:: 2631 2632 Directory Used by BL1? Used by BL2? Used by BL31? 2633 bl1 Yes No No 2634 bl2 No Yes No 2635 bl31 No No Yes 2636 plat Yes Yes Yes 2637 drivers Yes No Yes 2638 common Yes Yes Yes 2639 lib Yes Yes Yes 2640 services No No Yes 2641 2642The build system provides a non configurable build option IMAGE_BLx for each 2643boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2644defined by the build system. This enables TF-A to compile certain code only 2645for specific boot loader stages 2646 2647All assembler files have the ``.S`` extension. The linker source files for each 2648boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2649linker scripts which have the extension ``.ld``. 2650 2651FDTs provide a description of the hardware platform and are used by the Linux 2652kernel at boot time. These can be found in the ``fdts`` directory. 2653 2654References 2655---------- 2656 2657.. [#] `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2658.. [#] `Power State Coordination Interface PDD`_ 2659.. [#] `SMC Calling Convention PDD`_ 2660.. [#] `TF-A Interrupt Management Design guide`_. 2661 2662-------------- 2663 2664*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* 2665 2666.. _Reset Design: ./reset-design.rst 2667.. _Porting Guide: ../getting_started/porting-guide.rst 2668.. _Firmware Update: ./firmware-update.rst 2669.. _PSCI PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2670.. _SMC calling convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf 2671.. _PSCI Library integration guide: ../getting_started/psci-lib-integration-guide.rst 2672.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf 2673.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2674.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2675.. _here: ../getting_started/psci-lib-integration-guide.rst 2676.. _cpu-specific-build-macros.rst: ./cpu-specific-build-macros.rst 2677.. _CPUBM: ./cpu-specific-build-macros.rst 2678.. _Arm ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html 2679.. _User Guide: ../getting_started/user-guide.rst 2680.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf 2681.. _TF-A Interrupt Management Design guide: ./interrupt-framework-design.rst 2682.. _Xlat_tables design: xlat-tables-lib-v2-design.rst 2683.. _Exception Handling Framework: exception-handling.rst 2684.. _ROMLIB Design: romlib-design.rst 2685.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a 2686 2687.. |Image 1| image:: diagrams/rt-svc-descs-layout.png?raw=true 2688
