1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/bl_common.h> 9 #include <drivers/console.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 #include <platform.h> 12 #include <tegra_def.h> 13 #include <tegra_private.h> 14 15 /* sets of MMIO ranges setup */ 16 #define MMIO_RANGE_0_ADDR 0x50000000 17 #define MMIO_RANGE_1_ADDR 0x60000000 18 #define MMIO_RANGE_2_ADDR 0x70000000 19 #define MMIO_RANGE_SIZE 0x200000 20 21 /* 22 * Table of regions to map using the MMU. 23 */ 24 static const mmap_region_t tegra_mmap[] = { 25 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 26 MT_DEVICE | MT_RW | MT_SECURE), 27 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 28 MT_DEVICE | MT_RW | MT_SECURE), 29 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 30 MT_DEVICE | MT_RW | MT_SECURE), 31 {0} 32 }; 33 34 /******************************************************************************* 35 * Set up the pagetables as per the platform memory map & initialize the MMU 36 ******************************************************************************/ 37 const mmap_region_t *plat_get_mmio_map(void) 38 { 39 /* MMIO space */ 40 return tegra_mmap; 41 } 42 43 /******************************************************************************* 44 * The Tegra power domain tree has a single system level power domain i.e. a 45 * single root node. The first entry in the power domain descriptor specifies 46 * the number of power domains at the highest power level. 47 ******************************************************************************* 48 */ 49 const unsigned char tegra_power_domain_tree_desc[] = { 50 /* No of root nodes */ 51 1, 52 /* No of clusters */ 53 PLATFORM_CLUSTER_COUNT, 54 /* No of CPU cores - cluster0 */ 55 PLATFORM_MAX_CPUS_PER_CLUSTER, 56 /* No of CPU cores - cluster1 */ 57 PLATFORM_MAX_CPUS_PER_CLUSTER 58 }; 59 60 /******************************************************************************* 61 * This function returns the Tegra default topology tree information. 62 ******************************************************************************/ 63 const unsigned char *plat_get_power_domain_tree_desc(void) 64 { 65 return tegra_power_domain_tree_desc; 66 } 67 68 /******************************************************************************* 69 * Handler to get the System Counter Frequency 70 ******************************************************************************/ 71 unsigned int plat_get_syscnt_freq2(void) 72 { 73 return 19200000; 74 } 75 76 /******************************************************************************* 77 * Maximum supported UART controllers 78 ******************************************************************************/ 79 #define TEGRA210_MAX_UART_PORTS 5 80 81 /******************************************************************************* 82 * This variable holds the UART port base addresses 83 ******************************************************************************/ 84 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 85 0, /* undefined - treated as an error case */ 86 TEGRA_UARTA_BASE, 87 TEGRA_UARTB_BASE, 88 TEGRA_UARTC_BASE, 89 TEGRA_UARTD_BASE, 90 TEGRA_UARTE_BASE, 91 }; 92 93 /******************************************************************************* 94 * Retrieve the UART controller base to be used as the console 95 ******************************************************************************/ 96 uint32_t plat_get_console_from_id(int id) 97 { 98 if (id > TEGRA210_MAX_UART_PORTS) 99 return 0; 100 101 return tegra210_uart_addresses[id]; 102 } 103 104 /******************************************************************************* 105 * Initialize the GIC and SGIs 106 ******************************************************************************/ 107 void plat_gic_setup(void) 108 { 109 tegra_gic_setup(NULL, 0); 110 } 111