1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc380.h> 17 #include <drivers/console.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables.h> 22 #include <plat/common/platform.h> 23 24 #include <gpc.h> 25 #include <imx_uart.h> 26 #include <plat_imx8.h> 27 28 static const mmap_region_t imx_mmap[] = { 29 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */ 30 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */ 31 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */ 32 {0}, 33 }; 34 35 static entry_point_info_t bl32_image_ep_info; 36 static entry_point_info_t bl33_image_ep_info; 37 38 /* get SPSR for BL33 entry */ 39 static uint32_t get_spsr_for_bl33_entry(void) 40 { 41 unsigned long el_status; 42 unsigned long mode; 43 uint32_t spsr; 44 45 /* figure out what mode we enter the non-secure world */ 46 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 47 el_status &= ID_AA64PFR0_ELX_MASK; 48 49 mode = (el_status) ? MODE_EL2 : MODE_EL1; 50 51 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 52 return spsr; 53 } 54 55 static void bl31_tz380_setup(void) 56 { 57 unsigned int val; 58 59 val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10); 60 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 61 return; 62 63 tzc380_init(IMX_TZASC_BASE); 64 /* 65 * Need to substact offset 0x40000000 from CPU address when 66 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW 67 */ 68 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 69 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 70 } 71 72 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 73 u_register_t arg2, u_register_t arg3) 74 { 75 int i; 76 /* enable CSU NS access permission */ 77 for (i = 0; i < 64; i++) { 78 mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); 79 } 80 81 /* config CAAM JRaMID set MID to Cortex A */ 82 mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); 83 mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); 84 mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); 85 86 #if DEBUG_CONSOLE 87 static console_uart_t console; 88 89 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 90 IMX_CONSOLE_BAUDRATE, &console); 91 #endif 92 /* 93 * tell BL3-1 where the non-secure software image is located 94 * and the entry state information. 95 */ 96 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 97 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 98 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 99 100 bl31_tz380_setup(); 101 } 102 103 void bl31_plat_arch_setup(void) 104 { 105 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 106 MT_MEMORY | MT_RW | MT_SECURE); 107 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 108 MT_MEMORY | MT_RO | MT_SECURE); 109 110 mmap_add(imx_mmap); 111 112 #if USE_COHERENT_MEM 113 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 114 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 115 MT_DEVICE | MT_RW | MT_SECURE); 116 #endif 117 /* setup xlat table */ 118 init_xlat_tables(); 119 /* enable the MMU */ 120 enable_mmu_el3(0); 121 } 122 123 void bl31_platform_setup(void) 124 { 125 generic_delay_timer_init(); 126 127 /* init the GICv3 cpu and distributor interface */ 128 plat_gic_driver_init(); 129 plat_gic_init(); 130 131 /* gpc init */ 132 imx_gpc_init(); 133 } 134 135 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 136 { 137 if (type == NON_SECURE) 138 return &bl33_image_ep_info; 139 if (type == SECURE) 140 return &bl32_image_ep_info; 141 142 return NULL; 143 } 144 145 unsigned int plat_get_syscnt_freq2(void) 146 { 147 return COUNTER_FREQUENCY; 148 } 149 150 void bl31_plat_runtime_setup(void) 151 { 152 return; 153 } 154