dts: stm32: add RNG node in stm32mp251 SoC device tree file

Add the RNG node in the stm32mp251 SoC device tree file and default
enable it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.s

dts: stm32: add RNG node in stm32mp251 SoC device tree file

Add the RNG node in the stm32mp251 SoC device tree file and default
enable it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: update clock and power management

Better handle clock and reset resources by implementing
enable_rng_clock()/disable_rng_clock(). Do not implement a PM callback
if OP-TEE runs wi

drivers: stm32_rng: update clock and power management

Better handle clock and reset resources by implementing
enable_rng_clock()/disable_rng_clock(). Do not implement a PM callback
if OP-TEE runs with a software RNG. Finally, implement shared resource
management only for stm32mp15x platforms as it is not used on other
platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: default enable CFG_DRIVERS_FIREWALL

Default enable the CFG_DRIVERS_FIREWALL switch that is used to enable
the support of the firewall framework.

Signed-off-by: Gatien Chevallie

plat-stm32mp2: conf: default enable CFG_DRIVERS_FIREWALL

Default enable the CFG_DRIVERS_FIREWALL switch that is used to enable
the support of the firewall framework.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: restrain access on non secure peripherals for OP-TEE

Implement a driver specific firewall bus probe that will
only probe secure peripherals and implement firewall exceptions fo

drivers: stm32_rifsc: restrain access on non secure peripherals for OP-TEE

Implement a driver specific firewall bus probe that will
only probe secure peripherals and implement firewall exceptions for
which no firewall operations will be done when CFG_INSECURE is set.
This allows, for example, to share a console with the non-secure world
for development purposes.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: update RIFSC as a firewall controller

Use the new firewall API to populate the firewall bus and register
the RIFSC as a firewall provider.

While there, update device tree RIF

drivers: stm32_rifsc: update RIFSC as a firewall controller

Use the new firewall API to populate the firewall bus and register
the RIFSC as a firewall provider.

While there, update device tree RIF macros and sort them in the correct
files. Register bit-field macros should be present in the driver while
device tree macros should be present in device tree bindings files.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: declare RIFSC as an access-controller on stm32mp2 platforms

RIFSC is a firewall controller. Add the access-controllers property to
all RIFSC sub-nodes. Also add the "simple-bus" compatib

dts: stm32: declare RIFSC as an access-controller on stm32mp2 platforms

RIFSC is a firewall controller. Add the access-controllers property to
all RIFSC sub-nodes. Also add the "simple-bus" compatible for backward
compatibility and "#access-controllers-cells" to the RIFSC node.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: remove firewall_dt_probe_bus()

Remove firewall_dt_probe_bus() from the firewall framework as it seems
unlikely that we can have a consensual implementation of this feature.

Signe

drivers: firewall: remove firewall_dt_probe_bus()

Remove firewall_dt_probe_bus() from the firewall framework as it seems
unlikely that we can have a consensual implementation of this feature.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add RISAF support for the stm32mp257f-ev1 platform

Enable RISAF2/5 instances for this board that embeds PCIE ports and
some storage peripherals. Define a memory mapping and the RIF
confi

dts: stm32: add RISAF support for the stm32mp257f-ev1 platform

Enable RISAF2/5 instances for this board that embeds PCIE ports and
some storage peripherals. Define a memory mapping and the RIF
configuration of each memory region. Reorganize includes at board level
to avoid some build issues.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: default enable RISAF on stm32mp2 platforms

Default enable RISAF on stm32mp2 platforms to apply the device tree
RIF configuration on enabled RISAF instances.

Signed-off-by: Gatien Che

plat-stm32mp2: default enable RISAF on stm32mp2 platforms

Default enable RISAF on stm32mp2 platforms to apply the device tree
RIF configuration on enabled RISAF instances.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: add stm32_risaf driver

Add the stm32_risaf driver to handle all RISAFs instances on a SoC.
Through RISAF registers, a trusted domain application, or the application
to whom the co

drivers: firewall: add stm32_risaf driver

Add the stm32_risaf driver to handle all RISAFs instances on a SoC.
Through RISAF registers, a trusted domain application, or the application
to whom the configuration has been delegated, assigns memory regions to
one or more security domains (secure, privilege, compartment).
RISAF4 includes the DDR memory cipher engine (DDRMCE) feature.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add RISAF nodes in the stm32mp251 SoC DT file

Add the RISAF1/2/4/5 nodes in the stm32mp251 SoC DT file. Default enable
RISAF4 that protects the DDR and the RISAF1 that protects the backu

dts: stm32: add RISAF nodes in the stm32mp251 SoC DT file

Add the RISAF1/2/4/5 nodes in the stm32mp251 SoC DT file. Default enable
RISAF4 that protects the DDR and the RISAF1 that protects the backup
RAM (BKPSRAM). Other RISAF instances should be enabled at board level.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: add RISAF4 base address in platform config helper

Add RISAF4 base address in platform configuration helper.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-

plat-stm32mp2: add RISAF4 base address in platform config helper

Add RISAF4 base address in platform configuration helper.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add stm32mp25 RISAF bindings

Add stm32mp25 specific RISAF device tree bindings. This file contains
device tree contains helpers and RISAFPROT macro that is used to
define the RIF config

dt-bindings: add stm32mp25 RISAF bindings

Add stm32mp25 specific RISAF device tree bindings. This file contains
device tree contains helpers and RISAFPROT macro that is used to
define the RIF configuration for a RISAF region.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32-core: set clock number to 0 if node is not found

If fdt_clk_stm32_parse_by_name() is called for a clock node that is not
present, the fdt_getprop() may return an error value for len. In t

clk: stm32-core: set clock number to 0 if node is not found

If fdt_clk_stm32_parse_by_name() is called for a clock node that is not
present, the fdt_getprop() may return an error value for len. In this
case, set *nb to 0 instead of returning an error code.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Gabriel FERNANDEZ <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: implement multi-gate management at core level

The majority of all peripherals have their bus and kernel clocks with
the same clock gating register bit. Therefore it is mandatory to handle
a cou

clk: implement multi-gate management at core level

The majority of all peripherals have their bus and kernel clocks with
the same clock gating register bit. Therefore it is mandatory to handle
a counter on the gates.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp1: add dsb in clock driver

Add memory barriers in RCC clock driver to ensure the system is in the
expected state when requests are proceeded by RCC. No pending register
operation before

clk: stm32mp1: add dsb in clock driver

Add memory barriers in RCC clock driver to ensure the system is in the
expected state when requests are proceeded by RCC. No pending register
operation before disabling the clocks and return to caller only when
clock is enabled, so before any accesses to the clocked devices.

As the registers are mapped as device memory (shareable, bufferable),
the order of operation is guaranteed only at outer shareable limit
and not on each device, for example when they are not on the same bus.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32_gpio: add GPIO banks RIF configurations for stm32mp257f-ev1

Add initial RIF GPIO configuration for stm32mp257f-ev1 board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

dts: stm32_gpio: add GPIO banks RIF configurations for stm32mp257f-ev1

Add initial RIF GPIO configuration for stm32mp257f-ev1 board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add console support on USART2 for stm32mp257f-ev1

Populate USART2 node and enable console support on USART2 on
stm32mp257f-ev1 board.

Signed-off-by: Gatien Chevallier <gatien.chevallier

dts: stm32: add console support on USART2 for stm32mp257f-ev1

Populate USART2 node and enable console support on USART2 on
stm32mp257f-ev1 board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: save/restore consumed GPIOs in PM sequence

Save and restore during PM suspend/resume sequences the state of the
consumed GPIOs.

Consumers are expected to get their GPIOs using

drivers: stm32_gpio: save/restore consumed GPIOs in PM sequence

Save and restore during PM suspend/resume sequences the state of the
consumed GPIOs.

Consumers are expected to get their GPIOs using the DT resources hence
register a PM handle when the GPIO is requested (stm32_gpio_get_dt()) so
that the dependency order established during drivers initialization is
satisfied during PM suspend and resume sequences. PM handle is
unregistered when consumer releases the GPIO which requires the handles
to be referenced in a list so that we can find it back.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: pm: add unregister_pm_cb()

Add unregister_pm_cb() API function and its helper variants to
allow unregistering a PM callback entry. This can be needed for
example in the GPIO framework where gp

core: pm: add unregister_pm_cb()

Add unregister_pm_cb() API function and its helper variants to
allow unregistering a PM callback entry. This can be needed for
example in the GPIO framework where gpio_put() can release a GPIO
that a driver no more consumed. In case a PM callback was previously
registered for such a GPIO, consumer driver needs mean to unregister
it.

This change implies that the PM callbacks list is protected from
concurrent accesses hence add a lock for that purpose.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: stm32_gpio: add stm32mp25x support

Add support for stm32mp25x platforms by adding RIF support to the driver.
GPIO banks are RIF-aware peripherals, meaning that they are responsible
for sett

drivers: stm32_gpio: add stm32mp25x support

Add support for stm32mp25x platforms by adding RIF support to the driver.
GPIO banks are RIF-aware peripherals, meaning that they are responsible
for setting their own RIF configuration.

While there, remove the use of set_bank_gpio_non_secure() as it is of no
use since a pin not configured as secured in the device tree will already
result being non-secure.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rif: tag unused parameters as __unused

When CFG_STM32_RIF is not set, inclusion of this header file causes
warnings because of function parameters not being tagged as unused.
Tag them

drivers: stm32_rif: tag unused parameters as __unused

When CFG_STM32_RIF is not set, inclusion of this header file causes
warnings because of function parameters not being tagged as unused.
Tag them properly.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Fixes: 1506f47af917 ("drivers: firewall: add stm32_rif driver for common RIF features")
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: Remove thread_exit_user_mode()

Currently, the user mode abort and some system calls return to kernel
mode by thread_exit_user_mode(). Although this function creates a
shorter path to re

core: riscv: Remove thread_exit_user_mode()

Currently, the user mode abort and some system calls return to kernel
mode by thread_exit_user_mode(). Although this function creates a
shorter path to return to kernel mode, it leads to some problems because
the function does not update the core local flags. Especially when
CFG_CORE_DEBUG_CHECK_STACKS=y, some checks will fail due to wrong type
of stack recorded in the core local flags.

Fix it by removing thread_exit_user_mode(). So that the core local flags
can be correctly updated in the common trap handler.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>

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core: riscv: Use sp as base register of load instructions

Use sp as base register of load instructions can reduce code size if RVC
extension is enabled to generate 16-bit instructions. The following

core: riscv: Use sp as base register of load instructions

Use sp as base register of load instructions can reduce code size if RVC
extension is enabled to generate 16-bit instructions. The following code
shows the difference after applying this commit.

Before:
f10009da: 0d053d83 ld s11,208(a0)
f10009de: 0c853d03 ld s10,200(a0)
f10009e2: 0c053c83 ld s9,192(a0)
f10009e6: 0b853c03 ld s8,184(a0)
f10009ea: 0b053b83 ld s7,176(a0)
f10009ee: 0a853b03 ld s6,168(a0)
f10009f2: 0a053a83 ld s5,160(a0)
f10009f6: 09853a03 ld s4,152(a0)
f10009fa: 09053983 ld s3,144(a0)
f10009fe: 08853903 ld s2,136(a0)

After:
f10009a6: 6dce ld s11,208(sp)
f10009a8: 6d2e ld s10,200(sp)
f10009aa: 6c8e ld s9,192(sp)
f10009ac: 7c6a ld s8,184(sp)
f10009ae: 7bca ld s7,176(sp)
f10009b0: 7b2a ld s6,168(sp)
f10009b2: 7a8a ld s5,160(sp)
f10009b4: 6a6a ld s4,152(sp)
f10009b6: 69ca ld s3,144(sp)
f10009b8: 692a ld s2,136(sp)

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>

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core: riscv: Fix misconfiguration of XSCRATCH when XRET to kernel mode

When the program wants to XRET to kernel mode, the value of XSCRATCH
must be cleared to zero.

Signed-off-by: Alvin Chang <alvi

core: riscv: Fix misconfiguration of XSCRATCH when XRET to kernel mode

When the program wants to XRET to kernel mode, the value of XSCRATCH
must be cleared to zero.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>

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