1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/clock/stm32mp13-clksrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/gpio/stm32mp_gpio.h> 12#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 13#include "stm32mp135.dtsi" 14#include "stm32mp13xf.dtsi" 15#include "stm32mp13-pinctrl.dtsi" 16 17/ { 18 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 19 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 20 21 aliases { 22 serial0 = &uart4; 23 serial1 = &usart1; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 memory@c0000000 { 31 device_type = "memory"; 32 reg = <0xc0000000 0x20000000>; 33 }; 34 35 reserved-memory { 36 #address-cells = <1>; 37 #size-cells = <1>; 38 ranges; 39 40 optee_framebuffer: optee-framebuffer@dd000000 { 41 /* Secure framebuffer memory */ 42 reg = <0xdd000000 0x1000000>; 43 no-map; 44 }; 45 }; 46 47 vin: vin { 48 compatible = "regulator-fixed"; 49 regulator-name = "vin"; 50 regulator-min-microvolt = <5000000>; 51 regulator-max-microvolt = <5000000>; 52 regulator-always-on; 53 }; 54 55 v3v3_ao: v3v3_ao { 56 compatible = "regulator-fixed"; 57 regulator-name = "v3v3_ao"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 regulator-always-on; 61 }; 62}; 63 64&bsec { 65 board_id: board_id@f0 { 66 reg = <0xf0 0x4>; 67 st,non-secure-otp; 68 }; 69}; 70 71&gpiob { 72 st,protreg = <TZPROT(9)>; 73}; 74 75&gpiod { 76 st,protreg = <TZPROT(7)>; 77}; 78 79&gpioe { 80 st,protreg = <TZPROT(15)>; 81}; 82 83&i2c4 { 84 pinctrl-names = "default"; 85 pinctrl-0 = <&i2c4_pins_a>; 86 i2c-scl-rising-time-ns = <185>; 87 i2c-scl-falling-time-ns = <20>; 88 clock-frequency = <400000>; 89 status = "okay"; 90 91 pmic: stpmic@33 { 92 compatible = "st,stpmic1"; 93 reg = <0x33>; 94 status = "okay"; 95 st,wakeup-pin-number = <1>; 96 st,notif-it-id = <0>; 97 98 regulators { 99 compatible = "st,stpmic1-regulators"; 100 buck1-supply = <&vin>; 101 buck2-supply = <&vin>; 102 buck3-supply = <&vin>; 103 buck4-supply = <&vin>; 104 ldo1-supply = <&vin>; 105 ldo4-supply = <&vin>; 106 ldo5-supply = <&vin>; 107 ldo6-supply = <&vin>; 108 vref_ddr-supply = <&vin>; 109 pwr_sw1-supply = <&bst_out>; 110 pwr_sw2-supply = <&v3v3_ao>; 111 112 vddcpu: buck1 { 113 regulator-name = "vddcpu"; 114 regulator-min-microvolt = <1250000>; 115 regulator-max-microvolt = <1350000>; 116 regulator-always-on; 117 regulator-over-current-protection; 118 119 lp-stop { 120 regulator-suspend-microvolt = <1250000>; 121 }; 122 lplv-stop { 123 regulator-suspend-microvolt = <900000>; 124 }; 125 lplv-stop2 { 126 regulator-off-in-suspend; 127 }; 128 standby-ddr-sr { 129 regulator-off-in-suspend; 130 }; 131 standby-ddr-off { 132 regulator-off-in-suspend; 133 }; 134 }; 135 136 vdd_ddr: buck2 { 137 regulator-name = "vdd_ddr"; 138 regulator-min-microvolt = <1350000>; 139 regulator-max-microvolt = <1350000>; 140 regulator-always-on; 141 regulator-over-current-protection; 142 143 standby-ddr-off { 144 regulator-off-in-suspend; 145 }; 146 }; 147 148 vdd: buck3 { 149 regulator-name = "vdd"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 regulator-always-on; 153 st,mask-reset; 154 regulator-over-current-protection; 155 }; 156 157 vddcore: buck4 { 158 regulator-name = "vddcore"; 159 regulator-min-microvolt = <1250000>; 160 regulator-max-microvolt = <1250000>; 161 regulator-always-on; 162 regulator-over-current-protection; 163 164 lplv-stop { 165 regulator-suspend-microvolt = <900000>; 166 }; 167 lplv-stop2 { 168 regulator-suspend-microvolt = <900000>; 169 }; 170 standby-ddr-sr { 171 regulator-off-in-suspend; 172 }; 173 standby-ddr-off { 174 regulator-off-in-suspend; 175 }; 176 }; 177 178 vdd_adc: ldo1 { 179 regulator-name = "vdd_adc"; 180 regulator-min-microvolt = <3300000>; 181 regulator-max-microvolt = <3300000>; 182 183 standby-ddr-sr { 184 regulator-off-in-suspend; 185 }; 186 standby-ddr-off { 187 regulator-off-in-suspend; 188 }; 189 }; 190 191 unused1: ldo2 { 192 regulator-name = "ldo2"; 193 }; 194 195 unused2: ldo3 { 196 regulator-name = "ldo3"; 197 }; 198 199 vdd_usb: ldo4 { 200 regulator-name = "vdd_usb"; 201 regulator-min-microvolt = <3300000>; 202 regulator-max-microvolt = <3300000>; 203 204 standby-ddr-sr { 205 regulator-off-in-suspend; 206 }; 207 standby-ddr-off { 208 regulator-off-in-suspend; 209 }; 210 }; 211 212 vdd_sd: ldo5 { 213 regulator-name = "vdd_sd"; 214 regulator-min-microvolt = <3300000>; 215 regulator-max-microvolt = <3300000>; 216 regulator-boot-on; 217 218 standby-ddr-sr { 219 regulator-off-in-suspend; 220 }; 221 standby-ddr-off { 222 regulator-off-in-suspend; 223 }; 224 }; 225 226 v1v8_periph: ldo6 { 227 regulator-name = "v1v8_periph"; 228 regulator-min-microvolt = <1800000>; 229 regulator-max-microvolt = <1800000>; 230 231 standby-ddr-sr { 232 regulator-off-in-suspend; 233 }; 234 standby-ddr-off { 235 regulator-off-in-suspend; 236 }; 237 }; 238 239 vref_ddr: vref_ddr { 240 regulator-name = "vref_ddr"; 241 regulator-always-on; 242 243 standby-ddr-sr { 244 regulator-off-in-suspend; 245 }; 246 standby-ddr-off { 247 regulator-off-in-suspend; 248 }; 249 }; 250 251 bst_out: boost { 252 regulator-name = "bst_out"; 253 }; 254 255 v3v3_sw: pwr_sw2 { 256 regulator-name = "v3v3_sw"; 257 regulator-active-discharge = <1>; 258 regulator-min-microvolt = <3300000>; 259 regulator-max-microvolt = <3300000>; 260 }; 261 }; 262 }; 263}; 264 265&iwdg1 { 266 timeout-sec = <32>; 267 status = "okay"; 268}; 269 270&oem_enc_key { 271 st,non-secure-otp-provisioning; 272}; 273 274&pwr_regulators { 275 vdd-supply = <&vdd>; 276 vdd_3v3_usbfs-supply = <&vdd_usb>; 277}; 278 279&rcc { 280 compatible = "st,stm32mp13-rcc", "syscon"; 281 282 st,clksrc = < 283 CLK_MPU_PLL1P 284 CLK_AXI_PLL2P 285 CLK_MLAHBS_PLL3 286 CLK_RTC_LSE 287 CLK_MCO1_HSE 288 CLK_MCO2_DISABLED 289 CLK_CKPER_HSE 290 CLK_ETH1_PLL4P 291 CLK_ETH2_PLL4P 292 CLK_SDMMC1_PLL4P 293 CLK_SDMMC2_PLL4P 294 CLK_STGEN_HSE 295 CLK_USBPHY_HSE 296 CLK_I2C4_HSI 297 CLK_I2C5_HSI 298 CLK_USBO_USBPHY 299 CLK_ADC2_CKPER 300 CLK_I2C12_HSI 301 CLK_UART1_HSI 302 CLK_UART2_HSI 303 CLK_UART35_HSI 304 CLK_UART4_HSI 305 CLK_UART6_HSI 306 CLK_UART78_HSI 307 CLK_SAES_AXI 308 CLK_DCMIPP_PLL2Q 309 CLK_LPTIM3_PCLK3 310 CLK_RNG1_PLL4R 311 >; 312 313 st,clkdiv = < 314 DIV(DIV_MPU, 1) 315 DIV(DIV_AXI, 0) 316 DIV(DIV_MLAHB, 0) 317 DIV(DIV_APB1, 1) 318 DIV(DIV_APB2, 1) 319 DIV(DIV_APB3, 1) 320 DIV(DIV_APB4, 1) 321 DIV(DIV_APB5, 2) 322 DIV(DIV_APB6, 1) 323 DIV(DIV_RTC, 0) 324 DIV(DIV_MCO1, 0) 325 DIV(DIV_MCO2, 0) 326 >; 327 328 st,pll_vco { 329 pll1_vco_2000Mhz: pll1-vco-2000Mhz { 330 src = <CLK_PLL12_HSE>; 331 divmn = <1 82>; 332 frac = <0xAAA>; 333 }; 334 335 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 336 src = <CLK_PLL12_HSE>; 337 divmn = <2 80>; 338 frac = <0x800>; 339 }; 340 341 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 342 src = <CLK_PLL12_HSE>; 343 divmn = <2 65>; 344 frac = <0x1400>; 345 }; 346 347 pll3_vco_417Mhz: pll3-vco-417Mhz { 348 src = <CLK_PLL3_HSE>; 349 divmn = <1 33>; 350 frac = <0x1a04>; 351 }; 352 353 pll4_vco_600Mhz: pll4-vco-600Mhz { 354 src = <CLK_PLL4_HSE>; 355 divmn = <1 49>; 356 }; 357 }; 358 359 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 360 pll1: st,pll@0 { 361 compatible = "st,stm32mp1-pll"; 362 reg = <0>; 363 364 st,pll = <&pll1_cfg1>; 365 366 pll1_cfg1: pll1_cfg1 { 367 st,pll_vco = <&pll1_vco_1300Mhz>; 368 st,pll_div_pqr = <0 1 1>; 369 }; 370 371 pll1_cfg2: pll1_cfg2 { 372 st,pll_vco = <&pll1_vco_2000Mhz>; 373 st,pll_div_pqr = <0 1 1>; 374 }; 375 }; 376 377 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 378 pll2: st,pll@1 { 379 compatible = "st,stm32mp1-pll"; 380 reg = <1>; 381 382 st,pll = <&pll2_cfg1>; 383 384 pll2_cfg1: pll2_cfg1 { 385 st,pll_vco = <&pll2_vco_1066Mhz>; 386 st,pll_div_pqr = <1 1 0>; 387 }; 388 }; 389 390 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 391 pll3: st,pll@2 { 392 compatible = "st,stm32mp1-pll"; 393 reg = <2>; 394 395 st,pll = <&pll3_cfg1>; 396 397 pll3_cfg1: pll3_cfg1 { 398 st,pll_vco = <&pll3_vco_417Mhz>; 399 st,pll_div_pqr = <1 16 36>; 400 }; 401 }; 402 403 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ 404 pll4: st,pll@3 { 405 compatible = "st,stm32mp1-pll"; 406 reg = <3>; 407 st,pll = <&pll4_cfg1>; 408 409 pll4_cfg1: pll4_cfg1 { 410 st,pll_vco = <&pll4_vco_600Mhz>; 411 st,pll_div_pqr = <11 59 11>; 412 }; 413 }; 414 415 st,clk_opp { 416 /* CK_MPU clock config for MP13 */ 417 st,ck_mpu { 418 419 cfg_1 { 420 hz = <650000000>; 421 st,clksrc = <CLK_MPU_PLL1P>; 422 st,pll = <&pll1_cfg1>; 423 }; 424 425 cfg_2 { 426 hz = <1000000000>; 427 st,clksrc = <CLK_MPU_PLL1P>; 428 st,pll = <&pll1_cfg2>; 429 }; 430 }; 431 }; 432}; 433 434&rng { 435 status = "okay"; 436 clock-error-detect; 437}; 438 439&rtc { 440 status = "okay"; 441}; 442 443&saes { 444 status = "okay"; 445}; 446 447&sdmmc1_io { 448 vddsd1-supply = <&vdd>; 449}; 450 451&sdmmc2_io { 452 vddsd2-supply = <&vdd>; 453}; 454 455&uart4 { 456 pinctrl-names = "default"; 457 pinctrl-0 = <&uart4_pins_a>; 458 status = "okay"; 459}; 460 461&usart1 { 462 pinctrl-names = "default"; 463 pinctrl-0 = <&usart1_pins_a>; 464 uart-has-rtscts; 465 status = "disabled"; 466}; 467