core: user_mode_ctx: fix unused warning when disable log

When compiled with clang 22.0 and set CFG_TEE_CORE_LOG_LEVEL to 0,
the variable n becomes unused and the compiler generates a warning,
which

core: user_mode_ctx: fix unused warning when disable log

When compiled with clang 22.0 and set CFG_TEE_CORE_LOG_LEVEL to 0,
the variable n becomes unused and the compiler generates a warning,
which can fail the build process if -Werror is enabled.

core/kernel/user_mode_ctx.c:14:9: warning: variable 'n' set but not used [-Wunused-but-set-variable]
14 | size_t n = 0;
| ^
1 warning generated.

Signed-off-by: Leo Chen <shf.chen@mediatek.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-corstone1000: Add Cortex-A320 support

Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the

plat-corstone1000: Add Cortex-A320 support

Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the make command line.

The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
When arm64-platform-cpuarch is set to cortex-a320, switch to
-march=armv9.2-a.

The new Corstone-1000 variant with Cortex-A320 replaces the original
GIC-400 (v2) interrupt controller with a GIC-600, which is
architecturally compliant with GICv3. Since OP-TEE already provides
a generic GICv3 driver, only minimal platform changes are needed
to expose the updated register map and initialize the GICv3 interface.

**Changes introduced**

* When `cortex-a320` is selected:
* Force `CFG_ARM_GICV3=y`.
* Map the Redistributor region (`GICR_BASE`).
* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
the Cortex-A35 + GIC-400 variant continues to build unchanged.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Add support for TI mailbox driver

New devices like the AM62L use a mailbox to communicate with the
security firmware. Add mailbox driver here to support the mailbox
hardware.

Sign

plat-k3: drivers: Add support for TI mailbox driver

New devices like the AM62L use a mailbox to communicate with the
security firmware. Add mailbox driver here to support the mailbox
hardware.

Signed-off-by: Aniket Sarkar <a-sarkar1@ti.com>
Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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plat-k3: drivers: Refactor sec_proxy driver

Since the underneath transport layer may or may not always be sec_proxy
it doesn't make sense to keep following the k3_sec_proxy_* convention
for the TI_S

plat-k3: drivers: Refactor sec_proxy driver

Since the underneath transport layer may or may not always be sec_proxy
it doesn't make sense to keep following the k3_sec_proxy_* convention
for the TI_SCI message transports.
Rename them to something more generic like ti_sci_transport_*.

Signed-off-by: Aniket Sarkar <a-sarkar1@ti.com>
Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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plat-k3: drivers: Set SEC_PROXY_MAX_MSG_SIZE to 56

Currently, SEC_PROXY_MAX_MSG_SIZE is set to 60. However, its max size
(including the secure header) is 56. Therefore correct this macro.

Signed-of

plat-k3: drivers: Set SEC_PROXY_MAX_MSG_SIZE to 56

Currently, SEC_PROXY_MAX_MSG_SIZE is set to 60. However, its max size
(including the secure header) is 56. Therefore correct this macro.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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plat-k3: drivers: Open TRNG firewall for TIFS on all k3 devs

On k3 devices, TRNG is firewalled to be accessed only by OPTEE.

TIFS needs this for the encryption and decryption services to support
di

plat-k3: drivers: Open TRNG firewall for TIFS on all k3 devs

On k3 devices, TRNG is firewalled to be accessed only by OPTEE.

TIFS needs this for the encryption and decryption services to support
different low power modes. So, open firewall to TIFS as well.

There is no concurrent usage of TRNG, as TIFS uses TRNG only at suspend
when OPTEE is down and resume, when firewalls are restored but OPTEE is
not up yet.

As this is a firewall that required to be shared along with TIFS on all
devices, making this a common change and open on all devs.

Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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core: ffa: add missing field in memory access descriptor

FF-A v1.2 introduced a 16 byte implementation-defined field in the
endpoint memory access descriptor. Update all handling of struct
ffa_mem_a

core: ffa: add missing field in memory access descriptor

FF-A v1.2 introduced a 16 byte implementation-defined field in the
endpoint memory access descriptor. Update all handling of struct
ffa_mem_access to for correct access regardless of FF-A version.

With this patch, OP-TEE will use the updated memory access descriptor,
but ignore the impdef field.

Suggested-by: Olivier Deprez <olivier.deprez@arm.com>
Fixes: bef959c837fe ("core: arm: ffa: switch to FF-A version 1.2")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: ele: update struct get_info_rsp{} fields

update struct get_info_rsp{} fields

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.or

drivers: ele: update struct get_info_rsp{} fields

update struct get_info_rsp{} fields

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: ele: enable getting HUK/RNG from ELE on i.MX943

Enable support for getting HUK/RNG from ELE on i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <r

drivers: ele: enable getting HUK/RNG from ELE on i.MX943

Enable support for getting HUK/RNG from ELE on i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: enable MU and ELE driver on i.MX943

Enable MU and ELE driver on i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>

core: imx: enable MU and ELE driver on i.MX943

Enable MU and ELE driver on i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add MU_BASE and MU_SIZE for i.MX943

Add MU_BASE and MU_SIZE for i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>

core: imx: add MU_BASE and MU_SIZE for i.MX943

Add MU_BASE and MU_SIZE for i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: imx_mu: add support for i.MX943

Enable MU driver support for i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked

drivers: imx_mu: add support for i.MX943

Enable MU driver support for i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add support for i.MX943 EVK

Add support for i.MX943 EVK

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens W

core: imx: add support for i.MX943 EVK

Add support for i.MX943 EVK

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add i.MX943 SoC ID

Add i.MX943 SoC ID

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wik

core: imx: add i.MX943 SoC ID

Add i.MX943 SoC ID

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add i.MX943 registers

Add i.MX943 registers

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <je

core: imx: add i.MX943 registers

Add i.MX943 registers

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: spinlock.S: use REGOFF for stack push and pop

In __cpu_spin_lock(), using STR/LDR and RISCV_XLEN_BYTES, it seems
that it wants to adopt the RV64 or RV32 environment, but missing the
shi

core: riscv: spinlock.S: use REGOFF for stack push and pop

In __cpu_spin_lock(), using STR/LDR and RISCV_XLEN_BYTES, it seems
that it wants to adopt the RV64 or RV32 environment, but missing the
shift byte for differ environmnt. therefore remove the const value and
using REGOFF() macro to fit the RV32/RV64 environment.

Signed-off-by: Randolph Lin <randolph@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: arm64: increase thread stack size with KASAN/check-stacks

Increase STACK_THREAD_SIZE from 10 KiB to 12 KiB when
CFG_CORE_SANITIZE_KADDRESS is enabled.

With the previous size, some regression

core: arm64: increase thread stack size with KASAN/check-stacks

Increase STACK_THREAD_SIZE from 10 KiB to 12 KiB when
CFG_CORE_SANITIZE_KADDRESS is enabled.

With the previous size, some regression tests (for example
regression_1006 "Test Basic OS features") may fail due to stack
canary corruption caused by the additional stack usage from
instrumentation.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp2: conf: default enable CFG_STM32_I2C for stm32mp2 family

Default enable STM32 I2C driver on STM32MP2 platforms.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by

plat-stm32mp2: conf: default enable CFG_STM32_I2C for stm32mp2 family

Default enable STM32 I2C driver on STM32MP2 platforms.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add i2c1 to i2c3 nodes in stm32mp211.dtsi

The STM32MP23x has a total of 3 instances of I2C.
Add all of them in stm32mp231.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.c

dts: stm32: add i2c1 to i2c3 nodes in stm32mp211.dtsi

The STM32MP23x has a total of 3 instances of I2C.
Add all of them in stm32mp231.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add i2c1, i2c2, i2c7 and i2c8 nodes in stm32mp231.dtsi

The STM32MP23x has a total of 4 instances of I2C.
Add all of them in stm32mp231.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourg

dts: stm32: add i2c1, i2c2, i2c7 and i2c8 nodes in stm32mp231.dtsi

The STM32MP23x has a total of 4 instances of I2C.
Add all of them in stm32mp231.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add i2c1 to i2c8 nodes in stm32mp251.dtsi

The STM32MP25x has a total of 8 instances of I2C hence add all
of them in stm32mp251.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss

dts: stm32: add i2c1 to i2c8 nodes in stm32mp251.dtsi

The STM32MP25x has a total of 8 instances of I2C hence add all
of them in stm32mp251.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_i2c: fallback to interrupt access when no bottom half

Change stm32_i2c driver to allow I2C transfers in interrupt context
before bottom half thread is initialized and after it's relea

drivers: stm32_i2c: fallback to interrupt access when no bottom half

Change stm32_i2c driver to allow I2C transfers in interrupt context
before bottom half thread is initialized and after it's released.

This can be needed by PMIC driver to handle PMCI interrupt events
when bottom half thread is not supported by normal wold.
In that case, PMIC driver would need to register its interrupt to
stm32_i2c driver.

Thread accesses to the bus still start by locking the I2C bus mutex.
Before using the bus, the sequence now masks the PMIC interrupt and
polls (with timeout) on I2C bus access atomic lock. This lock
may be held by an I2C transfer currently executing in an interrupt
context. A 100ms timeout is short enough to also allow
debug console traces in the interrupt sequence. Masking the interrupt
before polling the lock ensures no new pending interrupt will interrupt
us (and execute a I2C transfer) while the thread context accesses the
I2C bus.

Interrupt accesses to the bus atomically set/clear the I2C bus access
lock while executing the interrupt sequence.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_i2c: add support of stm32mp2 family

Add compatible st,stm32mp25-i2c to support stm32mp2x SoCs.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carri

drivers: stm32_i2c: add support of stm32mp2 family

Add compatible st,stm32mp25-i2c to support stm32mp2x SoCs.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: fs_htree: fix incorrect data type in create_and_sync

Fixes an incorrect data type used in the create_and_sync function.
When this function calls tee_fs_htree_sync_to_storage, it may invoke
tee

core: fs_htree: fix incorrect data type in create_and_sync

Fixes an incorrect data type used in the create_and_sync function.
When this function calls tee_fs_htree_sync_to_storage, it may invoke
tee_fs_htree_close to free the input hash tree in error cases.
Therefore, the input type should be struct tee_fs_htree **ht_arg
to handle these scenarios correctly.

Link: https://github.com/OP-TEE/optee_os/issues/7512
Fixes: 5a9d570a8d7f ("core: fs_htree: re-init hash tree when both tag and counter are zero")

Signed-off-by: Ox Yeh <ox.yeh@mediatek.com>
Reviewed-by: Menson Chen <menson.chen@mediatek.com>
Reviewed-by: Rayan Hu <rayan.hu@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-ti: Fix initialisation order

Since commit 358cdcd2b079 ("core: arm32: initialize secure monitor
late") TI platforms have been broken due to only initialising the
HUK in `init_sec_mon` after the

plat-ti: Fix initialisation order

Since commit 358cdcd2b079 ("core: arm32: initialize secure monitor
late") TI platforms have been broken due to only initialising the
HUK in `init_sec_mon` after the SSK has been derived/generated from
it in the `tee_fs_init_key_manager` service init.

Move initialisation of HUK into an `early_init` registration to
restore the correct order of operations.

Secure monitor initialisation cannot be moved into the
`early_init()` as the secure monitor stack is not yet initialised.

Link: https://github.com/OP-TEE/optee_os/issues/7587

Signed-off-by: Alistair Higgins <Alistair_Higgins@trimble.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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