drivers: imx_ocotp: write support i.MX6ULL

Reuse the same write function as the other i.MX6 SoCs since
the OCOTP IP is the same. i.MX6ULL just has fewer fuse banks
than i.MX6UL.

Reviewed-by: Sahil

drivers: imx_ocotp: write support i.MX6ULL

Reuse the same write function as the other i.MX6 SoCs since
the OCOTP IP is the same. i.MX6ULL just has fewer fuse banks
than i.MX6UL.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[m.felsch@pengutronix.de: adapt function name after renaming]
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: write support i.MX6Q/D/S/DL/UL

Reuse the same write functions as for i.MX8M SoC since they seem to use
the same OCOTP IP core according to the reference manual.

While on it, ren

drivers: imx_ocotp: write support i.MX6Q/D/S/DL/UL

Reuse the same write functions as for i.MX8M SoC since they seem to use
the same OCOTP IP core according to the reference manual.

While on it, rename the fuse write function and the set_timing helper
since it's no longer imx8m specific.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
[m.felsch@pengutronix.de: add function renaming]
[m.felsch@pengutronix.de: adapt commit message]
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: add support to burn fuses

This adds the support to burn fuses on i.MX8M SoCs. This approach assume
that the IPG clock is running at 66.67 MHz which is AHB/2 (AHB max.
clock = 133

drivers: imx_ocotp: add support to burn fuses

This adds the support to burn fuses on i.MX8M SoCs. This approach assume
that the IPG clock is running at 66.67 MHz which is AHB/2 (AHB max.
clock = 133 MHz). Due to lack of HW I added only the i.MX8M support.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix ocotp_ctrl_wait_for for i.MX6

Make use of the udelay() function and the newly added
OCOTP_OP_BUSY_TIMEOUT_US to align platforms which don't support
architected timers, like i

drivers: imx_ocotp: fix ocotp_ctrl_wait_for for i.MX6

Make use of the udelay() function and the newly added
OCOTP_OP_BUSY_TIMEOUT_US to align platforms which don't support
architected timers, like i.MX6Q with the ones that support architected
timers.

udelay() can be used since we have added the plat_get_freq() support for
all i.MX SoCs which don't support architected timers previously.

While on it drop the dsb() since the memory is mapped as non-cacheable
device-memory. So there is no need for a data barrier. Keep the isb() to
not send use-less register loads.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: make use of hw timers during ocotp_ctrl_wait_for

Use the ARM architected timer instead of assuming that the CPU is
running at 500MHz and the poll takes around ~20us.

Reviewed-by

drivers: imx_ocotp: make use of hw timers during ocotp_ctrl_wait_for

Use the ARM architected timer instead of assuming that the CPU is
running at 500MHz and the poll takes around ~20us.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix imx_ocotp_read g_base_addr and g_ocotp check

Check the g_base_addr and g_ocotp before do the first access.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by

drivers: imx_ocotp: fix imx_ocotp_read g_base_addr and g_ocotp check

Check the g_base_addr and g_ocotp before do the first access.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix clearing the error bit

According the reference manuals the ERROR bit should be cleared by
writing a '1' to the OCOTP_CTRL_CLR register and not by writing to the
OCOTP_CTRL di

drivers: imx_ocotp: fix clearing the error bit

According the reference manuals the ERROR bit should be cleared by
writing a '1' to the OCOTP_CTRL_CLR register and not by writing to the
OCOTP_CTRL direct.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix error/busy defines for i.MX8MP

The i.MX8MP has an OCOTP_CTRL_ADDR field which is 8-bit wide compared to
all other current supported i.MX SoCs. Due to the larger ADDR field al

drivers: imx_ocotp: fix error/busy defines for i.MX8MP

The i.MX8MP has an OCOTP_CTRL_ADDR field which is 8-bit wide compared to
all other current supported i.MX SoCs. Due to the larger ADDR field all
bits shifted by 1 bit.

Also make some minor style fixes while on it by replacing the mix of
tabs and spaces with tabs-only.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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core: plat-imx: i.MX6 CA9 has no generic timer

The Cortex-A9 inside of the i.MX6Q/D/QP/DL/S/SL/SLL SoCs has no generic
timer support, but all variants should boot with 792Mhz out of the boot
rom. Se

core: plat-imx: i.MX6 CA9 has no generic timer

The Cortex-A9 inside of the i.MX6Q/D/QP/DL/S/SL/SLL SoCs has no generic
timer support, but all variants should boot with 792Mhz out of the boot
rom. Set the Generic Timer configuration variable to n and implement the
required plat_get_freq() call to support the udelay() calls.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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driver: crypto: hisilicon: fix qm timeout variable type

The type of the timeout variable is fixed to prevent overflow

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wi

driver: crypto: hisilicon: fix qm timeout variable type

The type of the timeout variable is fixed to prevent overflow

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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driver: crypto: hisilicon: fix CKEY_LEN macro value

Fix CKEY_LEN macro value for hisilicon SEC driver

Fixes: 562874beda99 ("drivers: crypto: hisilicon: Add cipher algorithm")
Signed-off-by: Zexi Yu

driver: crypto: hisilicon: fix CKEY_LEN macro value

Fix CKEY_LEN macro value for hisilicon SEC driver

Fixes: 562874beda99 ("drivers: crypto: hisilicon: Add cipher algorithm")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: fix SM2 ECC encrypt and decrypt

Adds checks that the destination buffer has room for the result in
ecc_sm2_decrypt() and ecc_sm2_encrypt(). Note that these two functions
not reachab

drivers: crypto: fix SM2 ECC encrypt and decrypt

Adds checks that the destination buffer has room for the result in
ecc_sm2_decrypt() and ecc_sm2_encrypt(). Note that these two functions
not reachable upstream since none of the crypto drivers registers ECC
encrypt or decrypt drivers. So fix this before it becomes a problem.

Fixes: f4f85ac774af ("drivers: crypto: add SM2 ECC encrypt and decrypt")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Zexi Yu <yuzexi@hisilicon.com>

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plat-corstone1000: swap GIC-600 for GIC-700 for Cortex-A320 variant

Switch the Cortex-A320 variant to use GIC-700 instead of GIC-600.
GIC-700 implements the Arm GICv4.1 architecture, so enable the
C

plat-corstone1000: swap GIC-600 for GIC-700 for Cortex-A320 variant

Switch the Cortex-A320 variant to use GIC-700 instead of GIC-600.
GIC-700 implements the Arm GICv4.1 architecture, so enable the
CFG_ARM_GICV4 compiler definition for the Corstone-1000 platform.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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gic: refactor implementation of GICv3 to add GICv4 support

Refactor the definitions of GICv3 to facilitate adding support for
GICv4 by:
* Add macro for registers frame sizes based on GIC versions.
*

gic: refactor implementation of GICv3 to add GICv4 support

Refactor the definitions of GICv3 to facilitate adding support for
GICv4 by:
* Add macro for registers frame sizes based on GIC versions.
* Add macro for number of frame count for GICR based on GICv3 or GICv4.
* Add single GICR region size definition (GIC_REDIST_REG_SIZE)
based on GIC version in platform independent include/drivers/gic.h
along with existing GIC_CPU_REG_SIZE and GIC_DIST_REG_SIZE
definitions.
* Amend usage of the now platform independent GIC_REDIST_REG_SIZE
as it no longer includes a multiplication by the number of core on
the target platform.
* Sort in ascending order the listing of GICR register definitions and
add comments to denote each definitions sections.
* Add definitions for each GICR frames.
* Ensure that all relevant code sections that compile for CFG_ARM_GICV3
also compile for CFG_ARM_GICV4.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-corstone1000: specify GIC version in plat specific conf.mk

The Generic Interrupt Controller architecture version is not core
specific. Therefore move the CFG_ARM_GICV3 definition from
cortex-a3

plat-corstone1000: specify GIC version in plat specific conf.mk

The Generic Interrupt Controller architecture version is not core
specific. Therefore move the CFG_ARM_GICV3 definition from
cortex-a320.mk file to the Corstone-1000 specific file.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-marvell: register DDR for dynamic shared memory

Register non-secure DDR memory region for Armada 7K/8K and Armada 3700
platforms to enable dynamic shared memory support.

Without this, U-Boot's

plat-marvell: register DDR for dynamic shared memory

Register non-secure DDR memory region for Armada 7K/8K and Armada 3700
platforms to enable dynamic shared memory support.

Without this, U-Boot's OP-TEE driver fails to probe with:
"OP-TEE capabilities mismatch"

The U-Boot OPTEE driver requires OPTEE_SMC_SEC_CAP_DYNAMIC_SHM capability,
which is advertised when core_mmu_nsec_ddr_is_defined() returns true.

The registered region starts after the reserved shared memory
(CFG_SHMEM_START + CFG_SHMEM_SIZE) and extends to the end of DRAM.
CFG_DDR_SIZE defaults to 2GB but can be overridden at build time for
boards with different memory configurations.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Set firewall for DTHEv2 RNG

Set firewall to protect DTHEv2 RNG from non-secure world.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: T Pratham <t-pratham@ti.com>
Review

plat-k3: drivers: Set firewall for DTHEv2 RNG

Set firewall to protect DTHEv2 RNG from non-secure world.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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plat-k3: drivers: Remove code to get firewall configs

The ti_crypto_init_rng_fwl() function gets firewall configurations
before setting new ones. This is pointless, since we are not using
the config

plat-k3: drivers: Remove code to get firewall configs

The ti_crypto_init_rng_fwl() function gets firewall configurations
before setting new ones. This is pointless, since we are not using
the configurations that we get anywhere. Therefore remove these blocks
of code.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Reviewed-by: T Pratham <t-pratham@ti.com>

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plat-k3: drivers: Refactor SA2UL RNG firewall setup

sa2ul_init() contains code to set firewall for SA2UL RNG. However,
almost the same code can also be used to firewall DTHEv2 RNG. Therefore
refacto

plat-k3: drivers: Refactor SA2UL RNG firewall setup

sa2ul_init() contains code to set firewall for SA2UL RNG. However,
almost the same code can also be used to firewall DTHEv2 RNG. Therefore
refactor this code into a separate function in the ti_sci driver.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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core: mm: add extra xlat table when core ASan is enabled

Enabling CFG_CORE_SANITIZE_KADDRESS increases MMU translation
table usage in multiple ways. In addition to ASan shadow regions,
the overall s

core: mm: add extra xlat table when core ASan is enabled

Enabling CFG_CORE_SANITIZE_KADDRESS increases MMU translation
table usage in multiple ways. In addition to ASan shadow regions,
the overall size of the core image grows, including code, data,
and stack mappings. This often leads to additional page table splits
and higher xlat table consumption.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@st.com>

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plat-stm32mp1: default enable CFG_STM32_DEBUG_ACCESS_PTA

In order to handle request on the debug configuration, default enable
CFG_STM32_DEBUG_ACCESS_PTA to embed the debug access PTA.

Signed-off-b

plat-stm32mp1: default enable CFG_STM32_DEBUG_ACCESS_PTA

In order to handle request on the debug configuration, default enable
CFG_STM32_DEBUG_ACCESS_PTA to embed the debug access PTA.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@st.com>

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pta: stm32mp: add debug access PTA

Add the debug access PTA that is responsible of validating whether
a given debug profile is configured or not. This basically means that
the debug configuration sh

pta: stm32mp: add debug access PTA

Add the debug access PTA that is responsible of validating whether
a given debug profile is configured or not. This basically means that
the debug configuration should allow (at least!) access to the debug
peripherals requiring the debug profile being checked.

For now, as it is specific to BSEC, only embed the PTA if the BSEC support
is embedded as well.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@st.com>

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core: arm: fix feat_pauth_implemented not consider QARMA3 algorithm

The feat_pauth_implemented function does not take
ID_AA64ISAR2_EL1.{GPA3,APA3} into account, which indicates the
processor support

core: arm: fix feat_pauth_implemented not consider QARMA3 algorithm

The feat_pauth_implemented function does not take
ID_AA64ISAR2_EL1.{GPA3,APA3} into account, which indicates the
processor supports the QARMA3.

According to Arm's documentation, ID_AA64ISAR1_EL1.{GPI,GPA,API,APA}
should be zero if ID_AA64ISAR2_EL1.{GPA3,APA3} are non-zero.
Therefore, OP-TEE wrongly reports that PAC is not available to TA
when the CPU uses QARMA3 algorithm.

This commit also introduces the register read function and related
definitions for ID_AA64ISAR2_EL1.

Signed-off-by: Leo Chen <shf.chen@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: dt: add overlay support to dt_enable_secure_status

Add support to write the "secure-status" property to overlays in
addition to the inline DTB changes if the user enabled the overlay
support.

core: dt: add overlay support to dt_enable_secure_status

Add support to write the "secure-status" property to overlays in
addition to the inline DTB changes if the user enabled the overlay
support.

Most BL33 firmwares don't reuse the DTB provided to OP-TEE. Therefore
add an overlay for the requested node to not lose the changes done by
OP-TEE. The overlay can be used by the BL33 firmware to apply the
changes.

Reviewed-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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core: dt: add add_dt_node_overlay_fragment helper

Add a helper to add overlays to an external-dt for a caller provided
node. The overlay can be used by the caller to overwrite node
properties. The s

core: dt: add add_dt_node_overlay_fragment helper

Add a helper to add overlays to an external-dt for a caller provided
node. The overlay can be used by the caller to overwrite node
properties. The subsequent BL33 can use the overlay to apply the changes
to the BL33 DTB and kernel DTB.

Reviewed-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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