1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2022, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/pinctrl.h> 12 #include <drivers/stm32_bsec.h> 13 #include <kernel/panic.h> 14 #include <stdint.h> 15 #include <tee_api_types.h> 16 #include <types_ext.h> 17 18 /* Backup registers and RAM utils */ 19 vaddr_t stm32mp_bkpreg(unsigned int idx); 20 21 /* Platform util for the RCC drivers */ 22 vaddr_t stm32_rcc_base(void); 23 24 /* Platform util for the GIC */ 25 vaddr_t get_gicd_base(void); 26 27 /* Platform util for PMIC support */ 28 bool stm32mp_with_pmic(void); 29 30 /* Power management service */ 31 #ifdef CFG_PSCI_ARM32 32 void stm32mp_register_online_cpu(void); 33 #else 34 static inline void stm32mp_register_online_cpu(void) 35 { 36 } 37 #endif 38 39 /* 40 * Generic spinlock function that bypass spinlock if MMU is disabled or 41 * lock is NULL. 42 */ 43 uint32_t may_spin_lock(unsigned int *lock); 44 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 45 46 /* Helper from platform RCC clock driver */ 47 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 48 49 #ifdef CFG_STM32MP1_SHARED_RESOURCES 50 /* Return true if @clock_id is shared by secure and non-secure worlds */ 51 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 52 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 53 static inline bool stm32mp_nsec_can_access_clock(unsigned long clock_id 54 __unused) 55 { 56 return true; 57 } 58 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 59 60 extern const struct clk_ops stm32mp1_clk_ops; 61 62 #if defined(CFG_STPMIC1) 63 /* Return true if non-secure world can manipulate regulator @pmic_regu_name */ 64 bool stm32mp_nsec_can_access_pmic_regu(const char *pmic_regu_name); 65 #else 66 static inline bool stm32mp_nsec_can_access_pmic_regu(const char *name __unused) 67 { 68 return false; 69 } 70 #endif 71 72 #ifdef CFG_STM32MP1_SHARED_RESOURCES 73 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 74 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 75 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 76 static inline bool stm32mp_nsec_can_access_reset(unsigned int reset_id __unused) 77 { 78 return true; 79 } 80 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 81 82 /* Return rstctrl instance related to RCC reset controller DT binding ID */ 83 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 84 85 /* 86 * Structure and API function for BSEC driver to get some platform data. 87 * 88 * @base: BSEC interface registers physical base address 89 * @upper_start: Base ID for the BSEC upper words in the platform 90 * @max_id: Max value for BSEC word ID for the platform 91 */ 92 struct stm32_bsec_static_cfg { 93 paddr_t base; 94 unsigned int upper_start; 95 unsigned int max_id; 96 }; 97 98 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 99 100 /* 101 * Shared reference counter: increments by 2 on secure increment 102 * request, decrements by 2 on secure decrement request. Bit #0 103 * is set to 1 on non-secure increment request and reset to 0 on 104 * non-secure decrement request. These counters initialize to 105 * either 0, 1 or 2 upon their expect default state. 106 * Counters saturate to UINT_MAX / 2. 107 */ 108 #define SHREFCNT_NONSECURE_FLAG 0x1ul 109 #define SHREFCNT_SECURE_STEP 0x2ul 110 #define SHREFCNT_MAX (UINT_MAX / 2) 111 112 /* Return 1 if refcnt increments from 0, else return 0 */ 113 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 114 { 115 int rc = !*refcnt; 116 117 if (secure) { 118 if (*refcnt < SHREFCNT_MAX) { 119 *refcnt += SHREFCNT_SECURE_STEP; 120 assert(*refcnt < SHREFCNT_MAX); 121 } 122 } else { 123 *refcnt |= SHREFCNT_NONSECURE_FLAG; 124 } 125 126 return rc; 127 } 128 129 /* Return 1 if refcnt decrements to 0, else return 0 */ 130 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 131 { 132 int rc = 0; 133 134 if (secure) { 135 if (*refcnt < SHREFCNT_MAX) { 136 if (*refcnt < SHREFCNT_SECURE_STEP) 137 panic(); 138 139 *refcnt -= SHREFCNT_SECURE_STEP; 140 rc = !*refcnt; 141 } 142 } else { 143 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 144 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 145 } 146 147 return rc; 148 } 149 150 static inline int incr_refcnt(unsigned int *refcnt) 151 { 152 return incr_shrefcnt(refcnt, true); 153 } 154 155 static inline int decr_refcnt(unsigned int *refcnt) 156 { 157 return decr_shrefcnt(refcnt, true); 158 } 159 160 /* 161 * Shared peripherals and resources registration 162 * 163 * Resources listed in enum stm32mp_shres assigned at run-time to the 164 * non-secure world, to the secure world or shared by both worlds. 165 * In the later case, there must exist a secure service in OP-TEE 166 * for the non-secure world to access the resource. 167 * 168 * Resources may be a peripheral, a bus, a clock or a memory. 169 * 170 * Shared resources driver API functions allows drivers to register the 171 * resource as secure, non-secure or shared and to get the resource 172 * assignation state. 173 */ 174 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 175 176 enum stm32mp_shres { 177 STM32MP1_SHRES_GPIOZ_0 = 0, 178 STM32MP1_SHRES_GPIOZ_1, 179 STM32MP1_SHRES_GPIOZ_2, 180 STM32MP1_SHRES_GPIOZ_3, 181 STM32MP1_SHRES_GPIOZ_4, 182 STM32MP1_SHRES_GPIOZ_5, 183 STM32MP1_SHRES_GPIOZ_6, 184 STM32MP1_SHRES_GPIOZ_7, 185 STM32MP1_SHRES_IWDG1, 186 STM32MP1_SHRES_USART1, 187 STM32MP1_SHRES_SPI6, 188 STM32MP1_SHRES_I2C4, 189 STM32MP1_SHRES_RNG1, 190 STM32MP1_SHRES_HASH1, 191 STM32MP1_SHRES_CRYP1, 192 STM32MP1_SHRES_I2C6, 193 STM32MP1_SHRES_RTC, 194 STM32MP1_SHRES_MCU, 195 STM32MP1_SHRES_PLL3, 196 STM32MP1_SHRES_MDMA, 197 STM32MP1_SHRES_SRAM1, 198 STM32MP1_SHRES_SRAM2, 199 STM32MP1_SHRES_SRAM3, 200 STM32MP1_SHRES_SRAM4, 201 202 STM32MP1_SHRES_COUNT 203 }; 204 205 bool stm32mp_allow_probe_shared_device(const void *fdt, int node); 206 207 #ifdef CFG_STM32MP1_SHARED_RESOURCES 208 /* Register resource @id as a secure peripheral */ 209 void stm32mp_register_secure_periph(enum stm32mp_shres id); 210 211 /* Register resource @id as a non-secure peripheral */ 212 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 213 214 /* 215 * Register resource identified by @base as a secure peripheral 216 * @base: IOMEM physical base address of the resource 217 */ 218 void stm32mp_register_secure_periph_iomem(vaddr_t base); 219 220 /* 221 * Register resource identified by @base as a non-secure peripheral 222 * @base: IOMEM physical base address of the resource 223 */ 224 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 225 226 /* 227 * Register GPIO resource as a secure peripheral 228 * @bank: Bank of the target GPIO 229 * @pin: Bit position of the target GPIO in the bank 230 */ 231 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 232 233 /* 234 * Register GPIO resource as a non-secure peripheral 235 * @bank: Bank of the target GPIO 236 * @pin: Bit position of the target GPIO in the bank 237 */ 238 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 239 240 /* 241 * Register pin resource of a pin control state as a secure peripheral 242 * @bank: Bank of the target GPIO 243 * @pin: Bit position of the target GPIO in the bank 244 */ 245 void stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl); 246 247 /* 248 * Register pin resource of a pin control state as a non-secure peripheral 249 * @bank: Bank of the target GPIO 250 * @pin: Bit position of the target GPIO in the bank 251 */ 252 void stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl); 253 254 /* Return true if and only if resource @id is registered as secure */ 255 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 256 257 /* Return true if and only if GPIO bank @bank is registered as secure */ 258 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 259 260 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 261 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 262 263 /* Register parent clocks of @clock (ID used in clock DT bindings) as secure */ 264 void stm32mp_register_clock_parents_secure(unsigned long clock_id); 265 266 /* Register number of pins in the GPIOZ bank */ 267 void stm32mp_register_gpioz_pin_count(size_t count); 268 269 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 270 271 static inline void stm32mp_register_secure_periph(enum stm32mp_shres id 272 __unused) 273 { 274 } 275 276 static inline void stm32mp_register_non_secure_periph(enum stm32mp_shres id 277 __unused) 278 { 279 } 280 281 static inline void stm32mp_register_secure_periph_iomem(vaddr_t base __unused) 282 { 283 } 284 285 static inline void stm32mp_register_non_secure_periph_iomem(vaddr_t base 286 __unused) 287 { 288 } 289 290 static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, 291 unsigned int pin __unused) 292 { 293 } 294 295 static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, 296 unsigned int pin __unused) 297 { 298 } 299 300 static inline void 301 stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl __unused) 302 { 303 } 304 305 static inline void 306 stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl __unused) 307 { 308 } 309 310 static inline bool stm32mp_periph_is_secure(enum stm32mp_shres id __unused) 311 { 312 return true; 313 } 314 315 static inline bool stm32mp_gpio_bank_is_secure(unsigned int bank __unused) 316 { 317 return true; 318 } 319 320 static inline bool stm32mp_gpio_bank_is_non_secure(unsigned int bank __unused) 321 { 322 return false; 323 } 324 325 static inline void stm32mp_register_clock_parents_secure(unsigned long clock_id 326 __unused) 327 { 328 } 329 330 static inline void stm32mp_register_gpioz_pin_count(size_t count __unused) 331 { 332 } 333 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 334 #endif /*__STM32_UTIL_H__*/ 335