1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9#include <dt-bindings/firewall/stm32mp15-etzpc.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 clock-frequency = <650000000>; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 arm-pmu { 28 compatible = "arm,cortex-a7-pmu"; 29 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-affinity = <&cpu0>; 31 interrupt-parent = <&intc>; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0"; 36 method = "smc"; 37 }; 38 39 intc: interrupt-controller@a0021000 { 40 compatible = "arm,cortex-a7-gic"; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 reg = <0xa0021000 0x1000>, 44 <0xa0022000 0x2000>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&intc>; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 timers2: timer@40000000 { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 compatible = "st,stm32-timers"; 130 reg = <0x40000000 0x400>; 131 clocks = <&rcc TIM2_K>; 132 clock-names = "int"; 133 dmas = <&dmamux1 18 0x400 0x1>, 134 <&dmamux1 19 0x400 0x1>, 135 <&dmamux1 20 0x400 0x1>, 136 <&dmamux1 21 0x400 0x1>, 137 <&dmamux1 22 0x400 0x1>; 138 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 139 status = "disabled"; 140 141 pwm { 142 compatible = "st,stm32-pwm"; 143 #pwm-cells = <3>; 144 status = "disabled"; 145 }; 146 147 timer@1 { 148 compatible = "st,stm32h7-timer-trigger"; 149 reg = <1>; 150 status = "disabled"; 151 }; 152 153 counter { 154 compatible = "st,stm32-timer-counter"; 155 status = "disabled"; 156 }; 157 }; 158 159 timers3: timer@40001000 { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 compatible = "st,stm32-timers"; 163 reg = <0x40001000 0x400>; 164 clocks = <&rcc TIM3_K>; 165 clock-names = "int"; 166 dmas = <&dmamux1 23 0x400 0x1>, 167 <&dmamux1 24 0x400 0x1>, 168 <&dmamux1 25 0x400 0x1>, 169 <&dmamux1 26 0x400 0x1>, 170 <&dmamux1 27 0x400 0x1>, 171 <&dmamux1 28 0x400 0x1>; 172 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 173 status = "disabled"; 174 175 pwm { 176 compatible = "st,stm32-pwm"; 177 #pwm-cells = <3>; 178 status = "disabled"; 179 }; 180 181 timer@2 { 182 compatible = "st,stm32h7-timer-trigger"; 183 reg = <2>; 184 status = "disabled"; 185 }; 186 187 counter { 188 compatible = "st,stm32-timer-counter"; 189 status = "disabled"; 190 }; 191 }; 192 193 timers4: timer@40002000 { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 compatible = "st,stm32-timers"; 197 reg = <0x40002000 0x400>; 198 clocks = <&rcc TIM4_K>; 199 clock-names = "int"; 200 dmas = <&dmamux1 29 0x400 0x1>, 201 <&dmamux1 30 0x400 0x1>, 202 <&dmamux1 31 0x400 0x1>, 203 <&dmamux1 32 0x400 0x1>; 204 dma-names = "ch1", "ch2", "ch3", "ch4"; 205 status = "disabled"; 206 207 pwm { 208 compatible = "st,stm32-pwm"; 209 #pwm-cells = <3>; 210 status = "disabled"; 211 }; 212 213 timer@3 { 214 compatible = "st,stm32h7-timer-trigger"; 215 reg = <3>; 216 status = "disabled"; 217 }; 218 219 counter { 220 compatible = "st,stm32-timer-counter"; 221 status = "disabled"; 222 }; 223 }; 224 225 timers5: timer@40003000 { 226 #address-cells = <1>; 227 #size-cells = <0>; 228 compatible = "st,stm32-timers"; 229 reg = <0x40003000 0x400>; 230 clocks = <&rcc TIM5_K>; 231 clock-names = "int"; 232 dmas = <&dmamux1 55 0x400 0x1>, 233 <&dmamux1 56 0x400 0x1>, 234 <&dmamux1 57 0x400 0x1>, 235 <&dmamux1 58 0x400 0x1>, 236 <&dmamux1 59 0x400 0x1>, 237 <&dmamux1 60 0x400 0x1>; 238 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 239 status = "disabled"; 240 241 pwm { 242 compatible = "st,stm32-pwm"; 243 #pwm-cells = <3>; 244 status = "disabled"; 245 }; 246 247 timer@4 { 248 compatible = "st,stm32h7-timer-trigger"; 249 reg = <4>; 250 status = "disabled"; 251 }; 252 253 counter { 254 compatible = "st,stm32-timer-counter"; 255 status = "disabled"; 256 }; 257 }; 258 259 timers6: timer@40004000 { 260 #address-cells = <1>; 261 #size-cells = <0>; 262 compatible = "st,stm32-timers"; 263 reg = <0x40004000 0x400>; 264 clocks = <&rcc TIM6_K>; 265 clock-names = "int"; 266 dmas = <&dmamux1 69 0x400 0x1>; 267 dma-names = "up"; 268 status = "disabled"; 269 270 timer@5 { 271 compatible = "st,stm32h7-timer-trigger"; 272 reg = <5>; 273 status = "disabled"; 274 }; 275 }; 276 277 timers7: timer@40005000 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 compatible = "st,stm32-timers"; 281 reg = <0x40005000 0x400>; 282 clocks = <&rcc TIM7_K>; 283 clock-names = "int"; 284 dmas = <&dmamux1 70 0x400 0x1>; 285 dma-names = "up"; 286 status = "disabled"; 287 288 timer@6 { 289 compatible = "st,stm32h7-timer-trigger"; 290 reg = <6>; 291 status = "disabled"; 292 }; 293 }; 294 295 timers12: timer@40006000 { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 compatible = "st,stm32-timers"; 299 reg = <0x40006000 0x400>; 300 clocks = <&rcc TIM12_K>; 301 clock-names = "int"; 302 status = "disabled"; 303 304 pwm { 305 compatible = "st,stm32-pwm"; 306 #pwm-cells = <3>; 307 status = "disabled"; 308 }; 309 310 timer@11 { 311 compatible = "st,stm32h7-timer-trigger"; 312 reg = <11>; 313 status = "disabled"; 314 }; 315 }; 316 317 timers13: timer@40007000 { 318 #address-cells = <1>; 319 #size-cells = <0>; 320 compatible = "st,stm32-timers"; 321 reg = <0x40007000 0x400>; 322 clocks = <&rcc TIM13_K>; 323 clock-names = "int"; 324 status = "disabled"; 325 326 pwm { 327 compatible = "st,stm32-pwm"; 328 #pwm-cells = <3>; 329 status = "disabled"; 330 }; 331 332 timer@12 { 333 compatible = "st,stm32h7-timer-trigger"; 334 reg = <12>; 335 status = "disabled"; 336 }; 337 }; 338 339 timers14: timer@40008000 { 340 #address-cells = <1>; 341 #size-cells = <0>; 342 compatible = "st,stm32-timers"; 343 reg = <0x40008000 0x400>; 344 clocks = <&rcc TIM14_K>; 345 clock-names = "int"; 346 status = "disabled"; 347 348 pwm { 349 compatible = "st,stm32-pwm"; 350 #pwm-cells = <3>; 351 status = "disabled"; 352 }; 353 354 timer@13 { 355 compatible = "st,stm32h7-timer-trigger"; 356 reg = <13>; 357 status = "disabled"; 358 }; 359 }; 360 361 lptimer1: timer@40009000 { 362 #address-cells = <1>; 363 #size-cells = <0>; 364 compatible = "st,stm32-lptimer"; 365 reg = <0x40009000 0x400>; 366 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&rcc LPTIM1_K>; 368 clock-names = "mux"; 369 wakeup-source; 370 status = "disabled"; 371 372 pwm { 373 compatible = "st,stm32-pwm-lp"; 374 #pwm-cells = <3>; 375 status = "disabled"; 376 }; 377 378 trigger@0 { 379 compatible = "st,stm32-lptimer-trigger"; 380 reg = <0>; 381 status = "disabled"; 382 }; 383 384 counter { 385 compatible = "st,stm32-lptimer-counter"; 386 status = "disabled"; 387 }; 388 }; 389 390 spi2: spi@4000b000 { 391 #address-cells = <1>; 392 #size-cells = <0>; 393 compatible = "st,stm32h7-spi"; 394 reg = <0x4000b000 0x400>; 395 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&rcc SPI2_K>; 397 resets = <&rcc SPI2_R>; 398 dmas = <&dmamux1 39 0x400 0x05>, 399 <&dmamux1 40 0x400 0x05>; 400 dma-names = "rx", "tx"; 401 status = "disabled"; 402 }; 403 404 i2s2: audio-controller@4000b000 { 405 compatible = "st,stm32h7-i2s"; 406 #sound-dai-cells = <0>; 407 reg = <0x4000b000 0x400>; 408 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 409 dmas = <&dmamux1 39 0x400 0x01>, 410 <&dmamux1 40 0x400 0x01>; 411 dma-names = "rx", "tx"; 412 status = "disabled"; 413 }; 414 415 spi3: spi@4000c000 { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 compatible = "st,stm32h7-spi"; 419 reg = <0x4000c000 0x400>; 420 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&rcc SPI3_K>; 422 resets = <&rcc SPI3_R>; 423 dmas = <&dmamux1 61 0x400 0x05>, 424 <&dmamux1 62 0x400 0x05>; 425 dma-names = "rx", "tx"; 426 status = "disabled"; 427 }; 428 429 i2s3: audio-controller@4000c000 { 430 compatible = "st,stm32h7-i2s"; 431 #sound-dai-cells = <0>; 432 reg = <0x4000c000 0x400>; 433 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 434 dmas = <&dmamux1 61 0x400 0x01>, 435 <&dmamux1 62 0x400 0x01>; 436 dma-names = "rx", "tx"; 437 status = "disabled"; 438 }; 439 440 spdifrx: audio-controller@4000d000 { 441 compatible = "st,stm32h7-spdifrx"; 442 #sound-dai-cells = <0>; 443 reg = <0x4000d000 0x400>; 444 clocks = <&rcc SPDIF_K>; 445 clock-names = "kclk"; 446 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 447 dmas = <&dmamux1 93 0x400 0x01>, 448 <&dmamux1 94 0x400 0x01>; 449 dma-names = "rx", "rx-ctrl"; 450 status = "disabled"; 451 }; 452 453 usart2: serial@4000e000 { 454 compatible = "st,stm32h7-uart"; 455 reg = <0x4000e000 0x400>; 456 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&rcc USART2_K>; 458 wakeup-source; 459 dmas = <&dmamux1 43 0x400 0x15>, 460 <&dmamux1 44 0x400 0x11>; 461 dma-names = "rx", "tx"; 462 status = "disabled"; 463 }; 464 465 usart3: serial@4000f000 { 466 compatible = "st,stm32h7-uart"; 467 reg = <0x4000f000 0x400>; 468 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&rcc USART3_K>; 470 wakeup-source; 471 dmas = <&dmamux1 45 0x400 0x15>, 472 <&dmamux1 46 0x400 0x11>; 473 dma-names = "rx", "tx"; 474 status = "disabled"; 475 }; 476 477 uart4: serial@40010000 { 478 compatible = "st,stm32h7-uart"; 479 reg = <0x40010000 0x400>; 480 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&rcc UART4_K>; 482 wakeup-source; 483 dmas = <&dmamux1 63 0x400 0x15>, 484 <&dmamux1 64 0x400 0x11>; 485 dma-names = "rx", "tx"; 486 status = "disabled"; 487 }; 488 489 uart5: serial@40011000 { 490 compatible = "st,stm32h7-uart"; 491 reg = <0x40011000 0x400>; 492 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&rcc UART5_K>; 494 wakeup-source; 495 dmas = <&dmamux1 65 0x400 0x15>, 496 <&dmamux1 66 0x400 0x11>; 497 dma-names = "rx", "tx"; 498 status = "disabled"; 499 }; 500 501 i2c1: i2c@40012000 { 502 compatible = "st,stm32mp15-i2c"; 503 reg = <0x40012000 0x400>; 504 interrupt-names = "event", "error"; 505 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&rcc I2C1_K>; 508 resets = <&rcc I2C1_R>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 st,syscfg-fmp = <&syscfg 0x4 0x1>; 512 wakeup-source; 513 i2c-analog-filter; 514 status = "disabled"; 515 }; 516 517 i2c2: i2c@40013000 { 518 compatible = "st,stm32mp15-i2c"; 519 reg = <0x40013000 0x400>; 520 interrupt-names = "event", "error"; 521 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&rcc I2C2_K>; 524 resets = <&rcc I2C2_R>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 st,syscfg-fmp = <&syscfg 0x4 0x2>; 528 wakeup-source; 529 i2c-analog-filter; 530 status = "disabled"; 531 }; 532 533 i2c3: i2c@40014000 { 534 compatible = "st,stm32mp15-i2c"; 535 reg = <0x40014000 0x400>; 536 interrupt-names = "event", "error"; 537 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&rcc I2C3_K>; 540 resets = <&rcc I2C3_R>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 st,syscfg-fmp = <&syscfg 0x4 0x4>; 544 wakeup-source; 545 i2c-analog-filter; 546 status = "disabled"; 547 }; 548 549 i2c5: i2c@40015000 { 550 compatible = "st,stm32mp15-i2c"; 551 reg = <0x40015000 0x400>; 552 interrupt-names = "event", "error"; 553 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&rcc I2C5_K>; 556 resets = <&rcc I2C5_R>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 st,syscfg-fmp = <&syscfg 0x4 0x10>; 560 wakeup-source; 561 i2c-analog-filter; 562 status = "disabled"; 563 }; 564 565 cec: cec@40016000 { 566 compatible = "st,stm32-cec"; 567 reg = <0x40016000 0x400>; 568 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&rcc CEC_K>, <&rcc CEC>; 570 clock-names = "cec", "hdmi-cec"; 571 status = "disabled"; 572 }; 573 574 dac: dac@40017000 { 575 compatible = "st,stm32h7-dac-core"; 576 reg = <0x40017000 0x400>; 577 clocks = <&rcc DAC12>; 578 clock-names = "pclk"; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 status = "disabled"; 582 583 dac1: dac@1 { 584 compatible = "st,stm32-dac"; 585 #io-channel-cells = <1>; 586 reg = <1>; 587 status = "disabled"; 588 }; 589 590 dac2: dac@2 { 591 compatible = "st,stm32-dac"; 592 #io-channel-cells = <1>; 593 reg = <2>; 594 status = "disabled"; 595 }; 596 }; 597 598 uart7: serial@40018000 { 599 compatible = "st,stm32h7-uart"; 600 reg = <0x40018000 0x400>; 601 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&rcc UART7_K>; 603 wakeup-source; 604 dmas = <&dmamux1 79 0x400 0x15>, 605 <&dmamux1 80 0x400 0x11>; 606 dma-names = "rx", "tx"; 607 status = "disabled"; 608 }; 609 610 uart8: serial@40019000 { 611 compatible = "st,stm32h7-uart"; 612 reg = <0x40019000 0x400>; 613 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&rcc UART8_K>; 615 wakeup-source; 616 dmas = <&dmamux1 81 0x400 0x15>, 617 <&dmamux1 82 0x400 0x11>; 618 dma-names = "rx", "tx"; 619 status = "disabled"; 620 }; 621 622 timers1: timer@44000000 { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 compatible = "st,stm32-timers"; 626 reg = <0x44000000 0x400>; 627 clocks = <&rcc TIM1_K>; 628 clock-names = "int"; 629 dmas = <&dmamux1 11 0x400 0x1>, 630 <&dmamux1 12 0x400 0x1>, 631 <&dmamux1 13 0x400 0x1>, 632 <&dmamux1 14 0x400 0x1>, 633 <&dmamux1 15 0x400 0x1>, 634 <&dmamux1 16 0x400 0x1>, 635 <&dmamux1 17 0x400 0x1>; 636 dma-names = "ch1", "ch2", "ch3", "ch4", 637 "up", "trig", "com"; 638 status = "disabled"; 639 640 pwm { 641 compatible = "st,stm32-pwm"; 642 #pwm-cells = <3>; 643 status = "disabled"; 644 }; 645 646 timer@0 { 647 compatible = "st,stm32h7-timer-trigger"; 648 reg = <0>; 649 status = "disabled"; 650 }; 651 652 counter { 653 compatible = "st,stm32-timer-counter"; 654 status = "disabled"; 655 }; 656 }; 657 658 timers8: timer@44001000 { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 compatible = "st,stm32-timers"; 662 reg = <0x44001000 0x400>; 663 clocks = <&rcc TIM8_K>; 664 clock-names = "int"; 665 dmas = <&dmamux1 47 0x400 0x1>, 666 <&dmamux1 48 0x400 0x1>, 667 <&dmamux1 49 0x400 0x1>, 668 <&dmamux1 50 0x400 0x1>, 669 <&dmamux1 51 0x400 0x1>, 670 <&dmamux1 52 0x400 0x1>, 671 <&dmamux1 53 0x400 0x1>; 672 dma-names = "ch1", "ch2", "ch3", "ch4", 673 "up", "trig", "com"; 674 status = "disabled"; 675 676 pwm { 677 compatible = "st,stm32-pwm"; 678 #pwm-cells = <3>; 679 status = "disabled"; 680 }; 681 682 timer@7 { 683 compatible = "st,stm32h7-timer-trigger"; 684 reg = <7>; 685 status = "disabled"; 686 }; 687 688 counter { 689 compatible = "st,stm32-timer-counter"; 690 status = "disabled"; 691 }; 692 }; 693 694 usart6: serial@44003000 { 695 compatible = "st,stm32h7-uart"; 696 reg = <0x44003000 0x400>; 697 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&rcc USART6_K>; 699 wakeup-source; 700 dmas = <&dmamux1 71 0x400 0x15>, 701 <&dmamux1 72 0x400 0x11>; 702 dma-names = "rx", "tx"; 703 status = "disabled"; 704 }; 705 706 spi1: spi@44004000 { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 compatible = "st,stm32h7-spi"; 710 reg = <0x44004000 0x400>; 711 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&rcc SPI1_K>; 713 resets = <&rcc SPI1_R>; 714 dmas = <&dmamux1 37 0x400 0x05>, 715 <&dmamux1 38 0x400 0x05>; 716 dma-names = "rx", "tx"; 717 status = "disabled"; 718 }; 719 720 i2s1: audio-controller@44004000 { 721 compatible = "st,stm32h7-i2s"; 722 #sound-dai-cells = <0>; 723 reg = <0x44004000 0x400>; 724 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 725 dmas = <&dmamux1 37 0x400 0x01>, 726 <&dmamux1 38 0x400 0x01>; 727 dma-names = "rx", "tx"; 728 status = "disabled"; 729 }; 730 731 spi4: spi@44005000 { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 compatible = "st,stm32h7-spi"; 735 reg = <0x44005000 0x400>; 736 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&rcc SPI4_K>; 738 resets = <&rcc SPI4_R>; 739 dmas = <&dmamux1 83 0x400 0x05>, 740 <&dmamux1 84 0x400 0x05>; 741 dma-names = "rx", "tx"; 742 status = "disabled"; 743 }; 744 745 timers15: timer@44006000 { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 compatible = "st,stm32-timers"; 749 reg = <0x44006000 0x400>; 750 clocks = <&rcc TIM15_K>; 751 clock-names = "int"; 752 dmas = <&dmamux1 105 0x400 0x1>, 753 <&dmamux1 106 0x400 0x1>, 754 <&dmamux1 107 0x400 0x1>, 755 <&dmamux1 108 0x400 0x1>; 756 dma-names = "ch1", "up", "trig", "com"; 757 status = "disabled"; 758 759 pwm { 760 compatible = "st,stm32-pwm"; 761 #pwm-cells = <3>; 762 status = "disabled"; 763 }; 764 765 timer@14 { 766 compatible = "st,stm32h7-timer-trigger"; 767 reg = <14>; 768 status = "disabled"; 769 }; 770 }; 771 772 timers16: timer@44007000 { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 compatible = "st,stm32-timers"; 776 reg = <0x44007000 0x400>; 777 clocks = <&rcc TIM16_K>; 778 clock-names = "int"; 779 dmas = <&dmamux1 109 0x400 0x1>, 780 <&dmamux1 110 0x400 0x1>; 781 dma-names = "ch1", "up"; 782 status = "disabled"; 783 784 pwm { 785 compatible = "st,stm32-pwm"; 786 #pwm-cells = <3>; 787 status = "disabled"; 788 }; 789 timer@15 { 790 compatible = "st,stm32h7-timer-trigger"; 791 reg = <15>; 792 status = "disabled"; 793 }; 794 }; 795 796 timers17: timer@44008000 { 797 #address-cells = <1>; 798 #size-cells = <0>; 799 compatible = "st,stm32-timers"; 800 reg = <0x44008000 0x400>; 801 clocks = <&rcc TIM17_K>; 802 clock-names = "int"; 803 dmas = <&dmamux1 111 0x400 0x1>, 804 <&dmamux1 112 0x400 0x1>; 805 dma-names = "ch1", "up"; 806 status = "disabled"; 807 808 pwm { 809 compatible = "st,stm32-pwm"; 810 #pwm-cells = <3>; 811 status = "disabled"; 812 }; 813 814 timer@16 { 815 compatible = "st,stm32h7-timer-trigger"; 816 reg = <16>; 817 status = "disabled"; 818 }; 819 }; 820 821 spi5: spi@44009000 { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 compatible = "st,stm32h7-spi"; 825 reg = <0x44009000 0x400>; 826 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&rcc SPI5_K>; 828 resets = <&rcc SPI5_R>; 829 dmas = <&dmamux1 85 0x400 0x05>, 830 <&dmamux1 86 0x400 0x05>; 831 dma-names = "rx", "tx"; 832 status = "disabled"; 833 }; 834 835 sai1: sai@4400a000 { 836 compatible = "st,stm32h7-sai"; 837 #address-cells = <1>; 838 #size-cells = <1>; 839 ranges = <0 0x4400a000 0x400>; 840 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 841 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 842 resets = <&rcc SAI1_R>; 843 status = "disabled"; 844 845 sai1a: audio-controller@4400a004 { 846 #sound-dai-cells = <0>; 847 848 compatible = "st,stm32-sai-sub-a"; 849 reg = <0x4 0x20>; 850 clocks = <&rcc SAI1_K>; 851 clock-names = "sai_ck"; 852 dmas = <&dmamux1 87 0x400 0x01>; 853 status = "disabled"; 854 }; 855 856 sai1b: audio-controller@4400a024 { 857 #sound-dai-cells = <0>; 858 compatible = "st,stm32-sai-sub-b"; 859 reg = <0x24 0x20>; 860 clocks = <&rcc SAI1_K>; 861 clock-names = "sai_ck"; 862 dmas = <&dmamux1 88 0x400 0x01>; 863 status = "disabled"; 864 }; 865 }; 866 867 sai2: sai@4400b000 { 868 compatible = "st,stm32h7-sai"; 869 #address-cells = <1>; 870 #size-cells = <1>; 871 ranges = <0 0x4400b000 0x400>; 872 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 873 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 874 resets = <&rcc SAI2_R>; 875 status = "disabled"; 876 877 sai2a: audio-controller@4400b004 { 878 #sound-dai-cells = <0>; 879 compatible = "st,stm32-sai-sub-a"; 880 reg = <0x4 0x20>; 881 clocks = <&rcc SAI2_K>; 882 clock-names = "sai_ck"; 883 dmas = <&dmamux1 89 0x400 0x01>; 884 status = "disabled"; 885 }; 886 887 sai2b: audio-controller@4400b024 { 888 #sound-dai-cells = <0>; 889 compatible = "st,stm32-sai-sub-b"; 890 reg = <0x24 0x20>; 891 clocks = <&rcc SAI2_K>; 892 clock-names = "sai_ck"; 893 dmas = <&dmamux1 90 0x400 0x01>; 894 status = "disabled"; 895 }; 896 }; 897 898 sai3: sai@4400c000 { 899 compatible = "st,stm32h7-sai"; 900 #address-cells = <1>; 901 #size-cells = <1>; 902 ranges = <0 0x4400c000 0x400>; 903 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 904 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 905 resets = <&rcc SAI3_R>; 906 status = "disabled"; 907 908 sai3a: audio-controller@4400c004 { 909 #sound-dai-cells = <0>; 910 compatible = "st,stm32-sai-sub-a"; 911 reg = <0x04 0x20>; 912 clocks = <&rcc SAI3_K>; 913 clock-names = "sai_ck"; 914 dmas = <&dmamux1 113 0x400 0x01>; 915 status = "disabled"; 916 }; 917 918 sai3b: audio-controller@4400c024 { 919 #sound-dai-cells = <0>; 920 compatible = "st,stm32-sai-sub-b"; 921 reg = <0x24 0x20>; 922 clocks = <&rcc SAI3_K>; 923 clock-names = "sai_ck"; 924 dmas = <&dmamux1 114 0x400 0x01>; 925 status = "disabled"; 926 }; 927 }; 928 929 dfsdm: dfsdm@4400d000 { 930 compatible = "st,stm32mp1-dfsdm"; 931 reg = <0x4400d000 0x800>; 932 clocks = <&rcc DFSDM_K>; 933 clock-names = "dfsdm"; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 status = "disabled"; 937 938 dfsdm0: filter@0 { 939 compatible = "st,stm32-dfsdm-adc"; 940 #io-channel-cells = <1>; 941 reg = <0>; 942 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 943 dmas = <&dmamux1 101 0x400 0x01>; 944 dma-names = "rx"; 945 status = "disabled"; 946 }; 947 948 dfsdm1: filter@1 { 949 compatible = "st,stm32-dfsdm-adc"; 950 #io-channel-cells = <1>; 951 reg = <1>; 952 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 953 dmas = <&dmamux1 102 0x400 0x01>; 954 dma-names = "rx"; 955 status = "disabled"; 956 }; 957 958 dfsdm2: filter@2 { 959 compatible = "st,stm32-dfsdm-adc"; 960 #io-channel-cells = <1>; 961 reg = <2>; 962 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 963 dmas = <&dmamux1 103 0x400 0x01>; 964 dma-names = "rx"; 965 status = "disabled"; 966 }; 967 968 dfsdm3: filter@3 { 969 compatible = "st,stm32-dfsdm-adc"; 970 #io-channel-cells = <1>; 971 reg = <3>; 972 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 973 dmas = <&dmamux1 104 0x400 0x01>; 974 dma-names = "rx"; 975 status = "disabled"; 976 }; 977 978 dfsdm4: filter@4 { 979 compatible = "st,stm32-dfsdm-adc"; 980 #io-channel-cells = <1>; 981 reg = <4>; 982 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 983 dmas = <&dmamux1 91 0x400 0x01>; 984 dma-names = "rx"; 985 status = "disabled"; 986 }; 987 988 dfsdm5: filter@5 { 989 compatible = "st,stm32-dfsdm-adc"; 990 #io-channel-cells = <1>; 991 reg = <5>; 992 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 993 dmas = <&dmamux1 92 0x400 0x01>; 994 dma-names = "rx"; 995 status = "disabled"; 996 }; 997 }; 998 999 dma1: dma-controller@48000000 { 1000 compatible = "st,stm32-dma"; 1001 reg = <0x48000000 0x400>; 1002 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&rcc DMA1>; 1011 resets = <&rcc DMA1_R>; 1012 #dma-cells = <4>; 1013 st,mem2mem; 1014 dma-requests = <8>; 1015 status = "disabled"; 1016 }; 1017 1018 dma2: dma-controller@48001000 { 1019 compatible = "st,stm32-dma"; 1020 reg = <0x48001000 0x400>; 1021 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&rcc DMA2>; 1030 resets = <&rcc DMA2_R>; 1031 #dma-cells = <4>; 1032 st,mem2mem; 1033 dma-requests = <8>; 1034 status = "disabled"; 1035 }; 1036 1037 dmamux1: dma-router@48002000 { 1038 compatible = "st,stm32h7-dmamux"; 1039 reg = <0x48002000 0x40>; 1040 #dma-cells = <3>; 1041 dma-requests = <128>; 1042 dma-masters = <&dma1 &dma2>; 1043 dma-channels = <16>; 1044 clocks = <&rcc DMAMUX>; 1045 resets = <&rcc DMAMUX_R>; 1046 status = "disabled"; 1047 }; 1048 1049 adc: adc@48003000 { 1050 compatible = "st,stm32mp1-adc-core"; 1051 reg = <0x48003000 0x400>; 1052 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1055 clock-names = "bus", "adc"; 1056 interrupt-controller; 1057 st,syscfg = <&syscfg>; 1058 #interrupt-cells = <1>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 status = "disabled"; 1062 1063 adc1: adc@0 { 1064 compatible = "st,stm32mp1-adc"; 1065 #io-channel-cells = <1>; 1066 reg = <0x0>; 1067 interrupt-parent = <&adc>; 1068 interrupts = <0>; 1069 dmas = <&dmamux1 9 0x400 0x01>; 1070 dma-names = "rx"; 1071 status = "disabled"; 1072 }; 1073 1074 adc2: adc@100 { 1075 compatible = "st,stm32mp1-adc"; 1076 #io-channel-cells = <1>; 1077 reg = <0x100>; 1078 interrupt-parent = <&adc>; 1079 interrupts = <1>; 1080 dmas = <&dmamux1 10 0x400 0x01>; 1081 dma-names = "rx"; 1082 status = "disabled"; 1083 }; 1084 }; 1085 1086 sdmmc3: mmc@48004000 { 1087 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1088 arm,primecell-periphid = <0x00253180>; 1089 reg = <0x48004000 0x400>; 1090 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1091 interrupt-names = "cmd_irq"; 1092 clocks = <&rcc SDMMC3_K>; 1093 clock-names = "apb_pclk"; 1094 resets = <&rcc SDMMC3_R>; 1095 cap-sd-highspeed; 1096 cap-mmc-highspeed; 1097 max-frequency = <120000000>; 1098 status = "disabled"; 1099 }; 1100 1101 usbotg_hs: usb-otg@49000000 { 1102 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1103 reg = <0x49000000 0x10000>; 1104 clocks = <&rcc USBO_K>; 1105 clock-names = "otg"; 1106 resets = <&rcc USBO_R>; 1107 reset-names = "dwc2"; 1108 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1109 g-rx-fifo-size = <512>; 1110 g-np-tx-fifo-size = <32>; 1111 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1112 dr_mode = "otg"; 1113 otg-rev = <0x200>; 1114 usb33d-supply = <&usb33>; 1115 status = "disabled"; 1116 }; 1117 1118 ipcc: mailbox@4c001000 { 1119 compatible = "st,stm32mp1-ipcc"; 1120 #mbox-cells = <1>; 1121 reg = <0x4c001000 0x400>; 1122 st,proc-id = <0>; 1123 interrupts-extended = 1124 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1125 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1126 <&exti 61 1>; 1127 interrupt-names = "rx", "tx", "wakeup"; 1128 clocks = <&rcc IPCC>; 1129 wakeup-source; 1130 status = "disabled"; 1131 }; 1132 1133 dcmi: dcmi@4c006000 { 1134 compatible = "st,stm32-dcmi"; 1135 reg = <0x4c006000 0x400>; 1136 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1137 resets = <&rcc CAMITF_R>; 1138 clocks = <&rcc DCMI>; 1139 clock-names = "mclk"; 1140 dmas = <&dmamux1 75 0x400 0x01>; 1141 dma-names = "tx"; 1142 status = "disabled"; 1143 }; 1144 1145 rcc: rcc@50000000 { 1146 compatible = "st,stm32mp1-rcc", "syscon"; 1147 reg = <0x50000000 0x1000>; 1148 #clock-cells = <1>; 1149 #reset-cells = <1>; 1150 }; 1151 1152 pwr_regulators: pwr@50001000 { 1153 compatible = "st,stm32mp1,pwr-reg"; 1154 reg = <0x50001000 0x10>; 1155 1156 reg11: reg11 { 1157 regulator-name = "reg11"; 1158 regulator-min-microvolt = <1100000>; 1159 regulator-max-microvolt = <1100000>; 1160 }; 1161 1162 reg18: reg18 { 1163 regulator-name = "reg18"; 1164 regulator-min-microvolt = <1800000>; 1165 regulator-max-microvolt = <1800000>; 1166 }; 1167 1168 usb33: usb33 { 1169 regulator-name = "usb33"; 1170 regulator-min-microvolt = <3300000>; 1171 regulator-max-microvolt = <3300000>; 1172 }; 1173 }; 1174 1175 pwr_mcu: pwr_mcu@50001014 { 1176 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 1177 reg = <0x50001014 0x4>; 1178 }; 1179 1180 exti: interrupt-controller@5000d000 { 1181 compatible = "st,stm32mp1-exti", "syscon"; 1182 interrupt-controller; 1183 #interrupt-cells = <2>; 1184 reg = <0x5000d000 0x400>; 1185 }; 1186 1187 syscfg: syscon@50020000 { 1188 compatible = "st,stm32mp157-syscfg", "syscon"; 1189 reg = <0x50020000 0x400>; 1190 clocks = <&rcc SYSCFG>; 1191 }; 1192 1193 lptimer2: timer@50021000 { 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 compatible = "st,stm32-lptimer"; 1197 reg = <0x50021000 0x400>; 1198 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1199 clocks = <&rcc LPTIM2_K>; 1200 clock-names = "mux"; 1201 wakeup-source; 1202 status = "disabled"; 1203 1204 pwm { 1205 compatible = "st,stm32-pwm-lp"; 1206 #pwm-cells = <3>; 1207 status = "disabled"; 1208 }; 1209 1210 trigger@1 { 1211 compatible = "st,stm32-lptimer-trigger"; 1212 reg = <1>; 1213 status = "disabled"; 1214 }; 1215 1216 counter { 1217 compatible = "st,stm32-lptimer-counter"; 1218 status = "disabled"; 1219 }; 1220 }; 1221 1222 lptimer3: timer@50022000 { 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 compatible = "st,stm32-lptimer"; 1226 reg = <0x50022000 0x400>; 1227 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&rcc LPTIM3_K>; 1229 clock-names = "mux"; 1230 wakeup-source; 1231 status = "disabled"; 1232 1233 pwm { 1234 compatible = "st,stm32-pwm-lp"; 1235 #pwm-cells = <3>; 1236 status = "disabled"; 1237 }; 1238 1239 trigger@2 { 1240 compatible = "st,stm32-lptimer-trigger"; 1241 reg = <2>; 1242 status = "disabled"; 1243 }; 1244 }; 1245 1246 lptimer4: timer@50023000 { 1247 compatible = "st,stm32-lptimer"; 1248 reg = <0x50023000 0x400>; 1249 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&rcc LPTIM4_K>; 1251 clock-names = "mux"; 1252 wakeup-source; 1253 status = "disabled"; 1254 1255 pwm { 1256 compatible = "st,stm32-pwm-lp"; 1257 #pwm-cells = <3>; 1258 status = "disabled"; 1259 }; 1260 }; 1261 1262 lptimer5: timer@50024000 { 1263 compatible = "st,stm32-lptimer"; 1264 reg = <0x50024000 0x400>; 1265 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&rcc LPTIM5_K>; 1267 clock-names = "mux"; 1268 wakeup-source; 1269 status = "disabled"; 1270 1271 pwm { 1272 compatible = "st,stm32-pwm-lp"; 1273 #pwm-cells = <3>; 1274 status = "disabled"; 1275 }; 1276 }; 1277 1278 vrefbuf: vrefbuf@50025000 { 1279 compatible = "st,stm32-vrefbuf"; 1280 reg = <0x50025000 0x8>; 1281 regulator-min-microvolt = <1500000>; 1282 regulator-max-microvolt = <2500000>; 1283 clocks = <&rcc VREF>; 1284 status = "disabled"; 1285 }; 1286 1287 sai4: sai@50027000 { 1288 compatible = "st,stm32h7-sai"; 1289 #address-cells = <1>; 1290 #size-cells = <1>; 1291 ranges = <0 0x50027000 0x400>; 1292 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1293 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1294 resets = <&rcc SAI4_R>; 1295 status = "disabled"; 1296 1297 sai4a: audio-controller@50027004 { 1298 #sound-dai-cells = <0>; 1299 compatible = "st,stm32-sai-sub-a"; 1300 reg = <0x04 0x20>; 1301 clocks = <&rcc SAI4_K>; 1302 clock-names = "sai_ck"; 1303 dmas = <&dmamux1 99 0x400 0x01>; 1304 status = "disabled"; 1305 }; 1306 1307 sai4b: audio-controller@50027024 { 1308 #sound-dai-cells = <0>; 1309 compatible = "st,stm32-sai-sub-b"; 1310 reg = <0x24 0x20>; 1311 clocks = <&rcc SAI4_K>; 1312 clock-names = "sai_ck"; 1313 dmas = <&dmamux1 100 0x400 0x01>; 1314 status = "disabled"; 1315 }; 1316 }; 1317 1318 dts: thermal@50028000 { 1319 compatible = "st,stm32-thermal"; 1320 reg = <0x50028000 0x100>; 1321 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1322 clocks = <&rcc TMPSENS>; 1323 clock-names = "pclk"; 1324 #thermal-sensor-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 hash1: hash@54002000 { 1329 compatible = "st,stm32f756-hash"; 1330 reg = <0x54002000 0x400>; 1331 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&rcc HASH1>; 1333 resets = <&rcc HASH1_R>; 1334 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1335 dma-names = "in"; 1336 dma-maxburst = <2>; 1337 status = "disabled"; 1338 }; 1339 1340 rng1: rng@54003000 { 1341 compatible = "st,stm32-rng"; 1342 reg = <0x54003000 0x400>; 1343 clocks = <&rcc RNG1_K>; 1344 resets = <&rcc RNG1_R>; 1345 status = "disabled"; 1346 }; 1347 1348 mdma1: dma-controller@58000000 { 1349 compatible = "st,stm32h7-mdma"; 1350 reg = <0x58000000 0x1000>; 1351 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1352 clocks = <&rcc MDMA>; 1353 resets = <&rcc MDMA_R>; 1354 #dma-cells = <5>; 1355 dma-channels = <32>; 1356 dma-requests = <48>; 1357 }; 1358 1359 fmc: memory-controller@58002000 { 1360 #address-cells = <2>; 1361 #size-cells = <1>; 1362 compatible = "st,stm32mp1-fmc2-ebi"; 1363 reg = <0x58002000 0x1000>; 1364 clocks = <&rcc FMC_K>; 1365 resets = <&rcc FMC_R>; 1366 status = "disabled"; 1367 1368 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1369 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1370 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1371 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1372 <4 0 0x80000000 0x10000000>; /* NAND */ 1373 1374 nand-controller@4,0 { 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 compatible = "st,stm32mp1-fmc2-nfc"; 1378 reg = <4 0x00000000 0x1000>, 1379 <4 0x08010000 0x1000>, 1380 <4 0x08020000 0x1000>, 1381 <4 0x01000000 0x1000>, 1382 <4 0x09010000 0x1000>, 1383 <4 0x09020000 0x1000>; 1384 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1385 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1386 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1387 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1388 dma-names = "tx", "rx", "ecc"; 1389 status = "disabled"; 1390 }; 1391 }; 1392 1393 qspi: spi@58003000 { 1394 compatible = "st,stm32f469-qspi"; 1395 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1396 reg-names = "qspi", "qspi_mm"; 1397 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1398 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1399 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1400 dma-names = "tx", "rx"; 1401 clocks = <&rcc QSPI_K>; 1402 resets = <&rcc QSPI_R>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 status = "disabled"; 1406 }; 1407 1408 sdmmc1: mmc@58005000 { 1409 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1410 arm,primecell-periphid = <0x00253180>; 1411 reg = <0x58005000 0x1000>; 1412 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1413 interrupt-names = "cmd_irq"; 1414 clocks = <&rcc SDMMC1_K>; 1415 clock-names = "apb_pclk"; 1416 resets = <&rcc SDMMC1_R>; 1417 cap-sd-highspeed; 1418 cap-mmc-highspeed; 1419 max-frequency = <120000000>; 1420 status = "disabled"; 1421 }; 1422 1423 sdmmc2: mmc@58007000 { 1424 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1425 arm,primecell-periphid = <0x00253180>; 1426 reg = <0x58007000 0x1000>; 1427 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1428 interrupt-names = "cmd_irq"; 1429 clocks = <&rcc SDMMC2_K>; 1430 clock-names = "apb_pclk"; 1431 resets = <&rcc SDMMC2_R>; 1432 cap-sd-highspeed; 1433 cap-mmc-highspeed; 1434 max-frequency = <120000000>; 1435 status = "disabled"; 1436 }; 1437 1438 crc1: crc@58009000 { 1439 compatible = "st,stm32f7-crc"; 1440 reg = <0x58009000 0x400>; 1441 clocks = <&rcc CRC1>; 1442 status = "disabled"; 1443 }; 1444 1445 ethernet0: ethernet@5800a000 { 1446 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1447 reg = <0x5800a000 0x2000>; 1448 reg-names = "stmmaceth"; 1449 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1450 interrupt-names = "macirq"; 1451 clock-names = "stmmaceth", 1452 "mac-clk-tx", 1453 "mac-clk-rx", 1454 "eth-ck", 1455 "ptp_ref", 1456 "ethstp"; 1457 clocks = <&rcc ETHMAC>, 1458 <&rcc ETHTX>, 1459 <&rcc ETHRX>, 1460 <&rcc ETHCK_K>, 1461 <&rcc ETHPTP_K>, 1462 <&rcc ETHSTP>; 1463 st,syscon = <&syscfg 0x4>; 1464 snps,mixed-burst; 1465 snps,pbl = <2>; 1466 snps,en-tx-lpi-clockgating; 1467 snps,axi-config = <&stmmac_axi_config_0>; 1468 snps,tso; 1469 status = "disabled"; 1470 1471 stmmac_axi_config_0: stmmac-axi-config { 1472 snps,wr_osr_lmt = <0x7>; 1473 snps,rd_osr_lmt = <0x7>; 1474 snps,blen = <0 0 0 0 16 8 4>; 1475 }; 1476 }; 1477 1478 usbh_ohci: usb@5800c000 { 1479 compatible = "generic-ohci"; 1480 reg = <0x5800c000 0x1000>; 1481 clocks = <&usbphyc>, <&rcc USBH>; 1482 resets = <&rcc USBH_R>; 1483 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1484 status = "disabled"; 1485 }; 1486 1487 usbh_ehci: usb@5800d000 { 1488 compatible = "generic-ehci"; 1489 reg = <0x5800d000 0x1000>; 1490 clocks = <&usbphyc>, <&rcc USBH>; 1491 resets = <&rcc USBH_R>; 1492 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1493 companion = <&usbh_ohci>; 1494 status = "disabled"; 1495 }; 1496 1497 ltdc: display-controller@5a001000 { 1498 compatible = "st,stm32-ltdc"; 1499 reg = <0x5a001000 0x400>; 1500 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1502 clocks = <&rcc LTDC_PX>; 1503 clock-names = "lcd"; 1504 resets = <&rcc LTDC_R>; 1505 status = "disabled"; 1506 1507 port { 1508 #address-cells = <1>; 1509 #size-cells = <0>; 1510 }; 1511 }; 1512 1513 iwdg2: watchdog@5a002000 { 1514 compatible = "st,stm32mp1-iwdg"; 1515 reg = <0x5a002000 0x400>; 1516 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1517 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 1518 clock-names = "pclk", "lsi"; 1519 status = "disabled"; 1520 }; 1521 1522 usbphyc: usbphyc@5a006000 { 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 #clock-cells = <0>; 1526 compatible = "st,stm32mp1-usbphyc"; 1527 reg = <0x5a006000 0x1000>; 1528 clocks = <&rcc USBPHY_K>; 1529 resets = <&rcc USBPHY_R>; 1530 vdda1v1-supply = <®11>; 1531 vdda1v8-supply = <®18>; 1532 status = "disabled"; 1533 1534 usbphyc_port0: usb-phy@0 { 1535 #phy-cells = <0>; 1536 reg = <0>; 1537 }; 1538 1539 usbphyc_port1: usb-phy@1 { 1540 #phy-cells = <1>; 1541 reg = <1>; 1542 }; 1543 }; 1544 1545 usart1: serial@5c000000 { 1546 compatible = "st,stm32h7-uart"; 1547 reg = <0x5c000000 0x400>; 1548 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1549 clocks = <&rcc USART1_K>; 1550 wakeup-source; 1551 status = "disabled"; 1552 }; 1553 1554 spi6: spi@5c001000 { 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 compatible = "st,stm32h7-spi"; 1558 reg = <0x5c001000 0x400>; 1559 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1560 clocks = <&rcc SPI6_K>; 1561 resets = <&rcc SPI6_R>; 1562 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1563 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1564 dma-names = "rx", "tx"; 1565 status = "disabled"; 1566 }; 1567 1568 i2c4: i2c@5c002000 { 1569 compatible = "st,stm32mp15-i2c"; 1570 reg = <0x5c002000 0x400>; 1571 interrupt-names = "event", "error"; 1572 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1574 clocks = <&rcc I2C4_K>; 1575 resets = <&rcc I2C4_R>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1579 wakeup-source; 1580 i2c-analog-filter; 1581 status = "disabled"; 1582 }; 1583 1584 iwdg1: watchdog@5c003000 { 1585 compatible = "st,stm32mp1-iwdg"; 1586 reg = <0x5C003000 0x400>; 1587 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1588 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 1589 clock-names = "pclk", "lsi"; 1590 status = "disabled"; 1591 }; 1592 1593 rtc: rtc@5c004000 { 1594 compatible = "st,stm32mp1-rtc"; 1595 reg = <0x5c004000 0x400>; 1596 clocks = <&rcc RTCAPB>, <&rcc RTC>; 1597 clock-names = "pclk", "rtc_ck"; 1598 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 1599 status = "disabled"; 1600 }; 1601 1602 bsec: efuse@5c005000 { 1603 compatible = "st,stm32mp15-bsec"; 1604 reg = <0x5c005000 0x400>; 1605 #address-cells = <1>; 1606 #size-cells = <1>; 1607 1608 cfg0_otp: cfg0_otp@0 { 1609 reg = <0x0 0x1>; 1610 }; 1611 part_number_otp: part_number_otp@4 { 1612 reg = <0x4 0x1>; 1613 }; 1614 monotonic_otp: monotonic_otp@10 { 1615 reg = <0x10 0x4>; 1616 }; 1617 nand_otp: nand_otp@24 { 1618 reg = <0x24 0x4>; 1619 }; 1620 uid_otp: uid_otp@34 { 1621 reg = <0x34 0xc>; 1622 }; 1623 package_otp: package_otp@40 { 1624 reg = <0x40 0x4>; 1625 }; 1626 hw2_otp: hw2_otp@48 { 1627 reg = <0x48 0x4>; 1628 }; 1629 ts_cal1: calib@5c { 1630 reg = <0x5c 0x2>; 1631 }; 1632 ts_cal2: calib@5e { 1633 reg = <0x5e 0x2>; 1634 }; 1635 pkh_otp: pkh_otp@60 { 1636 reg = <0x60 0x20>; 1637 }; 1638 ethernet_mac_address: mac@e4 { 1639 reg = <0xe4 0x8>; 1640 st,non-secure-otp; 1641 }; 1642 }; 1643 1644 etzpc: etzpc@5c007000 { 1645 compatible = "st,stm32-etzpc"; 1646 reg = <0x5C007000 0x400>; 1647 clocks = <&rcc TZPC>; 1648 status = "disabled"; 1649 secure-status = "okay"; 1650 }; 1651 1652 i2c6: i2c@5c009000 { 1653 compatible = "st,stm32mp15-i2c"; 1654 reg = <0x5c009000 0x400>; 1655 interrupt-names = "event", "error"; 1656 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1658 clocks = <&rcc I2C6_K>; 1659 resets = <&rcc I2C6_R>; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1663 wakeup-source; 1664 i2c-analog-filter; 1665 status = "disabled"; 1666 }; 1667 1668 tamp: tamp@5c00a000 { 1669 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 1670 reg = <0x5c00a000 0x400>; 1671 clocks = <&rcc RTCAPB>; 1672 }; 1673 1674 /* 1675 * Break node order to solve dependency probe issue between 1676 * pinctrl and exti. 1677 */ 1678 pinctrl: pinctrl@50002000 { 1679 #address-cells = <1>; 1680 #size-cells = <1>; 1681 compatible = "st,stm32mp157-pinctrl"; 1682 ranges = <0 0x50002000 0xa400>; 1683 interrupt-parent = <&exti>; 1684 st,syscfg = <&exti 0x60 0xff>; 1685 pins-are-numbered; 1686 1687 gpioa: gpio@50002000 { 1688 gpio-controller; 1689 #gpio-cells = <2>; 1690 interrupt-controller; 1691 #interrupt-cells = <2>; 1692 reg = <0x0 0x400>; 1693 clocks = <&rcc GPIOA>; 1694 st,bank-name = "GPIOA"; 1695 status = "disabled"; 1696 }; 1697 1698 gpiob: gpio@50003000 { 1699 gpio-controller; 1700 #gpio-cells = <2>; 1701 interrupt-controller; 1702 #interrupt-cells = <2>; 1703 reg = <0x1000 0x400>; 1704 clocks = <&rcc GPIOB>; 1705 st,bank-name = "GPIOB"; 1706 status = "disabled"; 1707 }; 1708 1709 gpioc: gpio@50004000 { 1710 gpio-controller; 1711 #gpio-cells = <2>; 1712 interrupt-controller; 1713 #interrupt-cells = <2>; 1714 reg = <0x2000 0x400>; 1715 clocks = <&rcc GPIOC>; 1716 st,bank-name = "GPIOC"; 1717 status = "disabled"; 1718 }; 1719 1720 gpiod: gpio@50005000 { 1721 gpio-controller; 1722 #gpio-cells = <2>; 1723 interrupt-controller; 1724 #interrupt-cells = <2>; 1725 reg = <0x3000 0x400>; 1726 clocks = <&rcc GPIOD>; 1727 st,bank-name = "GPIOD"; 1728 status = "disabled"; 1729 }; 1730 1731 gpioe: gpio@50006000 { 1732 gpio-controller; 1733 #gpio-cells = <2>; 1734 interrupt-controller; 1735 #interrupt-cells = <2>; 1736 reg = <0x4000 0x400>; 1737 clocks = <&rcc GPIOE>; 1738 st,bank-name = "GPIOE"; 1739 status = "disabled"; 1740 }; 1741 1742 gpiof: gpio@50007000 { 1743 gpio-controller; 1744 #gpio-cells = <2>; 1745 interrupt-controller; 1746 #interrupt-cells = <2>; 1747 reg = <0x5000 0x400>; 1748 clocks = <&rcc GPIOF>; 1749 st,bank-name = "GPIOF"; 1750 status = "disabled"; 1751 }; 1752 1753 gpiog: gpio@50008000 { 1754 gpio-controller; 1755 #gpio-cells = <2>; 1756 interrupt-controller; 1757 #interrupt-cells = <2>; 1758 reg = <0x6000 0x400>; 1759 clocks = <&rcc GPIOG>; 1760 st,bank-name = "GPIOG"; 1761 status = "disabled"; 1762 }; 1763 1764 gpioh: gpio@50009000 { 1765 gpio-controller; 1766 #gpio-cells = <2>; 1767 interrupt-controller; 1768 #interrupt-cells = <2>; 1769 reg = <0x7000 0x400>; 1770 clocks = <&rcc GPIOH>; 1771 st,bank-name = "GPIOH"; 1772 status = "disabled"; 1773 }; 1774 1775 gpioi: gpio@5000a000 { 1776 gpio-controller; 1777 #gpio-cells = <2>; 1778 interrupt-controller; 1779 #interrupt-cells = <2>; 1780 reg = <0x8000 0x400>; 1781 clocks = <&rcc GPIOI>; 1782 st,bank-name = "GPIOI"; 1783 status = "disabled"; 1784 }; 1785 1786 gpioj: gpio@5000b000 { 1787 gpio-controller; 1788 #gpio-cells = <2>; 1789 interrupt-controller; 1790 #interrupt-cells = <2>; 1791 reg = <0x9000 0x400>; 1792 clocks = <&rcc GPIOJ>; 1793 st,bank-name = "GPIOJ"; 1794 status = "disabled"; 1795 }; 1796 1797 gpiok: gpio@5000c000 { 1798 gpio-controller; 1799 #gpio-cells = <2>; 1800 interrupt-controller; 1801 #interrupt-cells = <2>; 1802 reg = <0xa000 0x400>; 1803 clocks = <&rcc GPIOK>; 1804 st,bank-name = "GPIOK"; 1805 status = "disabled"; 1806 }; 1807 }; 1808 1809 pinctrl_z: pinctrl@54004000 { 1810 #address-cells = <1>; 1811 #size-cells = <1>; 1812 compatible = "st,stm32mp157-z-pinctrl"; 1813 ranges = <0 0x54004000 0x400>; 1814 pins-are-numbered; 1815 interrupt-parent = <&exti>; 1816 st,syscfg = <&exti 0x60 0xff>; 1817 1818 gpioz: gpio@54004000 { 1819 gpio-controller; 1820 #gpio-cells = <2>; 1821 interrupt-controller; 1822 #interrupt-cells = <2>; 1823 reg = <0 0x400>; 1824 clocks = <&rcc GPIOZ>; 1825 st,bank-name = "GPIOZ"; 1826 st,bank-ioport = <11>; 1827 status = "disabled"; 1828 }; 1829 }; 1830 }; 1831 1832 mlahb: ahb { 1833 compatible = "st,mlahb", "simple-bus"; 1834 #address-cells = <1>; 1835 #size-cells = <1>; 1836 ranges; 1837 dma-ranges = <0x00000000 0x38000000 0x10000>, 1838 <0x10000000 0x10000000 0x60000>, 1839 <0x30000000 0x30000000 0x60000>; 1840 1841 m4_rproc: m4@10000000 { 1842 compatible = "st,stm32mp1-m4"; 1843 reg = <0x10000000 0x40000>, 1844 <0x30000000 0x40000>, 1845 <0x38000000 0x10000>; 1846 resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; 1847 reset-names = "mcu_rst", "hold_boot"; 1848 st,syscfg-tz = <&rcc 0x000 0x1>; 1849 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1850 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1851 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 1852 status = "disabled"; 1853 }; 1854 }; 1855}; 1856