core: riscv: core_mmu_arch: zero-initialize new page tables

New page table pages must always start cleared. On some
platforms (e.g., QEMU) RAM happens to be zeroed at reset,
but on real hardware (FP

core: riscv: core_mmu_arch: zero-initialize new page tables

New page table pages must always start cleared. On some
platforms (e.g., QEMU) RAM happens to be zeroed at reset,
but on real hardware (FPGA/SoC DDR) may not be the case.
Without this memset, stale contents can make
core_mmu_map_region() see non-zero old_attr and panic with
"Page is already mapped" when CFG_DYN_CONFIG is enabled.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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crypto: asu: Add crypto hash driver

Add support for following Hash algorithms
SHA-256, SHA-384, SHA-512, SHA3-256, SHA3-384, SHA3-512

Signed-off-by: Harsh Jain <h.jain@amd.com>
Signed-off-by: Aksha

crypto: asu: Add crypto hash driver

Add support for following Hash algorithms
SHA-256, SHA-384, SHA-512, SHA3-256, SHA3-384, SHA3-512

Signed-off-by: Harsh Jain <h.jain@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: amd: Add ASU support

Add support for the AMD Application Security Unit (ASU), the on-chip
Hardware Security Module (HSM) for Versal Gen 2.
The ASU manages all device-level security services

drivers: amd: Add ASU support

Add support for the AMD Application Security Unit (ASU), the on-chip
Hardware Security Module (HSM) for Versal Gen 2.
The ASU manages all device-level security services for user
applications, extending beyond accelerator-centric tasks.
Its firmware also exposes several software-based cryptographic
primitives, including:
- Key transfer
- RSA authentication (multiple padding schemes)
- HMAC
- Key Derivation Function (KDF)
- Key wrap / unwrap

Co-developed-by: Harsh Jain <h.jain@amd.com>
Signed-off-by: Harsh Jain <h.jain@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: fix cache invalidation of RSA buffer

When using CAAM to generate an RSA key the CPU caching of the DMA
buffers need to be controlled to ensure the correct visibility for both
devices.

drivers: caam: fix cache invalidation of RSA buffer

When using CAAM to generate an RSA key the CPU caching of the DMA
buffers need to be controlled to ensure the correct visibility for both
devices. For the n parameter the wrong address was used when
invalidating the CPU cache after the DMA operation, resulting in <key
length> bytes of the stack being invalidated (without flushing to
memory) instead of the buffer.

The first potential consequence of this is that any parts of the n
buffer that were cached during the key generation won't get read from
RAM, resulting in a corrupt key. This is unlikely since the n buffer
was correctly flushed immediately before starting the CAAM operation.
To reliably reproduce this, a read that should normally be harmless can
be inserted immediately before caam_jr_enqueue:
((volatile uint8_t *)genkey.n.data)[0];

The second effect of this bug is that parts of the do_gen_keypair stack
frame will have its cache lines invalidated (again without write back to
memory). With 4096 bit keys and a compiler that produces the right stack
layout this affects callee saved registers, the return pointer and
potentially a stack canary. I have not been able to see the effects of
this on my iMX8MQ test device.

Fixes: ccbcceeb73c1 ("drivers: caam: add CAAM key support for RSA")
Signed-off-by: Martin Nyhus <martin@nyhus.dev>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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drivers: caam: handle serialization of short params

Adjusts the caam key serialization code to account for keys where
sec_size < buf.length. When that is the case the serialization can only
touch th

drivers: caam: handle serialization of short params

Adjusts the caam key serialization code to account for keys where
sec_size < buf.length. When that is the case the serialization can only
touch the first sec_size bytes since the rest are invalid, and the
serialized length is thus sec_size.

If the default key type has been changed to plain this can happen during
RSA keygen if the d parameter ends up shorter than the key size in
bytes. In that case the valid bytes are at the front of the buffer and
do_gen_keypair accounts for this by setting sec_size correctly, and
caam_key_serialize_to_bn is called with an inkey in the sec_size <
buf.length state. This ended up creating corrupt keys for roughly 1% of
keygens, and was caught by various RSA tests in optee_test.

Fixes: 1495f6c4a82a ("drivers: caam: add CAAM key driver")
Signed-off-by: Martin Nyhus <martin@nyhus.dev>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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drivers: caam: fix bits/bytes confusion

Fixes two mixups of bits and bytes in caam_key_init that roughly cancel
each other out. Both sec_size and the result from
caam_key_serialized_size are values

drivers: caam: fix bits/bytes confusion

Fixes two mixups of bits and bytes in caam_key_init that roughly cancel
each other out. Both sec_size and the result from
caam_key_serialized_size are values in bytes, so the key sizes in bits
need to be converted. For plain text keys this makes no difference to
the result since they cancel each other out exactly.

For the default key type of BLACK_CCM the blob overhead is now correctly
counted as bytes instead of bits which decreases the headroom, but since
the default config of 4576 was calculated correctly, the assert still
shouldn't fail.

Fixes: 1495f6c4a82a ("drivers: caam: add CAAM key driver")
Signed-off-by: Martin Nyhus <martin@nyhus.dev>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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plat-k3: drivers: Increase mailbox timeout to 1000ms

Mailbox driver waits for 10ms to get a response from TIFS, before
flagging the transaction a failure. 10ms seems to be right at the edge,
since u

plat-k3: drivers: Increase mailbox timeout to 1000ms

Mailbox driver waits for 10ms to get a response from TIFS, before
flagging the transaction a failure. 10ms seems to be right at the edge,
since unrelated updates to other components in the boot chain are
causing the actual wait time to increase. Therefore increase the timeout
to 1000ms.

1000ms is chosen to keep uniformity with the mailbox driver in TF-A.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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plat-rockchip: px30: set CFG_CRYPTO_WITH_CE ?= y

Similarly to what's been done to RK3399 in commit 3ab148c8f4a0
("plat-rockchip: rk3399: set CFG_CRYPTO_WITH_CE ?= y"), we can enable
the Arm Cryptogr

plat-rockchip: px30: set CFG_CRYPTO_WITH_CE ?= y

Similarly to what's been done to RK3399 in commit 3ab148c8f4a0
("plat-rockchip: rk3399: set CFG_CRYPTO_WITH_CE ?= y"), we can enable
the Arm Cryptography Extensions by default for PX30 as Rockchip claims
they are supported in the datasheet[1].

Tested with:

xtest --aes-perf -m XTS -s 1000000 -n 1000

Before:
min=88574.2us max=91273us mean=88942.8us stddev=234.498us (cv 0.26365%) (10.7223MiB/s)

After:
min=3297.58us max=3655.75us mean=3464.66us stddev=59.7159us (cv 1.72357%) (275.258MiB/s)

Link: https://opensource.rock-chips.com/images/8/87/Rockchip_PX30_Datasheet_V1.4-20191227.pdf [1]
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

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core: arm: link.mk: Fix typo for python command line

Fix typo for python command line
$(q)scripts/gen_tee_bin.py => $(q)$(PYTHON3) scripts/gen_tee_bin.py

Signed-off-by: guan-gm.lin <guan-gm.lin@med

core: arm: link.mk: Fix typo for python command line

Fix typo for python command line
$(q)scripts/gen_tee_bin.py => $(q)$(PYTHON3) scripts/gen_tee_bin.py

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rockchip: disable early console by default

The early console is very useful for debugging. Alas, a misconfigured
early console seems to be halting/panicking OP-TEE OS.

Better have something al

plat-rockchip: disable early console by default

The early console is very useful for debugging. Alas, a misconfigured
early console seems to be halting/panicking OP-TEE OS.

Better have something always work possibly without console output (e.g.
if no FDT is passed to OP-TEE OS) than crashing without information.

The user can still enable the console if they want to for debugging
sessions.

This fixes OP-TEE OS crashing on RK3399 Puma which uses UART0 instead of
default UART2.

I've tested on PX30 and RK3588 by specifying a UART controller different
from the one that can be used by the device.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

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plat-mediatek: add support for MT7987 SoC

Add OP-TEE support for the MT7987 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-mediatek: add support for MT7981 SoC

Add OP-TEE support for the MT7981 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-mediatek: add support for MT7986 SoC

Add OP-TEE support for the MT7986 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

core: ffa: support fragmented memory transaction via S-EL2 SPMC

Add support to retrieve a fragmented memory transaction via an SPMC at
S-EL2.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.or

core: ffa: support fragmented memory transaction via S-EL2 SPMC

Add support to retrieve a fragmented memory transaction via an SPMC at
S-EL2.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>

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core: ffa: harden memory transaction checks

Harden the checks for FF-A memory transaction operations. Check that
internal parts are well aligned and that we can handle fragmented
transactions.

Sign

core: ffa: harden memory transaction checks

Harden the checks for FF-A memory transaction operations. Check that
internal parts are well aligned and that we can handle fragmented
transactions.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@arm.com>

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plat-qcom: Add support for lemans SoC

Add support for lemans SoC with platform support tested on lemans EVK
platform also known as Qualcomm Dragonwing IQ-9075. More information
regarding this platfo

plat-qcom: Add support for lemans SoC

Add support for lemans SoC with platform support tested on lemans EVK
platform also known as Qualcomm Dragonwing IQ-9075. More information
regarding this platform can be found here [1].

[1] https://www.qualcomm.com/internet-of-things/products/iq9-series/iq-9075

Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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drivers: imx_ocotp: write support i.MX6ULL

Reuse the same write function as the other i.MX6 SoCs since
the OCOTP IP is the same. i.MX6ULL just has fewer fuse banks
than i.MX6UL.

Reviewed-by: Sahil

drivers: imx_ocotp: write support i.MX6ULL

Reuse the same write function as the other i.MX6 SoCs since
the OCOTP IP is the same. i.MX6ULL just has fewer fuse banks
than i.MX6UL.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[m.felsch@pengutronix.de: adapt function name after renaming]
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: write support i.MX6Q/D/S/DL/UL

Reuse the same write functions as for i.MX8M SoC since they seem to use
the same OCOTP IP core according to the reference manual.

While on it, ren

drivers: imx_ocotp: write support i.MX6Q/D/S/DL/UL

Reuse the same write functions as for i.MX8M SoC since they seem to use
the same OCOTP IP core according to the reference manual.

While on it, rename the fuse write function and the set_timing helper
since it's no longer imx8m specific.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
[m.felsch@pengutronix.de: add function renaming]
[m.felsch@pengutronix.de: adapt commit message]
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: add support to burn fuses

This adds the support to burn fuses on i.MX8M SoCs. This approach assume
that the IPG clock is running at 66.67 MHz which is AHB/2 (AHB max.
clock = 133

drivers: imx_ocotp: add support to burn fuses

This adds the support to burn fuses on i.MX8M SoCs. This approach assume
that the IPG clock is running at 66.67 MHz which is AHB/2 (AHB max.
clock = 133 MHz). Due to lack of HW I added only the i.MX8M support.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix ocotp_ctrl_wait_for for i.MX6

Make use of the udelay() function and the newly added
OCOTP_OP_BUSY_TIMEOUT_US to align platforms which don't support
architected timers, like i

drivers: imx_ocotp: fix ocotp_ctrl_wait_for for i.MX6

Make use of the udelay() function and the newly added
OCOTP_OP_BUSY_TIMEOUT_US to align platforms which don't support
architected timers, like i.MX6Q with the ones that support architected
timers.

udelay() can be used since we have added the plat_get_freq() support for
all i.MX SoCs which don't support architected timers previously.

While on it drop the dsb() since the memory is mapped as non-cacheable
device-memory. So there is no need for a data barrier. Keep the isb() to
not send use-less register loads.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: make use of hw timers during ocotp_ctrl_wait_for

Use the ARM architected timer instead of assuming that the CPU is
running at 500MHz and the poll takes around ~20us.

Reviewed-by

drivers: imx_ocotp: make use of hw timers during ocotp_ctrl_wait_for

Use the ARM architected timer instead of assuming that the CPU is
running at 500MHz and the poll takes around ~20us.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix imx_ocotp_read g_base_addr and g_ocotp check

Check the g_base_addr and g_ocotp before do the first access.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by

drivers: imx_ocotp: fix imx_ocotp_read g_base_addr and g_ocotp check

Check the g_base_addr and g_ocotp before do the first access.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix clearing the error bit

According the reference manuals the ERROR bit should be cleared by
writing a '1' to the OCOTP_CTRL_CLR register and not by writing to the
OCOTP_CTRL di

drivers: imx_ocotp: fix clearing the error bit

According the reference manuals the ERROR bit should be cleared by
writing a '1' to the OCOTP_CTRL_CLR register and not by writing to the
OCOTP_CTRL direct.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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drivers: imx_ocotp: fix error/busy defines for i.MX8MP

The i.MX8MP has an OCOTP_CTRL_ADDR field which is 8-bit wide compared to
all other current supported i.MX SoCs. Due to the larger ADDR field al

drivers: imx_ocotp: fix error/busy defines for i.MX8MP

The i.MX8MP has an OCOTP_CTRL_ADDR field which is 8-bit wide compared to
all other current supported i.MX SoCs. Due to the larger ADDR field all
bits shifted by 1 bit.

Also make some minor style fixes while on it by replacing the mix of
tabs and spaces with tabs-only.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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core: plat-imx: i.MX6 CA9 has no generic timer

The Cortex-A9 inside of the i.MX6Q/D/QP/DL/S/SL/SLL SoCs has no generic
timer support, but all variants should boot with 792Mhz out of the boot
rom. Se

core: plat-imx: i.MX6 CA9 has no generic timer

The Cortex-A9 inside of the i.MX6Q/D/QP/DL/S/SL/SLL SoCs has no generic
timer support, but all variants should boot with 792Mhz out of the boot
rom. Set the Generic Timer configuration variable to n and implement the
required plat_get_freq() call to support the udelay() calls.

Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

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