1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/clock/stm32mp13-clksrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/gpio/stm32mp_gpio.h> 12#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 13#include "stm32mp135.dtsi" 14#include "stm32mp13xf.dtsi" 15#include "stm32mp13-pinctrl.dtsi" 16 17/ { 18 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 19 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 20 21 aliases { 22 serial0 = &uart4; 23 serial1 = &usart1; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 memory@c0000000 { 31 device_type = "memory"; 32 reg = <0xc0000000 0x20000000>; 33 }; 34 35 reserved-memory { 36 #address-cells = <1>; 37 #size-cells = <1>; 38 ranges; 39 40 optee_framebuffer: optee-framebuffer@dd000000 { 41 /* Secure framebuffer memory */ 42 reg = <0xdd000000 0x1000000>; 43 no-map; 44 }; 45 }; 46 47 vin: vin { 48 compatible = "regulator-fixed"; 49 regulator-name = "vin"; 50 regulator-min-microvolt = <5000000>; 51 regulator-max-microvolt = <5000000>; 52 regulator-always-on; 53 }; 54 55 v3v3_ao: v3v3_ao { 56 compatible = "regulator-fixed"; 57 regulator-name = "v3v3_ao"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 regulator-always-on; 61 }; 62}; 63 64&bsec { 65 board_id: board_id@f0 { 66 reg = <0xf0 0x4>; 67 st,non-secure-otp; 68 }; 69}; 70 71&etzpc { 72 st,decprot = 73 <DECPROT(STM32MP1_ETZPC_ADC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 74 <DECPROT(STM32MP1_ETZPC_ADC2_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 75 <DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 76 <DECPROT(STM32MP1_ETZPC_CRYP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 77 <DECPROT(STM32MP1_ETZPC_DCMIPP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 78 <DECPROT(STM32MP1_ETZPC_DDRCTRLPHY_ID, DECPROT_NS_R_S_W, DECPROT_UNLOCK)>, 79 <DECPROT(STM32MP1_ETZPC_ETH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 80 <DECPROT(STM32MP1_ETZPC_ETH2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 81 <DECPROT(STM32MP1_ETZPC_FMC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 82 <DECPROT(STM32MP1_ETZPC_HASH_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 83 <DECPROT(STM32MP1_ETZPC_I2C3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 84 <DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 85 <DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 86 <DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 87 <DECPROT(STM32MP1_ETZPC_LPTIM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 88 <DECPROT(STM32MP1_ETZPC_LPTIM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 89 <DECPROT(STM32MP1_ETZPC_LTDC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 90 <DECPROT(STM32MP1_ETZPC_MCE_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 91 <DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 92 <DECPROT(STM32MP1_ETZPC_PKA_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 93 <DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 94 <DECPROT(STM32MP1_ETZPC_RNG_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 95 <DECPROT(STM32MP1_ETZPC_SAES_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 96 <DECPROT(STM32MP1_ETZPC_SDMMC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 97 <DECPROT(STM32MP1_ETZPC_SDMMC2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 98 <DECPROT(STM32MP1_ETZPC_SPI4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 99 <DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 100 <DECPROT(STM32MP1_ETZPC_SRAM1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 101 <DECPROT(STM32MP1_ETZPC_SRAM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 102 <DECPROT(STM32MP1_ETZPC_SRAM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 103 <DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 104 <DECPROT(STM32MP1_ETZPC_TIM12_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 105 <DECPROT(STM32MP1_ETZPC_TIM13_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 106 <DECPROT(STM32MP1_ETZPC_TIM14_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 107 <DECPROT(STM32MP1_ETZPC_TIM15_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 108 <DECPROT(STM32MP1_ETZPC_TIM16_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 109 <DECPROT(STM32MP1_ETZPC_TIM17_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 110 <DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 111 <DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 112 <DECPROT(STM32MP1_ETZPC_USBPHYCTRL_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 113 <DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>; 114}; 115 116&gpiob { 117 st,protreg = <TZPROT(9)>; 118}; 119 120&gpiod { 121 st,protreg = <TZPROT(7)>; 122}; 123 124&gpioe { 125 st,protreg = <TZPROT(15)>; 126}; 127 128&i2c4 { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&i2c4_pins_a>; 131 i2c-scl-rising-time-ns = <185>; 132 i2c-scl-falling-time-ns = <20>; 133 clock-frequency = <400000>; 134 status = "okay"; 135 136 pmic: stpmic@33 { 137 compatible = "st,stpmic1"; 138 reg = <0x33>; 139 status = "okay"; 140 st,wakeup-pin-number = <1>; 141 st,notif-it-id = <0>; 142 143 regulators { 144 compatible = "st,stpmic1-regulators"; 145 buck1-supply = <&vin>; 146 buck2-supply = <&vin>; 147 buck3-supply = <&vin>; 148 buck4-supply = <&vin>; 149 ldo1-supply = <&vin>; 150 ldo4-supply = <&vin>; 151 ldo5-supply = <&vin>; 152 ldo6-supply = <&vin>; 153 vref_ddr-supply = <&vin>; 154 pwr_sw1-supply = <&bst_out>; 155 pwr_sw2-supply = <&v3v3_ao>; 156 157 vddcpu: buck1 { 158 regulator-name = "vddcpu"; 159 regulator-min-microvolt = <1250000>; 160 regulator-max-microvolt = <1350000>; 161 regulator-always-on; 162 regulator-over-current-protection; 163 164 lp-stop { 165 regulator-suspend-microvolt = <1250000>; 166 }; 167 lplv-stop { 168 regulator-suspend-microvolt = <900000>; 169 }; 170 lplv-stop2 { 171 regulator-off-in-suspend; 172 }; 173 standby-ddr-sr { 174 regulator-off-in-suspend; 175 }; 176 standby-ddr-off { 177 regulator-off-in-suspend; 178 }; 179 }; 180 181 vdd_ddr: buck2 { 182 regulator-name = "vdd_ddr"; 183 regulator-min-microvolt = <1350000>; 184 regulator-max-microvolt = <1350000>; 185 regulator-always-on; 186 regulator-over-current-protection; 187 188 standby-ddr-off { 189 regulator-off-in-suspend; 190 }; 191 }; 192 193 vdd: buck3 { 194 regulator-name = "vdd"; 195 regulator-min-microvolt = <3300000>; 196 regulator-max-microvolt = <3300000>; 197 regulator-always-on; 198 st,mask-reset; 199 regulator-over-current-protection; 200 }; 201 202 vddcore: buck4 { 203 regulator-name = "vddcore"; 204 regulator-min-microvolt = <1250000>; 205 regulator-max-microvolt = <1250000>; 206 regulator-always-on; 207 regulator-over-current-protection; 208 209 lplv-stop { 210 regulator-suspend-microvolt = <900000>; 211 }; 212 lplv-stop2 { 213 regulator-suspend-microvolt = <900000>; 214 }; 215 standby-ddr-sr { 216 regulator-off-in-suspend; 217 }; 218 standby-ddr-off { 219 regulator-off-in-suspend; 220 }; 221 }; 222 223 vdd_adc: ldo1 { 224 regulator-name = "vdd_adc"; 225 regulator-min-microvolt = <3300000>; 226 regulator-max-microvolt = <3300000>; 227 228 standby-ddr-sr { 229 regulator-off-in-suspend; 230 }; 231 standby-ddr-off { 232 regulator-off-in-suspend; 233 }; 234 }; 235 236 unused1: ldo2 { 237 regulator-name = "ldo2"; 238 }; 239 240 unused2: ldo3 { 241 regulator-name = "ldo3"; 242 }; 243 244 vdd_usb: ldo4 { 245 regulator-name = "vdd_usb"; 246 regulator-min-microvolt = <3300000>; 247 regulator-max-microvolt = <3300000>; 248 249 standby-ddr-sr { 250 regulator-off-in-suspend; 251 }; 252 standby-ddr-off { 253 regulator-off-in-suspend; 254 }; 255 }; 256 257 vdd_sd: ldo5 { 258 regulator-name = "vdd_sd"; 259 regulator-min-microvolt = <3300000>; 260 regulator-max-microvolt = <3300000>; 261 regulator-boot-on; 262 263 standby-ddr-sr { 264 regulator-off-in-suspend; 265 }; 266 standby-ddr-off { 267 regulator-off-in-suspend; 268 }; 269 }; 270 271 v1v8_periph: ldo6 { 272 regulator-name = "v1v8_periph"; 273 regulator-min-microvolt = <1800000>; 274 regulator-max-microvolt = <1800000>; 275 276 standby-ddr-sr { 277 regulator-off-in-suspend; 278 }; 279 standby-ddr-off { 280 regulator-off-in-suspend; 281 }; 282 }; 283 284 vref_ddr: vref_ddr { 285 regulator-name = "vref_ddr"; 286 regulator-always-on; 287 288 standby-ddr-sr { 289 regulator-off-in-suspend; 290 }; 291 standby-ddr-off { 292 regulator-off-in-suspend; 293 }; 294 }; 295 296 bst_out: boost { 297 regulator-name = "bst_out"; 298 }; 299 300 v3v3_sw: pwr_sw2 { 301 regulator-name = "v3v3_sw"; 302 regulator-active-discharge = <1>; 303 regulator-min-microvolt = <3300000>; 304 regulator-max-microvolt = <3300000>; 305 }; 306 }; 307 }; 308}; 309 310&iwdg1 { 311 timeout-sec = <32>; 312 status = "okay"; 313}; 314 315&oem_enc_key { 316 st,non-secure-otp-provisioning; 317}; 318 319&pwr_regulators { 320 vdd-supply = <&vdd>; 321 vdd_3v3_usbfs-supply = <&vdd_usb>; 322}; 323 324&rcc { 325 compatible = "st,stm32mp13-rcc", "syscon"; 326 327 st,clksrc = < 328 CLK_MPU_PLL1P 329 CLK_AXI_PLL2P 330 CLK_MLAHBS_PLL3 331 CLK_RTC_LSE 332 CLK_MCO1_HSE 333 CLK_MCO2_DISABLED 334 CLK_CKPER_HSE 335 CLK_ETH1_PLL4P 336 CLK_ETH2_PLL4P 337 CLK_SDMMC1_PLL4P 338 CLK_SDMMC2_PLL4P 339 CLK_STGEN_HSE 340 CLK_USBPHY_HSE 341 CLK_I2C4_HSI 342 CLK_I2C5_HSI 343 CLK_USBO_USBPHY 344 CLK_ADC2_CKPER 345 CLK_I2C12_HSI 346 CLK_UART1_HSI 347 CLK_UART2_HSI 348 CLK_UART35_HSI 349 CLK_UART4_HSI 350 CLK_UART6_HSI 351 CLK_UART78_HSI 352 CLK_SAES_AXI 353 CLK_DCMIPP_PLL2Q 354 CLK_LPTIM3_PCLK3 355 CLK_RNG1_PLL4R 356 >; 357 358 st,clkdiv = < 359 DIV(DIV_MPU, 1) 360 DIV(DIV_AXI, 0) 361 DIV(DIV_MLAHB, 0) 362 DIV(DIV_APB1, 1) 363 DIV(DIV_APB2, 1) 364 DIV(DIV_APB3, 1) 365 DIV(DIV_APB4, 1) 366 DIV(DIV_APB5, 2) 367 DIV(DIV_APB6, 1) 368 DIV(DIV_RTC, 0) 369 DIV(DIV_MCO1, 0) 370 DIV(DIV_MCO2, 0) 371 >; 372 373 st,pll_vco { 374 pll1_vco_2000Mhz: pll1-vco-2000Mhz { 375 src = <CLK_PLL12_HSE>; 376 divmn = <1 82>; 377 frac = <0xAAA>; 378 }; 379 380 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 381 src = <CLK_PLL12_HSE>; 382 divmn = <2 80>; 383 frac = <0x800>; 384 }; 385 386 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 387 src = <CLK_PLL12_HSE>; 388 divmn = <2 65>; 389 frac = <0x1400>; 390 }; 391 392 pll3_vco_417Mhz: pll3-vco-417Mhz { 393 src = <CLK_PLL3_HSE>; 394 divmn = <1 33>; 395 frac = <0x1a04>; 396 }; 397 398 pll4_vco_600Mhz: pll4-vco-600Mhz { 399 src = <CLK_PLL4_HSE>; 400 divmn = <1 49>; 401 }; 402 }; 403 404 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 405 pll1: st,pll@0 { 406 compatible = "st,stm32mp1-pll"; 407 reg = <0>; 408 409 st,pll = <&pll1_cfg1>; 410 411 pll1_cfg1: pll1_cfg1 { 412 st,pll_vco = <&pll1_vco_1300Mhz>; 413 st,pll_div_pqr = <0 1 1>; 414 }; 415 416 pll1_cfg2: pll1_cfg2 { 417 st,pll_vco = <&pll1_vco_2000Mhz>; 418 st,pll_div_pqr = <0 1 1>; 419 }; 420 }; 421 422 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 423 pll2: st,pll@1 { 424 compatible = "st,stm32mp1-pll"; 425 reg = <1>; 426 427 st,pll = <&pll2_cfg1>; 428 429 pll2_cfg1: pll2_cfg1 { 430 st,pll_vco = <&pll2_vco_1066Mhz>; 431 st,pll_div_pqr = <1 1 0>; 432 }; 433 }; 434 435 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 436 pll3: st,pll@2 { 437 compatible = "st,stm32mp1-pll"; 438 reg = <2>; 439 440 st,pll = <&pll3_cfg1>; 441 442 pll3_cfg1: pll3_cfg1 { 443 st,pll_vco = <&pll3_vco_417Mhz>; 444 st,pll_div_pqr = <1 16 36>; 445 }; 446 }; 447 448 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ 449 pll4: st,pll@3 { 450 compatible = "st,stm32mp1-pll"; 451 reg = <3>; 452 st,pll = <&pll4_cfg1>; 453 454 pll4_cfg1: pll4_cfg1 { 455 st,pll_vco = <&pll4_vco_600Mhz>; 456 st,pll_div_pqr = <11 59 11>; 457 }; 458 }; 459 460 st,clk_opp { 461 /* CK_MPU clock config for MP13 */ 462 st,ck_mpu { 463 464 cfg_1 { 465 hz = <650000000>; 466 st,clksrc = <CLK_MPU_PLL1P>; 467 st,pll = <&pll1_cfg1>; 468 }; 469 470 cfg_2 { 471 hz = <1000000000>; 472 st,clksrc = <CLK_MPU_PLL1P>; 473 st,pll = <&pll1_cfg2>; 474 }; 475 }; 476 }; 477}; 478 479&rng { 480 status = "okay"; 481 clock-error-detect; 482}; 483 484&rtc { 485 status = "okay"; 486}; 487 488&saes { 489 status = "okay"; 490}; 491 492&sdmmc1_io { 493 vddsd1-supply = <&vdd>; 494}; 495 496&sdmmc2_io { 497 vddsd2-supply = <&vdd>; 498}; 499 500&uart4 { 501 pinctrl-names = "default"; 502 pinctrl-0 = <&uart4_pins_a>; 503 status = "okay"; 504}; 505 506&usart1 { 507 pinctrl-names = "default"; 508 pinctrl-0 = <&usart1_pins_a>; 509 uart-has-rtscts; 510 status = "disabled"; 511}; 512