xref: /optee_os/core/arch/arm/dts/stm32mp251.dtsi (revision 182364b35c8464697f1b8d170033ca027edb8838) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/st,stm32mp25-rcc.h>
8#include <dt-bindings/firewall/stm32mp25-rifsc.h>
9#include <dt-bindings/firewall/stm32mp25-risab.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/reset/st,stm32mp25-rcc.h>
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			compatible = "arm,cortex-a35";
23			device_type = "cpu";
24			reg = <0>;
25			enable-method = "psci";
26		};
27	};
28
29	psci {
30		compatible = "arm,psci-1.0";
31		method = "smc";
32	};
33
34	intc: interrupt-controller@4ac00000 {
35		compatible = "arm,cortex-a7-gic";
36		#interrupt-cells = <3>;
37		interrupt-controller;
38		reg = <0x0 0x4ac10000 0x0 0x1000>,
39		      <0x0 0x4ac20000 0x0 0x2000>,
40		      <0x0 0x4ac40000 0x0 0x2000>,
41		      <0x0 0x4ac60000 0x0 0x2000>;
42		#address-cells = <1>;
43	};
44
45	clocks {
46		clk_hse: clk-hse {
47			#clock-cells = <0>;
48			compatible = "fixed-clock";
49			clock-frequency = <24000000>;
50		};
51
52		clk_hsi: clk-hsi {
53			#clock-cells = <0>;
54			compatible = "fixed-clock";
55			clock-frequency = <64000000>;
56		};
57
58		clk_lse: clk-lse {
59			#clock-cells = <0>;
60			compatible = "fixed-clock";
61			clock-frequency = <32768>;
62		};
63
64		clk_lsi: clk-lsi {
65			#clock-cells = <0>;
66			compatible = "fixed-clock";
67			clock-frequency = <32000>;
68		};
69
70		clk_msi: clk-msi {
71			#clock-cells = <0>;
72			compatible = "fixed-clock";
73			clock-frequency = <4000000>;
74		};
75
76		clk_i2sin: clk-i2sin {
77			#clock-cells = <0>;
78			compatible = "fixed-clock";
79			clock-frequency = <0>;
80		};
81
82		clk_rcbsec: clk-rcbsec {
83			#clock-cells = <0>;
84			compatible = "fixed-clock";
85			clock-frequency = <64000000>;
86		};
87	};
88
89	soc@0 {
90		compatible = "simple-bus";
91		#address-cells = <1>;
92		#size-cells = <1>;
93		interrupt-parent = <&intc>;
94		ranges = <0x0 0x0 0x0 0x80000000>;
95
96		hpdma1: dma-controller@40400000 {
97			compatible = "st,stm32-dma3";
98			reg = <0x40400000 0x1000>;
99			#dma-cells = <4>;
100			status = "disabled";
101		};
102
103		hpdma2: dma-controller@40410000 {
104			compatible = "st,stm32-dma3";
105			reg = <0x40410000 0x1000>;
106			#dma-cells = <4>;
107			status = "disabled";
108		};
109
110		hpdma3: dma-controller@40420000 {
111			compatible = "st,stm32-dma3";
112			reg = <0x40420000 0x1000>;
113			#dma-cells = <4>;
114			status = "disabled";
115		};
116
117		ipcc1: mailbox@40490000 {
118			compatible = "st,stm32mp25-ipcc";
119			reg = <0x40490000 0x400>;
120			status = "disabled";
121		};
122
123		rifsc: rifsc@42080000 {
124			compatible = "st,stm32mp25-rifsc", "simple-bus";
125			reg = <0x42080000 0x1000>;
126			#address-cells = <1>;
127			#size-cells = <1>;
128			#access-controller-cells = <1>;
129
130			usart2: serial@400e0000 {
131				compatible = "st,stm32h7-uart";
132				reg = <0x400e0000 0x400>;
133				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
134				clocks = <&rcc CK_KER_USART2>;
135				access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>;
136				status = "disabled";
137			};
138
139			rng: rng@42020000 {
140				compatible = "st,stm32mp25-rng";
141				reg = <0x42020000 0x400>;
142				clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>;
143				clock-names = "rng_clk", "rng_hclk";
144				resets = <&rcc RNG_R>;
145				access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>;
146			};
147		};
148
149		iac: iac@42090000 {
150			compatible = "st,stm32mp25-iac";
151			reg = <0x42090000 0x400>;
152			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
153		};
154
155		risaf1: risaf@420a0000 {
156			compatible = "st,stm32mp25-risaf";
157			reg = <0x420a0000 0x1000>;
158			clocks = <&rcc CK_BUS_BKPSRAM>;
159			st,mem-map = <0x0 0x42000000 0x0 0x2000>;
160		};
161
162		risaf2: risaf@420b0000 {
163			compatible = "st,stm32mp25-risaf";
164			reg = <0x420b0000 0x1000>;
165			clocks = <&rcc CK_KER_OSPI1>;
166			st,mem-map = <0x0 0x60000000 0x0 0x10000000>;
167			status = "disabled";
168		};
169
170		risaf4: risaf@420d0000 {
171			compatible = "st,stm32mp25-risaf-enc";
172			reg = <0x420d0000 0x1000>;
173			clocks = <&rcc CK_BUS_RISAF4>;
174			st,mem-map = <0x0 0x80000000 0x1 0x00000000>;
175		};
176
177		risaf5: risaf@420e0000 {
178			compatible = "st,stm32mp25-risaf";
179			reg = <0x420e0000 0x1000>;
180			clocks = <&rcc CK_BUS_PCIE>;
181			st,mem-map = <0x0 0x10000000 0x0 0x10000000>;
182			status = "disabled";
183		};
184
185		risab1: risab@420f0000 {
186			compatible = "st,stm32mp25-risab";
187			reg = <0x420f0000 0x1000>;
188			clocks = <&rcc CK_ICN_LS_MCU>;
189			st,mem-map = <0xa000000 0x20000>;
190			#access-controller-cells = <1>;
191		};
192
193		risab2: risab@42100000 {
194			compatible = "st,stm32mp25-risab";
195			reg = <0x42100000 0x1000>;
196			clocks = <&rcc CK_ICN_LS_MCU>;
197			st,mem-map = <0xa020000 0x20000>;
198			#access-controller-cells = <1>;
199		};
200
201		risab3: risab@42110000 {
202			compatible = "st,stm32mp25-risab";
203			reg = <0x42110000 0x1000>;
204			clocks = <&rcc CK_ICN_LS_MCU>;
205			st,mem-map = <0xa040000 0x20000>;
206			#access-controller-cells = <1>;
207		};
208
209		risab4: risab@42120000 {
210			compatible = "st,stm32mp25-risab";
211			reg = <0x42120000 0x1000>;
212			clocks = <&rcc CK_ICN_LS_MCU>;
213			st,mem-map = <0xa060000 0x20000>;
214			#access-controller-cells = <1>;
215		};
216
217		risab5: risab@42130000 {
218			compatible = "st,stm32mp25-risab";
219			reg = <0x42130000 0x1000>;
220			clocks = <&rcc CK_ICN_LS_MCU>;
221			st,mem-map = <0xa080000 0x20000>;
222			#access-controller-cells = <1>;
223		};
224
225		risab6: risab@42140000 {
226			compatible = "st,stm32mp25-risab";
227			reg = <0x42140000 0x1000>;
228			clocks = <&rcc CK_ICN_LS_MCU>;
229			st,mem-map = <0xa0a0000 0x20000>;
230			#access-controller-cells = <1>;
231			status = "disabled";
232		};
233
234		serc: serc@44080000 {
235			compatible = "st,stm32mp25-serc";
236			reg = <0x44080000 0x1000>;
237			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
238			clocks = <&rcc CK_BUS_SERC>;
239		};
240
241		rcc: rcc@44200000 {
242			compatible = "st,stm32mp25-rcc", "syscon";
243			reg = <0x44200000 0x10000>;
244			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
245
246			#clock-cells = <1>;
247			#reset-cells = <1>;
248			clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>,
249				 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>;
250			clock-names = "clk-hse", "clk-hsi", "clk-lse",
251				      "clk-lsi", "clk-msi", "clk-i2sin";
252
253			hsi_calibration: hsi-calibration {
254				compatible = "st,hsi-cal";
255				st,cal_hsi_dev = <31>;
256				st,cal_hsi_ref = <1953>;
257				status = "disabled";
258			};
259
260			msi_calibration: msi-calibration {
261				compatible = "st,msi-cal";
262				status = "disabled";
263			};
264		};
265
266		pinctrl: pinctrl@44240000 {
267			#address-cells = <1>;
268			#size-cells = <1>;
269			compatible = "st,stm32mp257-pinctrl";
270			ranges = <0 0x44240000 0xa0400>;
271			pins-are-numbered;
272
273			gpioa: gpio@44240000 {
274				gpio-controller;
275				#gpio-cells = <2>;
276				interrupt-controller;
277				#interrupt-cells = <2>;
278				reg = <0x0 0x400>;
279				clocks = <&rcc CK_BUS_GPIOA>;
280				st,bank-name = "GPIOA";
281				status = "disabled";
282			};
283
284			gpiob: gpio@44250000 {
285				gpio-controller;
286				#gpio-cells = <2>;
287				interrupt-controller;
288				#interrupt-cells = <2>;
289				reg = <0x10000 0x400>;
290				clocks = <&rcc CK_BUS_GPIOB>;
291				st,bank-name = "GPIOB";
292				status = "disabled";
293			};
294
295			gpioc: gpio@44260000 {
296				gpio-controller;
297				#gpio-cells = <2>;
298				interrupt-controller;
299				#interrupt-cells = <2>;
300				reg = <0x20000 0x400>;
301				clocks = <&rcc CK_BUS_GPIOC>;
302				st,bank-name = "GPIOC";
303				status = "disabled";
304			};
305
306			gpiod: gpio@44270000 {
307				gpio-controller;
308				#gpio-cells = <2>;
309				interrupt-controller;
310				#interrupt-cells = <2>;
311				reg = <0x30000 0x400>;
312				clocks = <&rcc CK_BUS_GPIOD>;
313				st,bank-name = "GPIOD";
314				status = "disabled";
315			};
316
317			gpioe: gpio@44280000 {
318				gpio-controller;
319				#gpio-cells = <2>;
320				interrupt-controller;
321				#interrupt-cells = <2>;
322				reg = <0x40000 0x400>;
323				clocks = <&rcc CK_BUS_GPIOE>;
324				st,bank-name = "GPIOE";
325				status = "disabled";
326			};
327
328			gpiof: gpio@44290000 {
329				gpio-controller;
330				#gpio-cells = <2>;
331				interrupt-controller;
332				#interrupt-cells = <2>;
333				reg = <0x50000 0x400>;
334				clocks = <&rcc CK_BUS_GPIOF>;
335				st,bank-name = "GPIOF";
336				status = "disabled";
337			};
338
339			gpiog: gpio@442a0000 {
340				gpio-controller;
341				#gpio-cells = <2>;
342				interrupt-controller;
343				#interrupt-cells = <2>;
344				reg = <0x60000 0x400>;
345				clocks = <&rcc CK_BUS_GPIOG>;
346				st,bank-name = "GPIOG";
347				status = "disabled";
348			};
349
350			gpioh: gpio@442b0000 {
351				gpio-controller;
352				#gpio-cells = <2>;
353				interrupt-controller;
354				#interrupt-cells = <2>;
355				reg = <0x70000 0x400>;
356				clocks = <&rcc CK_BUS_GPIOH>;
357				st,bank-name = "GPIOH";
358				status = "disabled";
359			};
360
361			gpioi: gpio@442c0000 {
362				gpio-controller;
363				#gpio-cells = <2>;
364				interrupt-controller;
365				#interrupt-cells = <2>;
366				reg = <0x80000 0x400>;
367				clocks = <&rcc CK_BUS_GPIOI>;
368				st,bank-name = "GPIOI";
369				status = "disabled";
370			};
371
372			gpioj: gpio@442d0000 {
373				gpio-controller;
374				#gpio-cells = <2>;
375				interrupt-controller;
376				#interrupt-cells = <2>;
377				reg = <0x90000 0x400>;
378				clocks = <&rcc CK_BUS_GPIOJ>;
379				st,bank-name = "GPIOJ";
380				status = "disabled";
381			};
382
383			gpiok: gpio@442e0000 {
384				gpio-controller;
385				#gpio-cells = <2>;
386				interrupt-controller;
387				#interrupt-cells = <2>;
388				reg = <0xa0000 0x400>;
389				clocks = <&rcc CK_BUS_GPIOK>;
390				st,bank-name = "GPIOK";
391				status = "disabled";
392			};
393		};
394
395		pinctrl_z: pinctrl-z@46200000 {
396			#address-cells = <1>;
397			#size-cells = <1>;
398			compatible = "st,stm32mp257-z-pinctrl";
399			ranges = <0 0x46200000 0x400>;
400			pins-are-numbered;
401
402			gpioz: gpio@46200000 {
403				gpio-controller;
404				#gpio-cells = <2>;
405				interrupt-controller;
406				#interrupt-cells = <2>;
407				reg = <0 0x400>;
408				clocks = <&rcc CK_BUS_GPIOZ>;
409				st,bank-name = "GPIOZ";
410				st,bank-ioport = <11>;
411				status = "disabled";
412			};
413		};
414
415		hsem: hwspinlock@46240000 {
416			compatible = "st,stm32mp25-hsem";
417			reg = <0x46240000 0x400>;
418			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
419			status = "disabled";
420		};
421
422		ipcc2: mailbox@46250000 {
423			compatible = "st,stm32mp25-ipcc";
424			reg = <0x46250000 0x400>;
425			status = "disabled";
426		};
427
428		fmc: memory-controller@48200000 {
429			#address-cells = <2>;
430			#size-cells = <1>;
431			compatible = "st,stm32mp25-fmc2-ebi";
432			reg = <0x48200000 0x400>;
433			status = "disabled";
434
435			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
436				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
437				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
438				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
439				 <4 0 0x80000000 0x10000000>; /* NAND */
440		};
441	};
442};
443