1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017-2024 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9#include <dt-bindings/firewall/stm32mp15-etzpc.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a7"; 21 clock-frequency = <650000000>; 22 device_type = "cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 arm-pmu { 28 compatible = "arm,cortex-a7-pmu"; 29 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-affinity = <&cpu0>; 31 interrupt-parent = <&intc>; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0"; 36 method = "smc"; 37 }; 38 39 intc: interrupt-controller@a0021000 { 40 compatible = "arm,cortex-a7-gic"; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 reg = <0xa0021000 0x1000>, 44 <0xa0022000 0x2000>; 45 }; 46 47 timer { 48 compatible = "arm,armv7-timer"; 49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 53 interrupt-parent = <&intc>; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 ipcc: mailbox@4c001000 { 127 compatible = "st,stm32mp1-ipcc"; 128 #mbox-cells = <1>; 129 reg = <0x4c001000 0x400>; 130 st,proc-id = <0>; 131 interrupts-extended = 132 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 134 <&exti 61 1>; 135 interrupt-names = "rx", "tx", "wakeup"; 136 clocks = <&rcc IPCC>; 137 wakeup-source; 138 status = "disabled"; 139 }; 140 141 rcc: rcc@50000000 { 142 compatible = "st,stm32mp1-rcc", "syscon"; 143 reg = <0x50000000 0x1000>; 144 #clock-cells = <1>; 145 #reset-cells = <1>; 146 }; 147 148 pwr_regulators: pwr@50001000 { 149 compatible = "st,stm32mp1,pwr-reg"; 150 reg = <0x50001000 0x10>; 151 152 reg11: reg11 { 153 regulator-name = "reg11"; 154 regulator-min-microvolt = <1100000>; 155 regulator-max-microvolt = <1100000>; 156 }; 157 158 reg18: reg18 { 159 regulator-name = "reg18"; 160 regulator-min-microvolt = <1800000>; 161 regulator-max-microvolt = <1800000>; 162 }; 163 164 usb33: usb33 { 165 regulator-name = "usb33"; 166 regulator-min-microvolt = <3300000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 }; 170 171 pwr_mcu: pwr_mcu@50001014 { 172 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 173 reg = <0x50001014 0x4>; 174 }; 175 176 exti: interrupt-controller@5000d000 { 177 compatible = "st,stm32mp1-exti", "syscon"; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 reg = <0x5000d000 0x400>; 181 }; 182 183 syscfg: syscon@50020000 { 184 compatible = "st,stm32mp157-syscfg", "syscon"; 185 reg = <0x50020000 0x400>; 186 clocks = <&rcc SYSCFG>; 187 }; 188 189 dts: thermal@50028000 { 190 compatible = "st,stm32-thermal"; 191 reg = <0x50028000 0x100>; 192 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&rcc TMPSENS>; 194 clock-names = "pclk"; 195 #thermal-sensor-cells = <0>; 196 status = "disabled"; 197 }; 198 199 mdma1: dma-controller@58000000 { 200 compatible = "st,stm32h7-mdma"; 201 reg = <0x58000000 0x1000>; 202 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&rcc MDMA>; 204 resets = <&rcc MDMA_R>; 205 #dma-cells = <5>; 206 dma-channels = <32>; 207 dma-requests = <48>; 208 }; 209 210 sdmmc1: mmc@58005000 { 211 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 212 arm,primecell-periphid = <0x00253180>; 213 reg = <0x58005000 0x1000>; 214 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 215 interrupt-names = "cmd_irq"; 216 clocks = <&rcc SDMMC1_K>; 217 clock-names = "apb_pclk"; 218 resets = <&rcc SDMMC1_R>; 219 cap-sd-highspeed; 220 cap-mmc-highspeed; 221 max-frequency = <120000000>; 222 status = "disabled"; 223 }; 224 225 sdmmc2: mmc@58007000 { 226 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 227 arm,primecell-periphid = <0x00253180>; 228 reg = <0x58007000 0x1000>; 229 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "cmd_irq"; 231 clocks = <&rcc SDMMC2_K>; 232 clock-names = "apb_pclk"; 233 resets = <&rcc SDMMC2_R>; 234 cap-sd-highspeed; 235 cap-mmc-highspeed; 236 max-frequency = <120000000>; 237 status = "disabled"; 238 }; 239 240 crc1: crc@58009000 { 241 compatible = "st,stm32f7-crc"; 242 reg = <0x58009000 0x400>; 243 clocks = <&rcc CRC1>; 244 status = "disabled"; 245 }; 246 247 usbh_ohci: usb@5800c000 { 248 compatible = "generic-ohci"; 249 reg = <0x5800c000 0x1000>; 250 clocks = <&usbphyc>, <&rcc USBH>; 251 resets = <&rcc USBH_R>; 252 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 253 status = "disabled"; 254 }; 255 256 usbh_ehci: usb@5800d000 { 257 compatible = "generic-ehci"; 258 reg = <0x5800d000 0x1000>; 259 clocks = <&usbphyc>, <&rcc USBH>; 260 resets = <&rcc USBH_R>; 261 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 262 companion = <&usbh_ohci>; 263 status = "disabled"; 264 }; 265 266 ltdc: display-controller@5a001000 { 267 compatible = "st,stm32-ltdc"; 268 reg = <0x5a001000 0x400>; 269 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&rcc LTDC_PX>; 272 clock-names = "lcd"; 273 resets = <&rcc LTDC_R>; 274 status = "disabled"; 275 276 port { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 }; 280 }; 281 282 iwdg2: watchdog@5a002000 { 283 compatible = "st,stm32mp1-iwdg"; 284 reg = <0x5a002000 0x400>; 285 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 287 clock-names = "pclk", "lsi"; 288 status = "disabled"; 289 }; 290 291 usbphyc: usbphyc@5a006000 { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 #clock-cells = <0>; 295 compatible = "st,stm32mp1-usbphyc"; 296 reg = <0x5a006000 0x1000>; 297 clocks = <&rcc USBPHY_K>; 298 resets = <&rcc USBPHY_R>; 299 vdda1v1-supply = <®11>; 300 vdda1v8-supply = <®18>; 301 status = "disabled"; 302 303 usbphyc_port0: usb-phy@0 { 304 #phy-cells = <0>; 305 reg = <0>; 306 }; 307 308 usbphyc_port1: usb-phy@1 { 309 #phy-cells = <1>; 310 reg = <1>; 311 }; 312 }; 313 314 rtc: rtc@5c004000 { 315 compatible = "st,stm32mp1-rtc"; 316 reg = <0x5c004000 0x400>; 317 clocks = <&rcc RTCAPB>, <&rcc RTC>; 318 clock-names = "pclk", "rtc_ck"; 319 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 320 status = "disabled"; 321 }; 322 323 bsec: efuse@5c005000 { 324 compatible = "st,stm32mp15-bsec"; 325 reg = <0x5c005000 0x400>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 329 cfg0_otp: cfg0_otp@0 { 330 reg = <0x0 0x1>; 331 }; 332 part_number_otp: part_number_otp@4 { 333 reg = <0x4 0x1>; 334 }; 335 monotonic_otp: monotonic_otp@10 { 336 reg = <0x10 0x4>; 337 }; 338 nand_otp: nand_otp@24 { 339 reg = <0x24 0x4>; 340 }; 341 uid_otp: uid_otp@34 { 342 reg = <0x34 0xc>; 343 }; 344 package_otp: package_otp@40 { 345 reg = <0x40 0x4>; 346 }; 347 hw2_otp: hw2_otp@48 { 348 reg = <0x48 0x4>; 349 }; 350 ts_cal1: calib@5c { 351 reg = <0x5c 0x2>; 352 }; 353 ts_cal2: calib@5e { 354 reg = <0x5e 0x2>; 355 }; 356 pkh_otp: pkh_otp@60 { 357 reg = <0x60 0x20>; 358 }; 359 ethernet_mac_address: mac@e4 { 360 reg = <0xe4 0x8>; 361 st,non-secure-otp; 362 }; 363 }; 364 365 tamp: tamp@5c00a000 { 366 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 367 reg = <0x5c00a000 0x400>; 368 clocks = <&rcc RTCAPB>; 369 }; 370 371 /* 372 * Break node order to solve dependency probe issue between 373 * pinctrl and exti. 374 */ 375 pinctrl: pinctrl@50002000 { 376 #address-cells = <1>; 377 #size-cells = <1>; 378 compatible = "st,stm32mp157-pinctrl"; 379 ranges = <0 0x50002000 0xa400>; 380 interrupt-parent = <&exti>; 381 st,syscfg = <&exti 0x60 0xff>; 382 pins-are-numbered; 383 384 gpioa: gpio@50002000 { 385 gpio-controller; 386 #gpio-cells = <2>; 387 interrupt-controller; 388 #interrupt-cells = <2>; 389 reg = <0x0 0x400>; 390 clocks = <&rcc GPIOA>; 391 st,bank-name = "GPIOA"; 392 status = "disabled"; 393 }; 394 395 gpiob: gpio@50003000 { 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 reg = <0x1000 0x400>; 401 clocks = <&rcc GPIOB>; 402 st,bank-name = "GPIOB"; 403 status = "disabled"; 404 }; 405 406 gpioc: gpio@50004000 { 407 gpio-controller; 408 #gpio-cells = <2>; 409 interrupt-controller; 410 #interrupt-cells = <2>; 411 reg = <0x2000 0x400>; 412 clocks = <&rcc GPIOC>; 413 st,bank-name = "GPIOC"; 414 status = "disabled"; 415 }; 416 417 gpiod: gpio@50005000 { 418 gpio-controller; 419 #gpio-cells = <2>; 420 interrupt-controller; 421 #interrupt-cells = <2>; 422 reg = <0x3000 0x400>; 423 clocks = <&rcc GPIOD>; 424 st,bank-name = "GPIOD"; 425 status = "disabled"; 426 }; 427 428 gpioe: gpio@50006000 { 429 gpio-controller; 430 #gpio-cells = <2>; 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 reg = <0x4000 0x400>; 434 clocks = <&rcc GPIOE>; 435 st,bank-name = "GPIOE"; 436 status = "disabled"; 437 }; 438 439 gpiof: gpio@50007000 { 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 reg = <0x5000 0x400>; 445 clocks = <&rcc GPIOF>; 446 st,bank-name = "GPIOF"; 447 status = "disabled"; 448 }; 449 450 gpiog: gpio@50008000 { 451 gpio-controller; 452 #gpio-cells = <2>; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 reg = <0x6000 0x400>; 456 clocks = <&rcc GPIOG>; 457 st,bank-name = "GPIOG"; 458 status = "disabled"; 459 }; 460 461 gpioh: gpio@50009000 { 462 gpio-controller; 463 #gpio-cells = <2>; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 reg = <0x7000 0x400>; 467 clocks = <&rcc GPIOH>; 468 st,bank-name = "GPIOH"; 469 status = "disabled"; 470 }; 471 472 gpioi: gpio@5000a000 { 473 gpio-controller; 474 #gpio-cells = <2>; 475 interrupt-controller; 476 #interrupt-cells = <2>; 477 reg = <0x8000 0x400>; 478 clocks = <&rcc GPIOI>; 479 st,bank-name = "GPIOI"; 480 status = "disabled"; 481 }; 482 483 gpioj: gpio@5000b000 { 484 gpio-controller; 485 #gpio-cells = <2>; 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 reg = <0x9000 0x400>; 489 clocks = <&rcc GPIOJ>; 490 st,bank-name = "GPIOJ"; 491 status = "disabled"; 492 }; 493 494 gpiok: gpio@5000c000 { 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 reg = <0xa000 0x400>; 500 clocks = <&rcc GPIOK>; 501 st,bank-name = "GPIOK"; 502 status = "disabled"; 503 }; 504 }; 505 506 pinctrl_z: pinctrl@54004000 { 507 #address-cells = <1>; 508 #size-cells = <1>; 509 compatible = "st,stm32mp157-z-pinctrl"; 510 ranges = <0 0x54004000 0x400>; 511 pins-are-numbered; 512 interrupt-parent = <&exti>; 513 st,syscfg = <&exti 0x60 0xff>; 514 515 gpioz: gpio@54004000 { 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 reg = <0 0x400>; 521 clocks = <&rcc GPIOZ>; 522 st,bank-name = "GPIOZ"; 523 st,bank-ioport = <11>; 524 status = "disabled"; 525 }; 526 }; 527 528 etzpc: etzpc@5c007000 { 529 compatible = "st,stm32-etzpc", "simple-bus"; 530 reg = <0x5C007000 0x400>; 531 clocks = <&rcc TZPC>; 532 #address-cells = <1>; 533 #size-cells = <1>; 534 #access-controller-cells = <1>; 535 536 timers2: timer@40000000 { 537 #address-cells = <1>; 538 #size-cells = <0>; 539 compatible = "st,stm32-timers"; 540 reg = <0x40000000 0x400>; 541 clocks = <&rcc TIM2_K>; 542 clock-names = "int"; 543 dmas = <&dmamux1 18 0x400 0x1>, 544 <&dmamux1 19 0x400 0x1>, 545 <&dmamux1 20 0x400 0x1>, 546 <&dmamux1 21 0x400 0x1>, 547 <&dmamux1 22 0x400 0x1>; 548 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 549 access-controllers = <&etzpc STM32MP1_ETZPC_TIM2_ID>; 550 status = "disabled"; 551 552 pwm { 553 compatible = "st,stm32-pwm"; 554 #pwm-cells = <3>; 555 status = "disabled"; 556 }; 557 558 timer@1 { 559 compatible = "st,stm32h7-timer-trigger"; 560 reg = <1>; 561 status = "disabled"; 562 }; 563 564 counter { 565 compatible = "st,stm32-timer-counter"; 566 status = "disabled"; 567 }; 568 }; 569 570 timers3: timer@40001000 { 571 #address-cells = <1>; 572 #size-cells = <0>; 573 compatible = "st,stm32-timers"; 574 reg = <0x40001000 0x400>; 575 clocks = <&rcc TIM3_K>; 576 clock-names = "int"; 577 dmas = <&dmamux1 23 0x400 0x1>, 578 <&dmamux1 24 0x400 0x1>, 579 <&dmamux1 25 0x400 0x1>, 580 <&dmamux1 26 0x400 0x1>, 581 <&dmamux1 27 0x400 0x1>, 582 <&dmamux1 28 0x400 0x1>; 583 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 584 access-controllers = <&etzpc STM32MP1_ETZPC_TIM3_ID>; 585 status = "disabled"; 586 587 pwm { 588 compatible = "st,stm32-pwm"; 589 #pwm-cells = <3>; 590 status = "disabled"; 591 }; 592 593 timer@2 { 594 compatible = "st,stm32h7-timer-trigger"; 595 reg = <2>; 596 status = "disabled"; 597 }; 598 599 counter { 600 compatible = "st,stm32-timer-counter"; 601 status = "disabled"; 602 }; 603 }; 604 605 timers4: timer@40002000 { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 compatible = "st,stm32-timers"; 609 reg = <0x40002000 0x400>; 610 clocks = <&rcc TIM4_K>; 611 clock-names = "int"; 612 dmas = <&dmamux1 29 0x400 0x1>, 613 <&dmamux1 30 0x400 0x1>, 614 <&dmamux1 31 0x400 0x1>, 615 <&dmamux1 32 0x400 0x1>; 616 dma-names = "ch1", "ch2", "ch3", "ch4"; 617 access-controllers = <&etzpc STM32MP1_ETZPC_TIM4_ID>; 618 status = "disabled"; 619 620 pwm { 621 compatible = "st,stm32-pwm"; 622 #pwm-cells = <3>; 623 status = "disabled"; 624 }; 625 626 timer@3 { 627 compatible = "st,stm32h7-timer-trigger"; 628 reg = <3>; 629 status = "disabled"; 630 }; 631 632 counter { 633 compatible = "st,stm32-timer-counter"; 634 status = "disabled"; 635 }; 636 }; 637 638 timers5: timer@40003000 { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 compatible = "st,stm32-timers"; 642 reg = <0x40003000 0x400>; 643 clocks = <&rcc TIM5_K>; 644 clock-names = "int"; 645 dmas = <&dmamux1 55 0x400 0x1>, 646 <&dmamux1 56 0x400 0x1>, 647 <&dmamux1 57 0x400 0x1>, 648 <&dmamux1 58 0x400 0x1>, 649 <&dmamux1 59 0x400 0x1>, 650 <&dmamux1 60 0x400 0x1>; 651 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 652 access-controllers = <&etzpc STM32MP1_ETZPC_TIM5_ID>; 653 status = "disabled"; 654 655 pwm { 656 compatible = "st,stm32-pwm"; 657 #pwm-cells = <3>; 658 status = "disabled"; 659 }; 660 661 timer@4 { 662 compatible = "st,stm32h7-timer-trigger"; 663 reg = <4>; 664 status = "disabled"; 665 }; 666 667 counter { 668 compatible = "st,stm32-timer-counter"; 669 status = "disabled"; 670 }; 671 }; 672 673 timers6: timer@40004000 { 674 #address-cells = <1>; 675 #size-cells = <0>; 676 compatible = "st,stm32-timers"; 677 reg = <0x40004000 0x400>; 678 clocks = <&rcc TIM6_K>; 679 clock-names = "int"; 680 dmas = <&dmamux1 69 0x400 0x1>; 681 dma-names = "up"; 682 access-controllers = <&etzpc STM32MP1_ETZPC_TIM6_ID>; 683 status = "disabled"; 684 685 timer@5 { 686 compatible = "st,stm32h7-timer-trigger"; 687 reg = <5>; 688 status = "disabled"; 689 }; 690 }; 691 692 timers7: timer@40005000 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 compatible = "st,stm32-timers"; 696 reg = <0x40005000 0x400>; 697 clocks = <&rcc TIM7_K>; 698 clock-names = "int"; 699 dmas = <&dmamux1 70 0x400 0x1>; 700 dma-names = "up"; 701 access-controllers = <&etzpc STM32MP1_ETZPC_TIM7_ID>; 702 status = "disabled"; 703 704 timer@6 { 705 compatible = "st,stm32h7-timer-trigger"; 706 reg = <6>; 707 status = "disabled"; 708 }; 709 }; 710 711 timers12: timer@40006000 { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 compatible = "st,stm32-timers"; 715 reg = <0x40006000 0x400>; 716 clocks = <&rcc TIM12_K>; 717 clock-names = "int"; 718 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 719 status = "disabled"; 720 721 pwm { 722 compatible = "st,stm32-pwm"; 723 #pwm-cells = <3>; 724 status = "disabled"; 725 }; 726 727 timer@11 { 728 compatible = "st,stm32h7-timer-trigger"; 729 reg = <11>; 730 status = "disabled"; 731 }; 732 }; 733 734 timers13: timer@40007000 { 735 #address-cells = <1>; 736 #size-cells = <0>; 737 compatible = "st,stm32-timers"; 738 reg = <0x40007000 0x400>; 739 clocks = <&rcc TIM13_K>; 740 clock-names = "int"; 741 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 742 status = "disabled"; 743 744 pwm { 745 compatible = "st,stm32-pwm"; 746 #pwm-cells = <3>; 747 status = "disabled"; 748 }; 749 750 timer@12 { 751 compatible = "st,stm32h7-timer-trigger"; 752 reg = <12>; 753 status = "disabled"; 754 }; 755 }; 756 757 timers14: timer@40008000 { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 compatible = "st,stm32-timers"; 761 reg = <0x40008000 0x400>; 762 clocks = <&rcc TIM14_K>; 763 clock-names = "int"; 764 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 765 status = "disabled"; 766 767 pwm { 768 compatible = "st,stm32-pwm"; 769 #pwm-cells = <3>; 770 status = "disabled"; 771 }; 772 773 timer@13 { 774 compatible = "st,stm32h7-timer-trigger"; 775 reg = <13>; 776 status = "disabled"; 777 }; 778 }; 779 780 lptimer1: timer@40009000 { 781 #address-cells = <1>; 782 #size-cells = <0>; 783 compatible = "st,stm32-lptimer"; 784 reg = <0x40009000 0x400>; 785 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&rcc LPTIM1_K>; 787 clock-names = "mux"; 788 wakeup-source; 789 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM1_ID>; 790 status = "disabled"; 791 792 pwm { 793 compatible = "st,stm32-pwm-lp"; 794 #pwm-cells = <3>; 795 status = "disabled"; 796 }; 797 798 trigger@0 { 799 compatible = "st,stm32-lptimer-trigger"; 800 reg = <0>; 801 status = "disabled"; 802 }; 803 804 counter { 805 compatible = "st,stm32-lptimer-counter"; 806 status = "disabled"; 807 }; 808 }; 809 810 spi2: spi@4000b000 { 811 #address-cells = <1>; 812 #size-cells = <0>; 813 compatible = "st,stm32h7-spi"; 814 reg = <0x4000b000 0x400>; 815 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&rcc SPI2_K>; 817 resets = <&rcc SPI2_R>; 818 dmas = <&dmamux1 39 0x400 0x05>, 819 <&dmamux1 40 0x400 0x05>; 820 dma-names = "rx", "tx"; 821 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 822 status = "disabled"; 823 }; 824 825 i2s2: audio-controller@4000b000 { 826 compatible = "st,stm32h7-i2s"; 827 #sound-dai-cells = <0>; 828 reg = <0x4000b000 0x400>; 829 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 830 dmas = <&dmamux1 39 0x400 0x01>, 831 <&dmamux1 40 0x400 0x01>; 832 dma-names = "rx", "tx"; 833 access-controllers = <&etzpc STM32MP1_ETZPC_SPI2_ID>; 834 status = "disabled"; 835 }; 836 837 spi3: spi@4000c000 { 838 #address-cells = <1>; 839 #size-cells = <0>; 840 compatible = "st,stm32h7-spi"; 841 reg = <0x4000c000 0x400>; 842 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&rcc SPI3_K>; 844 resets = <&rcc SPI3_R>; 845 dmas = <&dmamux1 61 0x400 0x05>, 846 <&dmamux1 62 0x400 0x05>; 847 dma-names = "rx", "tx"; 848 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 849 status = "disabled"; 850 }; 851 852 i2s3: audio-controller@4000c000 { 853 compatible = "st,stm32h7-i2s"; 854 #sound-dai-cells = <0>; 855 reg = <0x4000c000 0x400>; 856 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 857 dmas = <&dmamux1 61 0x400 0x01>, 858 <&dmamux1 62 0x400 0x01>; 859 dma-names = "rx", "tx"; 860 access-controllers = <&etzpc STM32MP1_ETZPC_SPI3_ID>; 861 status = "disabled"; 862 }; 863 864 spdifrx: audio-controller@4000d000 { 865 compatible = "st,stm32h7-spdifrx"; 866 #sound-dai-cells = <0>; 867 reg = <0x4000d000 0x400>; 868 clocks = <&rcc SPDIF_K>; 869 clock-names = "kclk"; 870 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 871 dmas = <&dmamux1 93 0x400 0x01>, 872 <&dmamux1 94 0x400 0x01>; 873 dma-names = "rx", "rx-ctrl"; 874 access-controllers = <&etzpc STM32MP1_ETZPC_SPDIFRX_ID>; 875 status = "disabled"; 876 }; 877 878 usart2: serial@4000e000 { 879 compatible = "st,stm32h7-uart"; 880 reg = <0x4000e000 0x400>; 881 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&rcc USART2_K>; 883 wakeup-source; 884 dmas = <&dmamux1 43 0x400 0x15>, 885 <&dmamux1 44 0x400 0x11>; 886 dma-names = "rx", "tx"; 887 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 888 status = "disabled"; 889 }; 890 891 usart3: serial@4000f000 { 892 compatible = "st,stm32h7-uart"; 893 reg = <0x4000f000 0x400>; 894 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&rcc USART3_K>; 896 wakeup-source; 897 dmas = <&dmamux1 45 0x400 0x15>, 898 <&dmamux1 46 0x400 0x11>; 899 dma-names = "rx", "tx"; 900 access-controllers = <&etzpc STM32MP1_ETZPC_USART3_ID>; 901 status = "disabled"; 902 }; 903 904 uart4: serial@40010000 { 905 compatible = "st,stm32h7-uart"; 906 reg = <0x40010000 0x400>; 907 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&rcc UART4_K>; 909 wakeup-source; 910 dmas = <&dmamux1 63 0x400 0x15>, 911 <&dmamux1 64 0x400 0x11>; 912 dma-names = "rx", "tx"; 913 access-controllers = <&etzpc STM32MP1_ETZPC_UART4_ID>; 914 status = "disabled"; 915 }; 916 917 uart5: serial@40011000 { 918 compatible = "st,stm32h7-uart"; 919 reg = <0x40011000 0x400>; 920 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&rcc UART5_K>; 922 wakeup-source; 923 dmas = <&dmamux1 65 0x400 0x15>, 924 <&dmamux1 66 0x400 0x11>; 925 dma-names = "rx", "tx"; 926 access-controllers = <&etzpc STM32MP1_ETZPC_UART5_ID>; 927 status = "disabled"; 928 }; 929 930 i2c1: i2c@40012000 { 931 compatible = "st,stm32mp15-i2c"; 932 reg = <0x40012000 0x400>; 933 interrupt-names = "event", "error"; 934 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&rcc I2C1_K>; 937 resets = <&rcc I2C1_R>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 st,syscfg-fmp = <&syscfg 0x4 0x1>; 941 wakeup-source; 942 i2c-analog-filter; 943 access-controllers = <&etzpc STM32MP1_ETZPC_I2C1_ID>; 944 status = "disabled"; 945 }; 946 947 i2c2: i2c@40013000 { 948 compatible = "st,stm32mp15-i2c"; 949 reg = <0x40013000 0x400>; 950 interrupt-names = "event", "error"; 951 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&rcc I2C2_K>; 954 resets = <&rcc I2C2_R>; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 st,syscfg-fmp = <&syscfg 0x4 0x2>; 958 wakeup-source; 959 i2c-analog-filter; 960 access-controllers = <&etzpc STM32MP1_ETZPC_I2C2_ID>; 961 status = "disabled"; 962 }; 963 964 i2c3: i2c@40014000 { 965 compatible = "st,stm32mp15-i2c"; 966 reg = <0x40014000 0x400>; 967 interrupt-names = "event", "error"; 968 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&rcc I2C3_K>; 971 resets = <&rcc I2C3_R>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 st,syscfg-fmp = <&syscfg 0x4 0x4>; 975 wakeup-source; 976 i2c-analog-filter; 977 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 978 status = "disabled"; 979 }; 980 981 i2c5: i2c@40015000 { 982 compatible = "st,stm32mp15-i2c"; 983 reg = <0x40015000 0x400>; 984 interrupt-names = "event", "error"; 985 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&rcc I2C5_K>; 988 resets = <&rcc I2C5_R>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 st,syscfg-fmp = <&syscfg 0x4 0x10>; 992 wakeup-source; 993 i2c-analog-filter; 994 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 995 status = "disabled"; 996 }; 997 998 cec: cec@40016000 { 999 compatible = "st,stm32-cec"; 1000 reg = <0x40016000 0x400>; 1001 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&rcc CEC_K>, <&rcc CEC>; 1003 clock-names = "cec", "hdmi-cec"; 1004 access-controllers = <&etzpc STM32MP1_ETZPC_CEC_ID>; 1005 status = "disabled"; 1006 }; 1007 1008 dac: dac@40017000 { 1009 compatible = "st,stm32h7-dac-core"; 1010 reg = <0x40017000 0x400>; 1011 clocks = <&rcc DAC12>; 1012 clock-names = "pclk"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 access-controllers = <&etzpc STM32MP1_ETZPC_DAC_ID>; 1016 status = "disabled"; 1017 1018 dac1: dac@1 { 1019 compatible = "st,stm32-dac"; 1020 #io-channel-cells = <1>; 1021 reg = <1>; 1022 status = "disabled"; 1023 }; 1024 1025 dac2: dac@2 { 1026 compatible = "st,stm32-dac"; 1027 #io-channel-cells = <1>; 1028 reg = <2>; 1029 status = "disabled"; 1030 }; 1031 }; 1032 1033 uart7: serial@40018000 { 1034 compatible = "st,stm32h7-uart"; 1035 reg = <0x40018000 0x400>; 1036 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&rcc UART7_K>; 1038 wakeup-source; 1039 dmas = <&dmamux1 79 0x400 0x15>, 1040 <&dmamux1 80 0x400 0x11>; 1041 dma-names = "rx", "tx"; 1042 access-controllers = <&etzpc STM32MP1_ETZPC_UART7_ID>; 1043 status = "disabled"; 1044 }; 1045 1046 uart8: serial@40019000 { 1047 compatible = "st,stm32h7-uart"; 1048 reg = <0x40019000 0x400>; 1049 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&rcc UART8_K>; 1051 wakeup-source; 1052 dmas = <&dmamux1 81 0x400 0x15>, 1053 <&dmamux1 82 0x400 0x11>; 1054 dma-names = "rx", "tx"; 1055 access-controllers = <&etzpc STM32MP1_ETZPC_UART8_ID>; 1056 status = "disabled"; 1057 }; 1058 1059 timers1: timer@44000000 { 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 compatible = "st,stm32-timers"; 1063 reg = <0x44000000 0x400>; 1064 clocks = <&rcc TIM1_K>; 1065 clock-names = "int"; 1066 dmas = <&dmamux1 11 0x400 0x1>, 1067 <&dmamux1 12 0x400 0x1>, 1068 <&dmamux1 13 0x400 0x1>, 1069 <&dmamux1 14 0x400 0x1>, 1070 <&dmamux1 15 0x400 0x1>, 1071 <&dmamux1 16 0x400 0x1>, 1072 <&dmamux1 17 0x400 0x1>; 1073 dma-names = "ch1", "ch2", "ch3", "ch4", 1074 "up", "trig", "com"; 1075 access-controllers = <&etzpc STM32MP1_ETZPC_TIM1_ID>; 1076 status = "disabled"; 1077 1078 pwm { 1079 compatible = "st,stm32-pwm"; 1080 #pwm-cells = <3>; 1081 status = "disabled"; 1082 }; 1083 1084 timer@0 { 1085 compatible = "st,stm32h7-timer-trigger"; 1086 reg = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 counter { 1091 compatible = "st,stm32-timer-counter"; 1092 status = "disabled"; 1093 }; 1094 }; 1095 1096 timers8: timer@44001000 { 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 compatible = "st,stm32-timers"; 1100 reg = <0x44001000 0x400>; 1101 clocks = <&rcc TIM8_K>; 1102 clock-names = "int"; 1103 dmas = <&dmamux1 47 0x400 0x1>, 1104 <&dmamux1 48 0x400 0x1>, 1105 <&dmamux1 49 0x400 0x1>, 1106 <&dmamux1 50 0x400 0x1>, 1107 <&dmamux1 51 0x400 0x1>, 1108 <&dmamux1 52 0x400 0x1>, 1109 <&dmamux1 53 0x400 0x1>; 1110 dma-names = "ch1", "ch2", "ch3", "ch4", 1111 "up", "trig", "com"; 1112 access-controllers = <&etzpc STM32MP1_ETZPC_TIM8_ID>; 1113 status = "disabled"; 1114 1115 pwm { 1116 compatible = "st,stm32-pwm"; 1117 #pwm-cells = <3>; 1118 status = "disabled"; 1119 }; 1120 1121 timer@7 { 1122 compatible = "st,stm32h7-timer-trigger"; 1123 reg = <7>; 1124 status = "disabled"; 1125 }; 1126 1127 counter { 1128 compatible = "st,stm32-timer-counter"; 1129 status = "disabled"; 1130 }; 1131 }; 1132 1133 usart6: serial@44003000 { 1134 compatible = "st,stm32h7-uart"; 1135 reg = <0x44003000 0x400>; 1136 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&rcc USART6_K>; 1138 wakeup-source; 1139 dmas = <&dmamux1 71 0x400 0x15>, 1140 <&dmamux1 72 0x400 0x11>; 1141 dma-names = "rx", "tx"; 1142 access-controllers = <&etzpc STM32MP1_ETZPC_USART6_ID>; 1143 status = "disabled"; 1144 }; 1145 1146 spi1: spi@44004000 { 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 compatible = "st,stm32h7-spi"; 1150 reg = <0x44004000 0x400>; 1151 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&rcc SPI1_K>; 1153 resets = <&rcc SPI1_R>; 1154 dmas = <&dmamux1 37 0x400 0x05>, 1155 <&dmamux1 38 0x400 0x05>; 1156 dma-names = "rx", "tx"; 1157 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1158 status = "disabled"; 1159 }; 1160 1161 i2s1: audio-controller@44004000 { 1162 compatible = "st,stm32h7-i2s"; 1163 #sound-dai-cells = <0>; 1164 reg = <0x44004000 0x400>; 1165 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1166 dmas = <&dmamux1 37 0x400 0x01>, 1167 <&dmamux1 38 0x400 0x01>; 1168 dma-names = "rx", "tx"; 1169 access-controllers = <&etzpc STM32MP1_ETZPC_SPI1_ID>; 1170 status = "disabled"; 1171 }; 1172 1173 spi4: spi@44005000 { 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 compatible = "st,stm32h7-spi"; 1177 reg = <0x44005000 0x400>; 1178 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&rcc SPI4_K>; 1180 resets = <&rcc SPI4_R>; 1181 dmas = <&dmamux1 83 0x400 0x05>, 1182 <&dmamux1 84 0x400 0x05>; 1183 dma-names = "rx", "tx"; 1184 access-controllers = <&etzpc STM32MP1_ETZPC_SPI4_ID>; 1185 status = "disabled"; 1186 }; 1187 1188 timers15: timer@44006000 { 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 compatible = "st,stm32-timers"; 1192 reg = <0x44006000 0x400>; 1193 clocks = <&rcc TIM15_K>; 1194 clock-names = "int"; 1195 dmas = <&dmamux1 105 0x400 0x1>, 1196 <&dmamux1 106 0x400 0x1>, 1197 <&dmamux1 107 0x400 0x1>, 1198 <&dmamux1 108 0x400 0x1>; 1199 dma-names = "ch1", "up", "trig", "com"; 1200 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 1201 status = "disabled"; 1202 1203 pwm { 1204 compatible = "st,stm32-pwm"; 1205 #pwm-cells = <3>; 1206 status = "disabled"; 1207 }; 1208 1209 timer@14 { 1210 compatible = "st,stm32h7-timer-trigger"; 1211 reg = <14>; 1212 status = "disabled"; 1213 }; 1214 }; 1215 1216 timers16: timer@44007000 { 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 compatible = "st,stm32-timers"; 1220 reg = <0x44007000 0x400>; 1221 clocks = <&rcc TIM16_K>; 1222 clock-names = "int"; 1223 dmas = <&dmamux1 109 0x400 0x1>, 1224 <&dmamux1 110 0x400 0x1>; 1225 dma-names = "ch1", "up"; 1226 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 1227 status = "disabled"; 1228 1229 pwm { 1230 compatible = "st,stm32-pwm"; 1231 #pwm-cells = <3>; 1232 status = "disabled"; 1233 }; 1234 timer@15 { 1235 compatible = "st,stm32h7-timer-trigger"; 1236 reg = <15>; 1237 status = "disabled"; 1238 }; 1239 }; 1240 1241 timers17: timer@44008000 { 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 compatible = "st,stm32-timers"; 1245 reg = <0x44008000 0x400>; 1246 clocks = <&rcc TIM17_K>; 1247 clock-names = "int"; 1248 dmas = <&dmamux1 111 0x400 0x1>, 1249 <&dmamux1 112 0x400 0x1>; 1250 dma-names = "ch1", "up"; 1251 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 1252 status = "disabled"; 1253 1254 pwm { 1255 compatible = "st,stm32-pwm"; 1256 #pwm-cells = <3>; 1257 status = "disabled"; 1258 }; 1259 1260 timer@16 { 1261 compatible = "st,stm32h7-timer-trigger"; 1262 reg = <16>; 1263 status = "disabled"; 1264 }; 1265 }; 1266 1267 spi5: spi@44009000 { 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 compatible = "st,stm32h7-spi"; 1271 reg = <0x44009000 0x400>; 1272 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&rcc SPI5_K>; 1274 resets = <&rcc SPI5_R>; 1275 dmas = <&dmamux1 85 0x400 0x05>, 1276 <&dmamux1 86 0x400 0x05>; 1277 dma-names = "rx", "tx"; 1278 access-controllers = <&etzpc STM32MP1_ETZPC_SPI5_ID>; 1279 status = "disabled"; 1280 }; 1281 1282 sai1: sai@4400a000 { 1283 compatible = "st,stm32h7-sai"; 1284 #address-cells = <1>; 1285 #size-cells = <1>; 1286 ranges = <0 0x4400a000 0x400>; 1287 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 1288 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1289 resets = <&rcc SAI1_R>; 1290 access-controllers = <&etzpc STM32MP1_ETZPC_SAI1_ID>; 1291 status = "disabled"; 1292 1293 sai1a: audio-controller@4400a004 { 1294 #sound-dai-cells = <0>; 1295 1296 compatible = "st,stm32-sai-sub-a"; 1297 reg = <0x4 0x20>; 1298 clocks = <&rcc SAI1_K>; 1299 clock-names = "sai_ck"; 1300 dmas = <&dmamux1 87 0x400 0x01>; 1301 status = "disabled"; 1302 }; 1303 1304 sai1b: audio-controller@4400a024 { 1305 #sound-dai-cells = <0>; 1306 compatible = "st,stm32-sai-sub-b"; 1307 reg = <0x24 0x20>; 1308 clocks = <&rcc SAI1_K>; 1309 clock-names = "sai_ck"; 1310 dmas = <&dmamux1 88 0x400 0x01>; 1311 status = "disabled"; 1312 }; 1313 }; 1314 1315 sai2: sai@4400b000 { 1316 compatible = "st,stm32h7-sai"; 1317 #address-cells = <1>; 1318 #size-cells = <1>; 1319 ranges = <0 0x4400b000 0x400>; 1320 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 1321 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1322 resets = <&rcc SAI2_R>; 1323 access-controllers = <&etzpc STM32MP1_ETZPC_SAI2_ID>; 1324 status = "disabled"; 1325 1326 sai2a: audio-controller@4400b004 { 1327 #sound-dai-cells = <0>; 1328 compatible = "st,stm32-sai-sub-a"; 1329 reg = <0x4 0x20>; 1330 clocks = <&rcc SAI2_K>; 1331 clock-names = "sai_ck"; 1332 dmas = <&dmamux1 89 0x400 0x01>; 1333 status = "disabled"; 1334 }; 1335 1336 sai2b: audio-controller@4400b024 { 1337 #sound-dai-cells = <0>; 1338 compatible = "st,stm32-sai-sub-b"; 1339 reg = <0x24 0x20>; 1340 clocks = <&rcc SAI2_K>; 1341 clock-names = "sai_ck"; 1342 dmas = <&dmamux1 90 0x400 0x01>; 1343 status = "disabled"; 1344 }; 1345 }; 1346 1347 sai3: sai@4400c000 { 1348 compatible = "st,stm32h7-sai"; 1349 #address-cells = <1>; 1350 #size-cells = <1>; 1351 ranges = <0 0x4400c000 0x400>; 1352 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 1353 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1354 resets = <&rcc SAI3_R>; 1355 access-controllers = <&etzpc STM32MP1_ETZPC_SAI3_ID>; 1356 status = "disabled"; 1357 1358 sai3a: audio-controller@4400c004 { 1359 #sound-dai-cells = <0>; 1360 compatible = "st,stm32-sai-sub-a"; 1361 reg = <0x04 0x20>; 1362 clocks = <&rcc SAI3_K>; 1363 clock-names = "sai_ck"; 1364 dmas = <&dmamux1 113 0x400 0x01>; 1365 status = "disabled"; 1366 }; 1367 1368 sai3b: audio-controller@4400c024 { 1369 #sound-dai-cells = <0>; 1370 compatible = "st,stm32-sai-sub-b"; 1371 reg = <0x24 0x20>; 1372 clocks = <&rcc SAI3_K>; 1373 clock-names = "sai_ck"; 1374 dmas = <&dmamux1 114 0x400 0x01>; 1375 status = "disabled"; 1376 }; 1377 }; 1378 1379 dfsdm: dfsdm@4400d000 { 1380 compatible = "st,stm32mp1-dfsdm"; 1381 reg = <0x4400d000 0x800>; 1382 clocks = <&rcc DFSDM_K>; 1383 clock-names = "dfsdm"; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 access-controllers = <&etzpc STM32MP1_ETZPC_DFSDM_ID>; 1387 status = "disabled"; 1388 1389 dfsdm0: filter@0 { 1390 compatible = "st,stm32-dfsdm-adc"; 1391 #io-channel-cells = <1>; 1392 reg = <0>; 1393 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1394 dmas = <&dmamux1 101 0x400 0x01>; 1395 dma-names = "rx"; 1396 status = "disabled"; 1397 }; 1398 1399 dfsdm1: filter@1 { 1400 compatible = "st,stm32-dfsdm-adc"; 1401 #io-channel-cells = <1>; 1402 reg = <1>; 1403 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1404 dmas = <&dmamux1 102 0x400 0x01>; 1405 dma-names = "rx"; 1406 status = "disabled"; 1407 }; 1408 1409 dfsdm2: filter@2 { 1410 compatible = "st,stm32-dfsdm-adc"; 1411 #io-channel-cells = <1>; 1412 reg = <2>; 1413 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1414 dmas = <&dmamux1 103 0x400 0x01>; 1415 dma-names = "rx"; 1416 status = "disabled"; 1417 }; 1418 1419 dfsdm3: filter@3 { 1420 compatible = "st,stm32-dfsdm-adc"; 1421 #io-channel-cells = <1>; 1422 reg = <3>; 1423 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1424 dmas = <&dmamux1 104 0x400 0x01>; 1425 dma-names = "rx"; 1426 status = "disabled"; 1427 }; 1428 1429 dfsdm4: filter@4 { 1430 compatible = "st,stm32-dfsdm-adc"; 1431 #io-channel-cells = <1>; 1432 reg = <4>; 1433 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1434 dmas = <&dmamux1 91 0x400 0x01>; 1435 dma-names = "rx"; 1436 status = "disabled"; 1437 }; 1438 1439 dfsdm5: filter@5 { 1440 compatible = "st,stm32-dfsdm-adc"; 1441 #io-channel-cells = <1>; 1442 reg = <5>; 1443 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1444 dmas = <&dmamux1 92 0x400 0x01>; 1445 dma-names = "rx"; 1446 status = "disabled"; 1447 }; 1448 }; 1449 1450 dma1: dma-controller@48000000 { 1451 compatible = "st,stm32-dma"; 1452 reg = <0x48000000 0x400>; 1453 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1461 clocks = <&rcc DMA1>; 1462 resets = <&rcc DMA1_R>; 1463 #dma-cells = <4>; 1464 st,mem2mem; 1465 dma-requests = <8>; 1466 access-controllers = <&etzpc STM32MP1_ETZPC_DMA1_ID>; 1467 status = "disabled"; 1468 }; 1469 1470 dma2: dma-controller@48001000 { 1471 compatible = "st,stm32-dma"; 1472 reg = <0x48001000 0x400>; 1473 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1481 clocks = <&rcc DMA2>; 1482 resets = <&rcc DMA2_R>; 1483 #dma-cells = <4>; 1484 st,mem2mem; 1485 dma-requests = <8>; 1486 access-controllers = <&etzpc STM32MP1_ETZPC_DMA2_ID>; 1487 status = "disabled"; 1488 }; 1489 1490 dmamux1: dma-router@48002000 { 1491 compatible = "st,stm32h7-dmamux"; 1492 reg = <0x48002000 0x40>; 1493 #dma-cells = <3>; 1494 dma-requests = <128>; 1495 dma-masters = <&dma1 &dma2>; 1496 dma-channels = <16>; 1497 clocks = <&rcc DMAMUX>; 1498 resets = <&rcc DMAMUX_R>; 1499 access-controllers = <&etzpc STM32MP1_ETZPC_DMAMUX_ID>; 1500 status = "disabled"; 1501 }; 1502 1503 adc: adc@48003000 { 1504 compatible = "st,stm32mp1-adc-core"; 1505 reg = <0x48003000 0x400>; 1506 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1508 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1509 clock-names = "bus", "adc"; 1510 interrupt-controller; 1511 st,syscfg = <&syscfg>; 1512 #interrupt-cells = <1>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 access-controllers = <&etzpc STM32MP1_ETZPC_ADC_ID>; 1516 status = "disabled"; 1517 1518 adc1: adc@0 { 1519 compatible = "st,stm32mp1-adc"; 1520 #io-channel-cells = <1>; 1521 reg = <0x0>; 1522 interrupt-parent = <&adc>; 1523 interrupts = <0>; 1524 dmas = <&dmamux1 9 0x400 0x01>; 1525 dma-names = "rx"; 1526 status = "disabled"; 1527 }; 1528 1529 adc2: adc@100 { 1530 compatible = "st,stm32mp1-adc"; 1531 #io-channel-cells = <1>; 1532 reg = <0x100>; 1533 interrupt-parent = <&adc>; 1534 interrupts = <1>; 1535 dmas = <&dmamux1 10 0x400 0x01>; 1536 dma-names = "rx"; 1537 status = "disabled"; 1538 }; 1539 }; 1540 1541 sdmmc3: mmc@48004000 { 1542 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1543 arm,primecell-periphid = <0x00253180>; 1544 reg = <0x48004000 0x400>; 1545 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1546 interrupt-names = "cmd_irq"; 1547 clocks = <&rcc SDMMC3_K>; 1548 clock-names = "apb_pclk"; 1549 resets = <&rcc SDMMC3_R>; 1550 cap-sd-highspeed; 1551 cap-mmc-highspeed; 1552 max-frequency = <120000000>; 1553 access-controllers = <&etzpc STM32MP1_ETZPC_SDMMC3_ID>; 1554 status = "disabled"; 1555 }; 1556 1557 usbotg_hs: usb-otg@49000000 { 1558 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1559 reg = <0x49000000 0x10000>; 1560 clocks = <&rcc USBO_K>; 1561 clock-names = "otg"; 1562 resets = <&rcc USBO_R>; 1563 reset-names = "dwc2"; 1564 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1565 g-rx-fifo-size = <512>; 1566 g-np-tx-fifo-size = <32>; 1567 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1568 dr_mode = "otg"; 1569 otg-rev = <0x200>; 1570 usb33d-supply = <&usb33>; 1571 access-controllers = <&etzpc STM32MP1_ETZPC_OTG_ID>; 1572 status = "disabled"; 1573 }; 1574 1575 dcmi: dcmi@4c006000 { 1576 compatible = "st,stm32-dcmi"; 1577 reg = <0x4c006000 0x400>; 1578 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1579 resets = <&rcc CAMITF_R>; 1580 clocks = <&rcc DCMI>; 1581 clock-names = "mclk"; 1582 dmas = <&dmamux1 75 0x400 0x01>; 1583 dma-names = "tx"; 1584 access-controllers = <&etzpc STM32MP1_ETZPC_DCMI_ID>; 1585 status = "disabled"; 1586 }; 1587 1588 lptimer2: timer@50021000 { 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 compatible = "st,stm32-lptimer"; 1592 reg = <0x50021000 0x400>; 1593 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1594 clocks = <&rcc LPTIM2_K>; 1595 clock-names = "mux"; 1596 wakeup-source; 1597 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 1598 status = "disabled"; 1599 1600 pwm { 1601 compatible = "st,stm32-pwm-lp"; 1602 #pwm-cells = <3>; 1603 status = "disabled"; 1604 }; 1605 1606 trigger@1 { 1607 compatible = "st,stm32-lptimer-trigger"; 1608 reg = <1>; 1609 status = "disabled"; 1610 }; 1611 1612 counter { 1613 compatible = "st,stm32-lptimer-counter"; 1614 status = "disabled"; 1615 }; 1616 }; 1617 1618 lptimer3: timer@50022000 { 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 compatible = "st,stm32-lptimer"; 1622 reg = <0x50022000 0x400>; 1623 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1624 clocks = <&rcc LPTIM3_K>; 1625 clock-names = "mux"; 1626 wakeup-source; 1627 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 1628 status = "disabled"; 1629 1630 pwm { 1631 compatible = "st,stm32-pwm-lp"; 1632 #pwm-cells = <3>; 1633 status = "disabled"; 1634 }; 1635 1636 trigger@2 { 1637 compatible = "st,stm32-lptimer-trigger"; 1638 reg = <2>; 1639 status = "disabled"; 1640 }; 1641 }; 1642 1643 lptimer4: timer@50023000 { 1644 compatible = "st,stm32-lptimer"; 1645 reg = <0x50023000 0x400>; 1646 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1647 clocks = <&rcc LPTIM4_K>; 1648 clock-names = "mux"; 1649 wakeup-source; 1650 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM4_ID>; 1651 status = "disabled"; 1652 1653 pwm { 1654 compatible = "st,stm32-pwm-lp"; 1655 #pwm-cells = <3>; 1656 status = "disabled"; 1657 }; 1658 }; 1659 1660 lptimer5: timer@50024000 { 1661 compatible = "st,stm32-lptimer"; 1662 reg = <0x50024000 0x400>; 1663 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1664 clocks = <&rcc LPTIM5_K>; 1665 clock-names = "mux"; 1666 wakeup-source; 1667 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM5_ID>; 1668 status = "disabled"; 1669 1670 pwm { 1671 compatible = "st,stm32-pwm-lp"; 1672 #pwm-cells = <3>; 1673 status = "disabled"; 1674 }; 1675 }; 1676 1677 vrefbuf: vrefbuf@50025000 { 1678 compatible = "st,stm32-vrefbuf"; 1679 reg = <0x50025000 0x8>; 1680 regulator-min-microvolt = <1500000>; 1681 regulator-max-microvolt = <2500000>; 1682 clocks = <&rcc VREF>; 1683 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 1684 status = "disabled"; 1685 }; 1686 1687 sai4: sai@50027000 { 1688 compatible = "st,stm32h7-sai"; 1689 #address-cells = <1>; 1690 #size-cells = <1>; 1691 ranges = <0 0x50027000 0x400>; 1692 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1693 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1694 resets = <&rcc SAI4_R>; 1695 access-controllers = <&etzpc STM32MP1_ETZPC_SAI4_ID>; 1696 status = "disabled"; 1697 1698 sai4a: audio-controller@50027004 { 1699 #sound-dai-cells = <0>; 1700 compatible = "st,stm32-sai-sub-a"; 1701 reg = <0x04 0x20>; 1702 clocks = <&rcc SAI4_K>; 1703 clock-names = "sai_ck"; 1704 dmas = <&dmamux1 99 0x400 0x01>; 1705 status = "disabled"; 1706 }; 1707 1708 sai4b: audio-controller@50027024 { 1709 #sound-dai-cells = <0>; 1710 compatible = "st,stm32-sai-sub-b"; 1711 reg = <0x24 0x20>; 1712 clocks = <&rcc SAI4_K>; 1713 clock-names = "sai_ck"; 1714 dmas = <&dmamux1 100 0x400 0x01>; 1715 status = "disabled"; 1716 }; 1717 }; 1718 1719 hash1: hash@54002000 { 1720 compatible = "st,stm32f756-hash"; 1721 reg = <0x54002000 0x400>; 1722 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1723 clocks = <&rcc HASH1>; 1724 resets = <&rcc HASH1_R>; 1725 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1726 dma-names = "in"; 1727 dma-maxburst = <2>; 1728 access-controllers = <&etzpc STM32MP1_ETZPC_HASH1_ID>; 1729 status = "disabled"; 1730 }; 1731 1732 rng1: rng@54003000 { 1733 compatible = "st,stm32-rng"; 1734 reg = <0x54003000 0x400>; 1735 clocks = <&rcc RNG1_K>; 1736 resets = <&rcc RNG1_R>; 1737 access-controllers = <&etzpc STM32MP1_ETZPC_RNG1_ID>; 1738 status = "disabled"; 1739 }; 1740 1741 fmc: memory-controller@58002000 { 1742 #address-cells = <2>; 1743 #size-cells = <1>; 1744 compatible = "st,stm32mp1-fmc2-ebi"; 1745 reg = <0x58002000 0x1000>; 1746 clocks = <&rcc FMC_K>; 1747 resets = <&rcc FMC_R>; 1748 access-controllers = <&etzpc STM32MP1_ETZPC_FMC_ID>; 1749 status = "disabled"; 1750 1751 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1752 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1753 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1754 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1755 <4 0 0x80000000 0x10000000>; /* NAND */ 1756 1757 nand-controller@4,0 { 1758 #address-cells = <1>; 1759 #size-cells = <0>; 1760 compatible = "st,stm32mp1-fmc2-nfc"; 1761 reg = <4 0x00000000 0x1000>, 1762 <4 0x08010000 0x1000>, 1763 <4 0x08020000 0x1000>, 1764 <4 0x01000000 0x1000>, 1765 <4 0x09010000 0x1000>, 1766 <4 0x09020000 0x1000>; 1767 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1768 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1769 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1770 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1771 dma-names = "tx", "rx", "ecc"; 1772 status = "disabled"; 1773 }; 1774 }; 1775 1776 qspi: spi@58003000 { 1777 compatible = "st,stm32f469-qspi"; 1778 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1779 reg-names = "qspi", "qspi_mm"; 1780 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1781 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1782 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1783 dma-names = "tx", "rx"; 1784 clocks = <&rcc QSPI_K>; 1785 resets = <&rcc QSPI_R>; 1786 #address-cells = <1>; 1787 #size-cells = <0>; 1788 access-controllers = <&etzpc STM32MP1_ETZPC_QSPI_ID>; 1789 status = "disabled"; 1790 }; 1791 1792 ethernet0: ethernet@5800a000 { 1793 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1794 reg = <0x5800a000 0x2000>; 1795 reg-names = "stmmaceth"; 1796 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1797 interrupt-names = "macirq"; 1798 clock-names = "stmmaceth", 1799 "mac-clk-tx", 1800 "mac-clk-rx", 1801 "eth-ck", 1802 "ptp_ref", 1803 "ethstp"; 1804 clocks = <&rcc ETHMAC>, 1805 <&rcc ETHTX>, 1806 <&rcc ETHRX>, 1807 <&rcc ETHCK_K>, 1808 <&rcc ETHPTP_K>, 1809 <&rcc ETHSTP>; 1810 st,syscon = <&syscfg 0x4>; 1811 snps,mixed-burst; 1812 snps,pbl = <2>; 1813 snps,en-tx-lpi-clockgating; 1814 snps,axi-config = <&stmmac_axi_config_0>; 1815 snps,tso; 1816 access-controllers = <&etzpc STM32MP1_ETZPC_ETH_ID>; 1817 status = "disabled"; 1818 1819 stmmac_axi_config_0: stmmac-axi-config { 1820 snps,wr_osr_lmt = <0x7>; 1821 snps,rd_osr_lmt = <0x7>; 1822 snps,blen = <0 0 0 0 16 8 4>; 1823 }; 1824 }; 1825 1826 usart1: serial@5c000000 { 1827 compatible = "st,stm32h7-uart"; 1828 reg = <0x5c000000 0x400>; 1829 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1830 clocks = <&rcc USART1_K>; 1831 wakeup-source; 1832 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 1833 status = "disabled"; 1834 }; 1835 1836 spi6: spi@5c001000 { 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 compatible = "st,stm32h7-spi"; 1840 reg = <0x5c001000 0x400>; 1841 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1842 clocks = <&rcc SPI6_K>; 1843 resets = <&rcc SPI6_R>; 1844 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1845 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1846 dma-names = "rx", "tx"; 1847 access-controllers = <&etzpc STM32MP1_ETZPC_SPI6_ID>; 1848 status = "disabled"; 1849 }; 1850 1851 i2c4: i2c@5c002000 { 1852 compatible = "st,stm32mp15-i2c"; 1853 reg = <0x5c002000 0x400>; 1854 interrupt-names = "event", "error"; 1855 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1857 clocks = <&rcc I2C4_K>; 1858 resets = <&rcc I2C4_R>; 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1862 wakeup-source; 1863 i2c-analog-filter; 1864 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 1865 status = "disabled"; 1866 }; 1867 1868 iwdg1: watchdog@5c003000 { 1869 compatible = "st,stm32mp1-iwdg"; 1870 reg = <0x5C003000 0x400>; 1871 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1872 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 1873 clock-names = "pclk", "lsi"; 1874 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 1875 status = "disabled"; 1876 }; 1877 1878 i2c6: i2c@5c009000 { 1879 compatible = "st,stm32mp15-i2c"; 1880 reg = <0x5c009000 0x400>; 1881 interrupt-names = "event", "error"; 1882 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1884 clocks = <&rcc I2C6_K>; 1885 resets = <&rcc I2C6_R>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1889 wakeup-source; 1890 i2c-analog-filter; 1891 access-controllers = <&etzpc STM32MP1_ETZPC_I2C6_ID>; 1892 status = "disabled"; 1893 }; 1894 }; 1895 }; 1896 1897 mlahb: ahb { 1898 compatible = "st,mlahb", "simple-bus"; 1899 #address-cells = <1>; 1900 #size-cells = <1>; 1901 ranges; 1902 dma-ranges = <0x00000000 0x38000000 0x10000>, 1903 <0x10000000 0x10000000 0x60000>, 1904 <0x30000000 0x30000000 0x60000>; 1905 1906 m4_rproc: m4@10000000 { 1907 compatible = "st,stm32mp1-m4"; 1908 reg = <0x10000000 0x40000>, 1909 <0x30000000 0x40000>, 1910 <0x38000000 0x10000>; 1911 resets = <&rcc MCU_R>, <&rcc MCU_HOLD_BOOT_R>; 1912 reset-names = "mcu_rst", "hold_boot"; 1913 st,syscfg-tz = <&rcc 0x000 0x1>; 1914 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1915 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1916 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 1917 status = "disabled"; 1918 }; 1919 }; 1920}; 1921