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Searched refs:u32PNL_XCDeviceBankOffset (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/drv/pnl/include/
H A Dpnl_hwreg_utility2.h2261 INTERFACE MS_U32 u32PNL_XCDeviceBankOffset[PNL_HWREG_MAX_SUPPORT_DEVICE_NUM]; variable
2272 ({if((((u32Reg) & 0xFFFF) >> 8) >= u32PNL_XCDeviceBankOffset[1])\
2278 …RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (u32PNL_XCDeviceBankOffset[u8Id] << 8) )…
2282 ( { ((((u32Reg) & 0xFFFF) >> 8) >= u32PNL_XCDeviceBankOffset[1])\
2284 …: RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (u32PNL_XCDeviceBankOffset[u8Id] << 8) …
2287 ({if((((u32Reg) & 0xFFFF) >> 8) >= u32PNL_XCDeviceBankOffset[1])\
2294 …RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (u32PNL_XCDeviceBankOffset[u8Id] << 8) )…
2295 …RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (u32PNL_XCDeviceBankOffset[u8Id] << 8) +…
2299 ( { ((((u32Reg) & 0xFFFF) >> 8) >= u32PNL_XCDeviceBankOffset[1])\
2301 …F) + (u32PNL_XCDeviceBankOffset[u8Id] << 8) ) << 1 ) | (MS_U32)(RIU_READ_2BYTE( (REG_SCALER_BASE +…
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/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.c1058 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
1059 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
1060 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC1 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.c1058 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
1059 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
1060 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC1 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.c1058 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
1059 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
1060 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC1 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.c1058 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
1059 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
1060 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC1 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.c1940 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
1941 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
1942 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.c1940 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
1941 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
1942 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.c2785 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
2786 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
2787 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.c2785 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
2786 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
2787 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.c3276 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
3277 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
3278 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A DhalPNL.c3660 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
3661 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
3662 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.c4007 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
4008 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
4009 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c4053 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
4054 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
4055 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c4053 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
4054 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
4055 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.c5038 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
5039 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
5040 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.c5068 memset(u32PNL_XCDeviceBankOffset, 0, sizeof(MS_U32)*E_PNL_DEVICE_ID_NUM); in MHal_PNL_Set_Device_Bank_Offset()
5069 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_0] = E_HALPNL_DEVICE0_XC_BANK_OFFSET; // Set SC0 reg ban… in MHal_PNL_Set_Device_Bank_Offset()
5070 …u32PNL_XCDeviceBankOffset[E_PNL_DEVICE_ID_1] = E_HALPNL_DEVICE1_XC_BANK_OFFSET; // Set SC2 reg ban… in MHal_PNL_Set_Device_Bank_Offset()