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Searched refs:SwInt_Stat1_L (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c2694 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_PcrFlt_ClearInt()
2695 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
2700 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_PcrFlt_ClearInt()
2701 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
4648 …REG16_SET(&_RegCtrl->SwInt_Stat1_L, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK… in HAL_TSP_INT_Enable()
4656 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_INT_Disable()
4657 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8))) | in HAL_TSP_INT_Disable()
4666 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_INT_ClrHW()
4667 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()
4676 …status = (MS_U32)(((REG16_R(&_RegCtrl->SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_STAT… in HAL_TSP_INT_GetHW()
H A DregTSP.h1119 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
/utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/
H A DhalTSP.c3049 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L, in HAL_TSP_VQueue_OverflowInt_En()
3050 … SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L)|0xFF00 , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8)); in HAL_TSP_VQueue_OverflowInt_En()
3059 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L, in HAL_TSP_VQueue_OverflowInt_En()
3060 … RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8)); in HAL_TSP_VQueue_OverflowInt_En()
3075 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L, in HAL_TSP_VQueue_Clr_OverflowInt()
3076 … RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L), TSP_HWINT2_VQ_OVERFLOW_STATUS)); in HAL_TSP_VQueue_Clr_OverflowInt()
3111 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_VQ_OVERFLOW_STATUS); in HAL_TSP_VQ_INT_STATUS()
H A DregTSP.h956 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
/utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/
H A DhalTSP.c3064 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L, in HAL_TSP_VQueue_OverflowInt_En()
3065 … SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L)|0xFF00 , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8)); in HAL_TSP_VQueue_OverflowInt_En()
3074 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L, in HAL_TSP_VQueue_OverflowInt_En()
3075 … RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8)); in HAL_TSP_VQueue_OverflowInt_En()
3090 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L, in HAL_TSP_VQueue_Clr_OverflowInt()
3091 … RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L), TSP_HWINT2_VQ_OVERFLOW_STATUS)); in HAL_TSP_VQueue_Clr_OverflowInt()
3126 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_VQ_OVERFLOW_STATUS); in HAL_TSP_VQ_INT_STATUS()
H A DregTSP.h955 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
/utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/
H A DhalTSP.c3053 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L, in HAL_TSP_VQueue_OverflowInt_En()
3054 … SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L)|0xFF00 , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8)); in HAL_TSP_VQueue_OverflowInt_En()
3063 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L, in HAL_TSP_VQueue_OverflowInt_En()
3064 … RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8)); in HAL_TSP_VQueue_OverflowInt_En()
3079 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L, in HAL_TSP_VQueue_Clr_OverflowInt()
3080 … RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L), TSP_HWINT2_VQ_OVERFLOW_STATUS)); in HAL_TSP_VQueue_Clr_OverflowInt()
3115 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_VQ_OVERFLOW_STATUS); in HAL_TSP_VQ_INT_STATUS()
H A DregTSP.h956 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DhalTSP.c3598 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_PcrFlt_ClearInt()
3599 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
3604 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_PcrFlt_ClearInt()
3605 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_PcrFlt_ClearInt()
6071 …REG16_SET(&_RegCtrl->SwInt_Stat1_L, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK… in HAL_TSP_INT_Enable()
6079 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_INT_Disable()
6080 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8))) | in HAL_TSP_INT_Disable()
6089 REG16_W(&_RegCtrl->SwInt_Stat1_L, in HAL_TSP_INT_ClrHW()
6090 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) | in HAL_TSP_INT_ClrHW()
6098 …status |= ((MS_U32)(((REG16_R(&_RegCtrl->SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_ST… in HAL_TSP_INT_GetHW()
H A DregTSP.h1155 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
/utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/
H A DregTSP.h1216 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
H A DhalTSP.c2767 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK); in HAL_TSP_HW_INT2_STATUS()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/
H A DregTSP.h1213 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
H A DhalTSP.c3013 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK); in HAL_TSP_HW_INT2_STATUS()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/
H A DregTSP.h1204 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
H A DhalTSP.c2978 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK); in HAL_TSP_HW_INT2_STATUS()
/utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/
H A DregTSP.h1270 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
H A DhalTSP.c2949 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK); in HAL_TSP_HW_INT2_STATUS()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/
H A DregTSP.h1274 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
H A DhalTSP.c3169 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK); in HAL_TSP_HW_INT2_STATUS()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/
H A DregTSP.h1274 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
H A DhalTSP.c3169 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK); in HAL_TSP_HW_INT2_STATUS()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/
H A DregTSP.h1290 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/
H A DregTSP.h1290 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregTSP.h1157 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c member

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