| /utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tsp/ |
| H A D | halTSP.c | 188 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
867 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
1111 RESET_FLAG1(_HAL_REG32_R(&(_TspCtrl3[0].PIDFLR_PCR[u32EngId])), TSP_PIDFLT_PCR_EN)); in HAL_TSP_PidFlt_HWPcrFlt_Enable()
1370 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_FILEIN_BYTETIMER_ENABLE)); in HAL_TSP_TsDma_SetDelay()
1411 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1556 _HAL_REG32_W(pRegPVREn, RESET_FLAG1(_HAL_REG32_R(pRegPVREn), u32PVRFlag)); in HAL_TSP_PVR_Enable()
1612 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32flag)); in HAL_TSP_PVR_All()
1638 … _HAL_REG32_W(&_TspCtrl[0].reg15b4, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), u32flag)); in HAL_TSP_PVR_BypassHeader_En()
1697 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].CH_BW_CTRL), TSP_CH_BW_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
1738 _HAL_REG16_W(&_TspCtrl5[0].HwCfg0, RESET_FLAG1(_HAL_REG16_R(&_TspCtrl5[0].HwCfg0), u16data)); in HAL_TSP_PVR_WaitFlush()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tsp/ |
| H A D | halTSP.c | 178 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
916 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
1144 RESET_FLAG1(_HAL_REG32_R(&(_TspCtrl3[0].PIDFLR_PCR[u32EngId])), TSP_PIDFLT_PCR_EN)); in HAL_TSP_PidFlt_HWPcrFlt_Enable()
1403 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_FILEIN_BYTETIMER_ENABLE)); in HAL_TSP_TsDma_SetDelay()
1444 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1589 _HAL_REG32_W(pRegPVREn, RESET_FLAG1(_HAL_REG32_R(pRegPVREn), u32PVRFlag)); in HAL_TSP_PVR_Enable()
1644 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32flag)); in HAL_TSP_PVR_All()
1670 … _HAL_REG32_W(&_TspCtrl[0].reg15b4, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), u32flag)); in HAL_TSP_PVR_BypassHeader_En()
1729 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].CH_BW_CTRL), TSP_CH_BW_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
1770 _HAL_REG16_W(&_TspCtrl5[0].HwCfg0, RESET_FLAG1(_HAL_REG16_R(&_TspCtrl5[0].HwCfg0), u16data)); in HAL_TSP_PVR_WaitFlush()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tsp/ |
| H A D | halTSP.c | 187 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
930 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
1158 RESET_FLAG1(_HAL_REG32_R(&(_TspCtrl3[0].PIDFLR_PCR[u32EngId])), TSP_PIDFLT_PCR_EN)); in HAL_TSP_PidFlt_HWPcrFlt_Enable()
1417 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_FILEIN_BYTETIMER_ENABLE)); in HAL_TSP_TsDma_SetDelay()
1458 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1611 _HAL_REG32_W(pRegPVREn, RESET_FLAG1(_HAL_REG32_R(pRegPVREn), u32PVRFlag)); in HAL_TSP_PVR_Enable()
1666 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32flag)); in HAL_TSP_PVR_All()
1692 … _HAL_REG32_W(&_TspCtrl[0].reg15b4, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), u32flag)); in HAL_TSP_PVR_BypassHeader_En()
1751 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].CH_BW_CTRL), TSP_CH_BW_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
1792 _HAL_REG16_W(&_TspCtrl5[0].HwCfg0, RESET_FLAG1(_HAL_REG16_R(&_TspCtrl5[0].HwCfg0), u16data)); in HAL_TSP_PVR_WaitFlush()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mooney/tsp/ |
| H A D | halTSP.c | 170 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
674 …RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld| TSP_match_pid_scr_fi_ld)); in HAL_TSP_Scmb_Detect()
693 RESET_FLAG1(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL), TSP_CA_AVPAUSE)); in HAL_TSP_Set_AVPAUSE()
1015 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1119 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILE_CHECK_WP)); in HAL_TSP_PVR_Enable()
1131 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_ENABLE)); in HAL_TSP_PVR_Enable()
1150 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC)); in HAL_TSP_PVR_All()
1152 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_REG_REC_PID_EN)); in HAL_TSP_PVR_All()
1157 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC)); in HAL_TSP_PVR_All()
1250 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_STR2MI_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/messi/tsp/ |
| H A D | halTSP.c | 169 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
670 …RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld| TSP_match_pid_scr_fi_ld)); in HAL_TSP_Scmb_Detect()
689 RESET_FLAG1(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL), TSP_CA_AVPAUSE)); in HAL_TSP_Set_AVPAUSE()
1011 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1115 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILE_CHECK_WP)); in HAL_TSP_PVR_Enable()
1127 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_ENABLE)); in HAL_TSP_PVR_Enable()
1146 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC)); in HAL_TSP_PVR_All()
1148 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_REG_REC_PID_EN)); in HAL_TSP_PVR_All()
1153 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC)); in HAL_TSP_PVR_All()
1246 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_STR2MI_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mainz/tsp/ |
| H A D | halTSP.c | 170 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
671 …RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld| TSP_match_pid_scr_fi_ld)); in HAL_TSP_Scmb_Detect()
690 RESET_FLAG1(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL), TSP_CA_AVPAUSE)); in HAL_TSP_Set_AVPAUSE()
1012 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1116 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILE_CHECK_WP)); in HAL_TSP_PVR_Enable()
1128 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_ENABLE)); in HAL_TSP_PVR_Enable()
1147 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC)); in HAL_TSP_PVR_All()
1149 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_REG_REC_PID_EN)); in HAL_TSP_PVR_All()
1154 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC)); in HAL_TSP_PVR_All()
1247 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_STR2MI_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tsp/ |
| H A D | halTSP.c | 191 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
936 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
1180 RESET_FLAG1(_HAL_REG32_R(&(_TspCtrl3[0].PIDFLR_PCR[u32EngId])), TSP_PIDFLT_PCR_EN)); in HAL_TSP_PidFlt_HWPcrFlt_Enable()
1439 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_FILEIN_BYTETIMER_ENABLE)); in HAL_TSP_TsDma_SetDelay()
1480 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1633 _HAL_REG32_W(pRegPVREn, RESET_FLAG1(_HAL_REG32_R(pRegPVREn), u32PVRFlag)); in HAL_TSP_PVR_Enable()
1689 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32flag)); in HAL_TSP_PVR_All()
1715 … _HAL_REG32_W(&_TspCtrl[0].reg15b4, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), u32flag)); in HAL_TSP_PVR_BypassHeader_En()
1774 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].CH_BW_CTRL), TSP_CH_BW_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
1815 _HAL_REG16_W(&_TspCtrl5[0].HwCfg0, RESET_FLAG1(_HAL_REG16_R(&_TspCtrl5[0].HwCfg0), u16data)); in HAL_TSP_PVR_WaitFlush()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tsp/ |
| H A D | halTSP.c | 191 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
936 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
1180 RESET_FLAG1(_HAL_REG32_R(&(_TspCtrl3[0].PIDFLR_PCR[u32EngId])), TSP_PIDFLT_PCR_EN)); in HAL_TSP_PidFlt_HWPcrFlt_Enable()
1439 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_FILEIN_BYTETIMER_ENABLE)); in HAL_TSP_TsDma_SetDelay()
1480 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1633 _HAL_REG32_W(pRegPVREn, RESET_FLAG1(_HAL_REG32_R(pRegPVREn), u32PVRFlag)); in HAL_TSP_PVR_Enable()
1689 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32flag)); in HAL_TSP_PVR_All()
1715 … _HAL_REG32_W(&_TspCtrl[0].reg15b4, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), u32flag)); in HAL_TSP_PVR_BypassHeader_En()
1774 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].CH_BW_CTRL), TSP_CH_BW_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
1815 _HAL_REG16_W(&_TspCtrl5[0].HwCfg0, RESET_FLAG1(_HAL_REG16_R(&_TspCtrl5[0].HwCfg0), u16data)); in HAL_TSP_PVR_WaitFlush()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tsp/ |
| H A D | halTSP.c | 191 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
954 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
1198 RESET_FLAG1(_HAL_REG32_R(&(_TspCtrl3[0].PIDFLR_PCR[u32EngId])), TSP_PIDFLT_PCR_EN)); in HAL_TSP_PidFlt_HWPcrFlt_Enable()
1496 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_FILEIN_BYTETIMER_ENABLE)); in HAL_TSP_TsDma_SetDelay()
1537 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1691 _HAL_REG32_W(pRegPVREn, RESET_FLAG1(_HAL_REG32_R(pRegPVREn), u32PVRFlag)); in HAL_TSP_PVR_Enable()
1746 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32flag)); in HAL_TSP_PVR_All()
1772 … _HAL_REG32_W(&_TspCtrl[0].reg15b4, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), u32flag)); in HAL_TSP_PVR_BypassHeader_En()
1831 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].CH_BW_CTRL), TSP_CH_BW_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
1872 _HAL_REG16_W(&_TspCtrl5[0].HwCfg0, RESET_FLAG1(_HAL_REG16_R(&_TspCtrl5[0].HwCfg0), u16data)); in HAL_TSP_PVR_WaitFlush()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tsp/ |
| H A D | halTSP.c | 191 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
954 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
1198 RESET_FLAG1(_HAL_REG32_R(&(_TspCtrl3[0].PIDFLR_PCR[u32EngId])), TSP_PIDFLT_PCR_EN)); in HAL_TSP_PidFlt_HWPcrFlt_Enable()
1457 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_FILEIN_BYTETIMER_ENABLE)); in HAL_TSP_TsDma_SetDelay()
1498 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1652 _HAL_REG32_W(pRegPVREn, RESET_FLAG1(_HAL_REG32_R(pRegPVREn), u32PVRFlag)); in HAL_TSP_PVR_Enable()
1707 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32flag)); in HAL_TSP_PVR_All()
1733 … _HAL_REG32_W(&_TspCtrl[0].reg15b4, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), u32flag)); in HAL_TSP_PVR_BypassHeader_En()
1792 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].CH_BW_CTRL), TSP_CH_BW_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
1833 _HAL_REG16_W(&_TspCtrl5[0].HwCfg0, RESET_FLAG1(_HAL_REG16_R(&_TspCtrl5[0].HwCfg0), u16data)); in HAL_TSP_PVR_WaitFlush()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/ |
| H A D | halTSP.c | 184 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
807 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_OPT_ORACESS_TIMING)); in HAL_TSP_ORAcess_Optimize()
1128 RESET_FLAG1(_HAL_REG32_R(&(_TspCtrl3[0].PIDFLR_PCR[u32EngId])), TSP_PIDFLT_PCR_EN)); in HAL_TSP_PidFlt_HWPcrFlt_Enable()
1376 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_FILEIN_BYTETIMER_ENABLE)); in HAL_TSP_TsDma_SetDelay()
1416 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)); in HAL_TSP_TsDma_Resume()
1559 _HAL_REG32_W(pRegPVREn, RESET_FLAG1(_HAL_REG32_R(pRegPVREn), u32PVRFlag)); in HAL_TSP_PVR_Enable()
1614 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32flag)); in HAL_TSP_PVR_All()
1640 … _HAL_REG32_W(&_TspCtrl[0].reg15b4, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), u32flag)); in HAL_TSP_PVR_BypassHeader_En()
1699 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].CH_BW_CTRL), TSP_CH_BW_WP_LD)); in HAL_TSP_PVR_GetBufWrite()
1735 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32flag)); in HAL_TSP_PVR_WaitFlush()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tso/ |
| H A D | halTSO.c | 162 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
421 …_HAL_REG16_W(&(_TSOCtrl2->TSO_CFG_21), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl2->TSO_CFG_21)), TSO_MMT… in HAL_TSO_Init()
1078 …_HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u1… in HAL_TSO_ReplaceFlt_Enable()
1175 … _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf)); in HAL_TSO_Filein_Enable()
1177 …RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_… in HAL_TSO_Filein_Enable()
1206 …_HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CF… in HAL_TSO_Filein_192Mode_Enable()
1213 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE)); in HAL_TSO_Filein_192Mode_Enable()
1222 … RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE)); in HAL_TSO_Filein_192BlockMode_Enable()
1264 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1279 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_ValidBlock_Count()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tso/ |
| H A D | halTSO.c | 162 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
430 …_HAL_REG16_W(&(_TSOCtrl2->TSO_CFG_21), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl2->TSO_CFG_21)), TSO_MMT… in HAL_TSO_Init()
1103 …_HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u1… in HAL_TSO_ReplaceFlt_Enable()
1200 … _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf)); in HAL_TSO_Filein_Enable()
1202 …RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_… in HAL_TSO_Filein_Enable()
1231 …_HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CF… in HAL_TSO_Filein_192Mode_Enable()
1238 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE)); in HAL_TSO_Filein_192Mode_Enable()
1247 … RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE)); in HAL_TSO_Filein_192BlockMode_Enable()
1289 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1304 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_ValidBlock_Count()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tso/ |
| H A D | halTSO.c | 162 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
430 …_HAL_REG16_W(&(_TSOCtrl2->TSO_CFG_21), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl2->TSO_CFG_21)), TSO_MMT… in HAL_TSO_Init()
1103 …_HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u1… in HAL_TSO_ReplaceFlt_Enable()
1200 … _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf)); in HAL_TSO_Filein_Enable()
1202 …RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_… in HAL_TSO_Filein_Enable()
1231 …_HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CF… in HAL_TSO_Filein_192Mode_Enable()
1238 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE)); in HAL_TSO_Filein_192Mode_Enable()
1247 … RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE)); in HAL_TSO_Filein_192BlockMode_Enable()
1289 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1304 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_ValidBlock_Count()
[all …]
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tso/ |
| H A D | halTSO.c | 162 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
421 …_HAL_REG16_W(&(_TSOCtrl2->TSO_CFG_21), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl2->TSO_CFG_21)), TSO_MMT… in HAL_TSO_Init()
1078 …_HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u1… in HAL_TSO_ReplaceFlt_Enable()
1175 … _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf)); in HAL_TSO_Filein_Enable()
1177 …RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_… in HAL_TSO_Filein_Enable()
1206 …_HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CF… in HAL_TSO_Filein_192Mode_Enable()
1213 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE)); in HAL_TSO_Filein_192Mode_Enable()
1222 … RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE)); in HAL_TSO_Filein_192BlockMode_Enable()
1264 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1279 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_ValidBlock_Count()
[all …]
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tso/ |
| H A D | halTSO.c | 146 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
854 …_HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u1… in HAL_TSO_ReplaceFlt_Enable()
935 … _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf)); in HAL_TSO_Filein_Enable()
937 …RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_… in HAL_TSO_Filein_Enable()
969 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE)); in HAL_TSO_Filein_192Mode_Enable()
978 … RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE)); in HAL_TSO_Filein_192BlockMode_Enable()
1020 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1035 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_ValidBlock_Count()
1054 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_InvalidBlock_Count()
1074 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_OutputPktSize()
[all …]
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/mustang/tso/ |
| H A D | halTSO.c | 160 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
929 …_HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u1… in HAL_TSO_ReplaceFlt_Enable()
995 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), TSO_CFG1_TSO_… in HAL_TSO_Filein_Enable()
997 …RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_… in HAL_TSO_Filein_Enable()
1026 …_HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CF… in HAL_TSO_Filein_192Mode_Enable()
1033 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE)); in HAL_TSO_Filein_192Mode_Enable()
1042 … RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE)); in HAL_TSO_Filein_192BlockMode_Enable()
1074 …_HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), TSO_SW_RSTZ_CMD… in HAL_TSO_CmdQ_Reset()
1090 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_ValidBlock_Count()
1109 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_InvalidBlock_Count()
[all …]
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tso/ |
| H A D | halTSO.c | 146 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
1001 …_HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u1… in HAL_TSO_ReplaceFlt_Enable()
1098 … _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf)); in HAL_TSO_Filein_Enable()
1100 …RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_… in HAL_TSO_Filein_Enable()
1132 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE)); in HAL_TSO_Filein_192Mode_Enable()
1141 … RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE)); in HAL_TSO_Filein_192BlockMode_Enable()
1183 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1198 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_ValidBlock_Count()
1217 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_InvalidBlock_Count()
1237 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_OutputPktSize()
[all …]
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tso/ |
| H A D | halTSO.c | 154 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
1029 …_HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u1… in HAL_TSO_ReplaceFlt_Enable()
1126 … _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf)); in HAL_TSO_Filein_Enable()
1128 …RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_… in HAL_TSO_Filein_Enable()
1160 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE)); in HAL_TSO_Filein_192Mode_Enable()
1169 … RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE)); in HAL_TSO_Filein_192BlockMode_Enable()
1211 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1226 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_ValidBlock_Count()
1245 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_InvalidBlock_Count()
1265 …_HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PA… in HAL_TSO_RW_OutputPktSize()
[all …]
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/ |
| H A D | halNDSRASP.c | 448 …_HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_… in HAL_NDSRASP_Exit()
526 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_RST_WADDR)); in HAL_NDSRASP_Payload_Enable()
540 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_EN)); in HAL_NDSRASP_Payload_Enable()
649 …_HAL_REG16_W((REG16 *)_u32PidfltReg, RESET_FLAG1(_HAL_REG16_R((REG16 *)_u32PidfltReg), RASP_PID_PK… in HAL_NDSRASP_SetCorptFlt()
917 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4) , RASP_TS_STR2MI_WP_LD_DIS)); in HAL_NDSRASP_GetWritePtr()
1034 RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3) , RASP_PAYLD2MIU_LPCR_WT)); in HAL_NDSRASP_SetPayloadTimeStamp()
1432 …RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4), RASP_AUTO_STREAM_47_48)); // '0'… in HAL_NDSRASP_SetStream_47_48()
2052 …_HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_… in HAL_RASP_Close()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/ |
| H A D | halNDSRASP.c | 448 …_HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_… in HAL_NDSRASP_Exit()
526 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_RST_WADDR)); in HAL_NDSRASP_Payload_Enable()
540 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_EN)); in HAL_NDSRASP_Payload_Enable()
649 …_HAL_REG16_W((REG16 *)_u32PidfltReg, RESET_FLAG1(_HAL_REG16_R((REG16 *)_u32PidfltReg), RASP_PID_PK… in HAL_NDSRASP_SetCorptFlt()
917 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4) , RASP_TS_STR2MI_WP_LD_DIS)); in HAL_NDSRASP_GetWritePtr()
1034 RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3) , RASP_PAYLD2MIU_LPCR_WT)); in HAL_NDSRASP_SetPayloadTimeStamp()
1432 …RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4), RASP_AUTO_STREAM_47_48)); // '0'… in HAL_NDSRASP_SetStream_47_48()
2052 …_HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_… in HAL_RASP_Close()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/ |
| H A D | halNDSRASP.c | 448 …_HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_… in HAL_NDSRASP_Exit()
526 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_RST_WADDR)); in HAL_NDSRASP_Payload_Enable()
540 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_EN)); in HAL_NDSRASP_Payload_Enable()
649 …_HAL_REG16_W((REG16 *)_u32PidfltReg, RESET_FLAG1(_HAL_REG16_R((REG16 *)_u32PidfltReg), RASP_PID_PK… in HAL_NDSRASP_SetCorptFlt()
917 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4) , RASP_TS_STR2MI_WP_LD_DIS)); in HAL_NDSRASP_GetWritePtr()
1034 RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3) , RASP_PAYLD2MIU_LPCR_WT)); in HAL_NDSRASP_SetPayloadTimeStamp()
1432 …RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4), RASP_AUTO_STREAM_47_48)); // '0'… in HAL_NDSRASP_SetStream_47_48()
2052 …_HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_… in HAL_RASP_Close()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/ |
| H A D | halNDSRASP.c | 448 …_HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_… in HAL_NDSRASP_Exit()
526 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_RST_WADDR)); in HAL_NDSRASP_Payload_Enable()
540 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_EN)); in HAL_NDSRASP_Payload_Enable()
649 …_HAL_REG16_W((REG16 *)_u32PidfltReg, RESET_FLAG1(_HAL_REG16_R((REG16 *)_u32PidfltReg), RASP_PID_PK… in HAL_NDSRASP_SetCorptFlt()
917 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4) , RASP_TS_STR2MI_WP_LD_DIS)); in HAL_NDSRASP_GetWritePtr()
1034 RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3) , RASP_PAYLD2MIU_LPCR_WT)); in HAL_NDSRASP_SetPayloadTimeStamp()
1432 …RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4), RASP_AUTO_STREAM_47_48)); // '0'… in HAL_NDSRASP_SetStream_47_48()
2052 …_HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_… in HAL_RASP_Close()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/ |
| H A D | halNDSRASP.c | 448 …_HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_… in HAL_NDSRASP_Exit()
526 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_RST_WADDR)); in HAL_NDSRASP_Payload_Enable()
540 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_EN)); in HAL_NDSRASP_Payload_Enable()
649 …_HAL_REG16_W((REG16 *)_u32PidfltReg, RESET_FLAG1(_HAL_REG16_R((REG16 *)_u32PidfltReg), RASP_PID_PK… in HAL_NDSRASP_SetCorptFlt()
917 … RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4) , RASP_TS_STR2MI_WP_LD_DIS)); in HAL_NDSRASP_GetWritePtr()
1034 RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3) , RASP_PAYLD2MIU_LPCR_WT)); in HAL_NDSRASP_SetPayloadTimeStamp()
1432 …RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4), RASP_AUTO_STREAM_47_48)); // '0'… in HAL_NDSRASP_SetStream_47_48()
2052 …_HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_… in HAL_RASP_Close()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/ |
| H A D | halTSO.c | 90 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) macro
95 #define _REG16_CLR(reg, value); _HAL_REG16_W(reg, RESET_FLAG1(_HAL_REG16_R(reg), value));
96 #define _REG32_CLR(reg, value); _HAL_REG32_W(reg, RESET_FLAG1(_HAL_REG32_R(reg), value));
1109 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data)); in HAL_TSO_CmdQ_Reset()
1541 …_HAL_REG16_W(&(_TSOCtrl->TSO_CONFIG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CONFIG1), TSO_CFG1_… in HAL_TSO_RW_OutputPktSize()
1858 _HAL_REG16_W(p16Reg , RESET_FLAG1(_HAL_REG16_R(p16Reg), TSO1_SVQ1_TX_CONFIG_TX_RESET)); in HAL_TSO_SVQ_TX_Reset()
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