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Searched refs:REG_CLKGEN0_TSO_OUT_PHASE (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tso/
H A DhalTSO.c117 #define REG_CLKGEN0_TSO_OUT_PHASE 0x2D macro
679 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
680 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()
687 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MA… in HAL_TSO_TSOOutDiv()
768 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
772 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
775 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
776 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
789 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_Set_PreTsoOutClk()
790 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN_TSO_P_TSO_OUT_MASK) | (u16PreTsoOutSel <… in HAL_TSO_Set_PreTsoOutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tso/
H A DhalTSO.c118 #define REG_CLKGEN0_TSO_OUT_PHASE 0x2D macro
682 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
683 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()
690 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MA… in HAL_TSO_TSOOutDiv()
771 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
775 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
778 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
779 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
792 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_Set_PreTsoOutClk()
793 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN_TSO_P_TSO_OUT_MASK) | (u16PreTsoOutSel <… in HAL_TSO_Set_PreTsoOutClk()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tso/
H A DhalTSO.c117 #define REG_CLKGEN0_TSO_OUT_PHASE 0x2D macro
678 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
679 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()
686 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MA… in HAL_TSO_TSOOutDiv()
767 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
771 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
774 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
775 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tso/
H A DhalTSO.c117 #define REG_CLKGEN0_TSO_OUT_PHASE 0x2D macro
678 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
679 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()
686 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MA… in HAL_TSO_TSOOutDiv()
767 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
771 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
774 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
775 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tso/
H A DhalTSO.c117 #define REG_CLKGEN0_TSO_OUT_PHASE 0x2D macro
681 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
682 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDiv… in HAL_TSO_TSOOutDiv()
689 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MA… in HAL_TSO_TSOOutDiv()
770 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
774 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
777 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
778 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/tso/
H A DhalTSO.c182 #define REG_CLKGEN0_TSO_OUT_PHASE 0x7CUL macro
952 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
955 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
993 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
994 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()
999 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()
2089 _u16TSOTopReg[0][1] = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE); in HAL_TSO_SaveRegs()
2115 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = _u16TSOTopReg[0][1]; in HAL_TSO_RestoreRegs()
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/tso/
H A DhalTSO.c183 #define REG_CLKGEN0_TSO_OUT_PHASE 0x7CUL macro
977 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
980 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
1018 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
1019 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()
1024 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()
2114 _u16TSOTopReg[0][1] = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE); in HAL_TSO_SaveRegs()
2140 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = _u16TSOTopReg[0][1]; in HAL_TSO_RestoreRegs()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/tso/
H A DhalTSO.c183 #define REG_CLKGEN0_TSO_OUT_PHASE 0x7CUL macro
977 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
980 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
1018 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
1019 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()
1024 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()
2114 _u16TSOTopReg[0][1] = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE); in HAL_TSO_SaveRegs()
2140 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = _u16TSOTopReg[0][1]; in HAL_TSO_RestoreRegs()
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/tso/
H A DhalTSO.c182 #define REG_CLKGEN0_TSO_OUT_PHASE 0x7CUL macro
952 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
955 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
993 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
994 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()
999 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()
2089 _u16TSOTopReg[0][1] = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE); in HAL_TSO_SaveRegs()
2115 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = _u16TSOTopReg[0][1]; in HAL_TSO_RestoreRegs()
/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/tso/
H A DhalTSO.c167 #define REG_CLKGEN0_TSO_OUT_PHASE 0x7CUL macro
874 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
877 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
915 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
916 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()
921 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/tso/
H A DhalTSO.c175 #define REG_CLKGEN0_TSO_OUT_PHASE 0x7CUL macro
902 … u16value = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_PH_TUN_NUM_MASK) in HAL_TSO_Set_TSOOut_Phase_Tune()
905 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = u16value; in HAL_TSO_Set_TSOOut_Phase_Tune()
943 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) = in HAL_TSO_TSOOutDiv()
944 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & ~REG_CLKGEN0_TSO_OUT_DIVNUM_MASK) | (*pu16ClkOutDivN… in HAL_TSO_TSOOutDiv()
949 … *pu16ClkOutDivNum = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_PHASE) & REG_CLKGEN0_TSO_OUT_DIVNUM_MASK; in HAL_TSO_TSOOutDiv()