Searched refs:REG_CLKGEN0_TSO_OUT_CLK (Results 1 – 11 of 11) sorted by relevance
187 #define REG_CLKGEN0_TSO_OUT_CLK 0x7DUL macro541 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()548 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()948 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()956 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()971 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = in HAL_TSO_PreTsoOutClk()972 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) | (*pu16PreTsoOutSe… in HAL_TSO_PreTsoOutClk()976 …*pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) … in HAL_TSO_PreTsoOutClk()990 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = in HAL_TSO_TSOOutDiv()991 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()[all …]
188 #define REG_CLKGEN0_TSO_OUT_CLK 0x7DUL macro550 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()557 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()973 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()981 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()996 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = in HAL_TSO_PreTsoOutClk()997 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) | (*pu16PreTsoOutSe… in HAL_TSO_PreTsoOutClk()1001 …*pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) … in HAL_TSO_PreTsoOutClk()1015 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = in HAL_TSO_TSOOutDiv()1016 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()[all …]
180 #define REG_CLKGEN0_TSO_OUT_CLK 0x7DUL macro482 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()489 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()898 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()906 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()921 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = in HAL_TSO_PreTsoOutClk()922 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) | (*pu16PreTsoOutSe… in HAL_TSO_PreTsoOutClk()926 …*pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) … in HAL_TSO_PreTsoOutClk()940 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = in HAL_TSO_TSOOutDiv()941 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()[all …]
172 #define REG_CLKGEN0_TSO_OUT_CLK 0x7DUL macro870 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()878 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_PHASE_TUN_ENABLE; in HAL_TSO_Set_TSOOut_Phase_Tune()893 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = in HAL_TSO_PreTsoOutClk()894 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) | (*pu16PreTsoOutSe… in HAL_TSO_PreTsoOutClk()898 …*pu16PreTsoOutSel = (TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_PRE_CLK_MASK) … in HAL_TSO_PreTsoOutClk()912 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = in HAL_TSO_TSOOutDiv()913 …(TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | (*pu16ClkOutDivSr… in HAL_TSO_TSOOutDiv()920 …*pu16ClkOutDivSrcSel = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK; in HAL_TSO_TSOOutDiv()929 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_OutClk()[all …]
132 #define REG_CLKGEN0_TSO_OUT_CLK 0x2F macro788 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_OutClk()810 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk; in HAL_TSO_OutClk()2089 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()2105 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()
132 #define REG_CLKGEN0_TSO_OUT_CLK 0x2F macro791 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_OutClk()813 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk; in HAL_TSO_OutClk()2154 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()2170 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()
132 #define REG_CLKGEN0_TSO_OUT_CLK 0x2F macro797 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_OutClk()819 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk; in HAL_TSO_OutClk()2160 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()2176 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()
133 #define REG_CLKGEN0_TSO_OUT_CLK 0x2F macro800 MS_U16 u16Clk = TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_OutClk()822 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) = u16Clk; in HAL_TSO_OutClk()2152 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) &= ~REG_CLKGEN0_TSO_OUT_CLK_MASK; in HAL_TSO_PowerCtrl()2168 TSO_CLKGEN0_REG(REG_CLKGEN0_TSO_OUT_CLK) |= REG_CLKGEN0_TSO_OUT_CLK_DISABLE; in HAL_TSO_PowerCtrl()