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Searched refs:MIU2_REG_BASE (Results 1 – 25 of 45) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/miu/hal/macan/miu/
H A DregMIU.h119 #define MIU2_REG_BASE (0x62000UL) macro
216 #define MIU2_PROTECT_EN (MIU2_REG_BASE+0xD2)
217 #define MIU2_PROTECT_DDR_SIZE (MIU2_REG_BASE+0xD3)
218 #define MIU2_PROTECT0_ID0 (MIU2_REG_BASE+0x2E)
219 #define MIU2_BW_REQUEST (MIU2_REG_BASE+0x1A)
220 #define MIU2_BW_RESULT (MIU2_REG_BASE+0x1C)
221 #define MIU2_PROTECT0_ID_ENABLE (MIU2_REG_BASE+0x20)
222 #define MIU2_PROTECT1_ID_ENABLE (MIU2_REG_BASE+0x22)
223 #define MIU2_PROTECT2_ID_ENABLE (MIU2_REG_BASE+0x24)
224 #define MIU2_PROTECT3_ID_ENABLE (MIU2_REG_BASE+0x26)
[all …]
H A DhalMIU.c1084 u32Reg = MIU2_REG_BASE; in HAL_MIU_Protect()
1214 u32Reg = MIU2_REG_BASE; in HAL_MIU_GetProtectInfo()
1389 u32Reg += MIU2_REG_BASE; in HAL_MIU_MaskReq()
1431 u32Reg += MIU2_REG_BASE; in HAL_MIU_UnMaskReq()
1467 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1481 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1495 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1509 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1523 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1760 u32RegAddr += MIU2_REG_BASE; in HAL_MIU_SetGroupPriority()
[all …]
/utopia/UTPA2-700.0.x/modules/miu/hal/messi/miu/
H A DregMIU.h94 #define MIU2_REG_BASE (0x62000UL) macro
178 #define MIU2_PROTECT_EN (MIU2_REG_BASE + 0xD2)
179 #define MIU2_PROTECT_DDR_SIZE (MIU2_REG_BASE + 0xD3)
180 #define MIU2_PROTECT0_ID0 (MIU2_REG_BASE + 0x2E)
181 #define MIU2_BW_REQUEST (MIU2_REG_BASE + 0x1A)
182 #define MIU2_BW_RESULT (MIU2_REG_BASE + 0x1C)
183 #define MIU2_PROTECT0_ID_ENABLE (MIU2_REG_BASE + 0x20)
184 #define MIU2_PROTECT1_ID_ENABLE (MIU2_REG_BASE + 0x22)
185 #define MIU2_PROTECT2_ID_ENABLE (MIU2_REG_BASE + 0x24)
186 #define MIU2_PROTECT3_ID_ENABLE (MIU2_REG_BASE + 0x26)
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H A DhalMIU.c1169 u32Reg = MIU2_REG_BASE; in HAL_MIU_Protect()
1299 u32Reg = MIU2_REG_BASE; in HAL_MIU_GetProtectInfo()
1514 u32Reg += MIU2_REG_BASE; in HAL_MIU_MaskReq()
1587 u32Reg += MIU2_REG_BASE; in HAL_MIU_UnMaskReq()
1624 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1638 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1652 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1666 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1680 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1917 u32RegAddr += MIU2_REG_BASE; in HAL_MIU_SetGroupPriority()
[all …]
/utopia/UTPA2-700.0.x/modules/miu/hal/mooney/miu/
H A DregMIU.h94 #define MIU2_REG_BASE (0x62000UL) macro
178 #define MIU2_PROTECT_EN (MIU2_REG_BASE + 0xD2)
179 #define MIU2_PROTECT_DDR_SIZE (MIU2_REG_BASE + 0xD3)
180 #define MIU2_PROTECT0_ID0 (MIU2_REG_BASE + 0x2E)
181 #define MIU2_BW_REQUEST (MIU2_REG_BASE + 0x1A)
182 #define MIU2_BW_RESULT (MIU2_REG_BASE + 0x1C)
183 #define MIU2_PROTECT0_ID_ENABLE (MIU2_REG_BASE + 0x20)
184 #define MIU2_PROTECT1_ID_ENABLE (MIU2_REG_BASE + 0x22)
185 #define MIU2_PROTECT2_ID_ENABLE (MIU2_REG_BASE + 0x24)
186 #define MIU2_PROTECT3_ID_ENABLE (MIU2_REG_BASE + 0x26)
[all …]
H A DhalMIU.c1128 u32Reg = MIU2_REG_BASE; in HAL_MIU_Protect()
1258 u32Reg = MIU2_REG_BASE; in HAL_MIU_GetProtectInfo()
1473 u32Reg += MIU2_REG_BASE; in HAL_MIU_MaskReq()
1546 u32Reg += MIU2_REG_BASE; in HAL_MIU_UnMaskReq()
1583 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1597 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1611 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1625 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1639 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1876 u32RegAddr += MIU2_REG_BASE; in HAL_MIU_SetGroupPriority()
[all …]
/utopia/UTPA2-700.0.x/modules/miu/hal/mainz/miu/
H A DregMIU.h94 #define MIU2_REG_BASE (0x62000UL) macro
178 #define MIU2_PROTECT_EN (MIU2_REG_BASE + 0xD2)
179 #define MIU2_PROTECT_DDR_SIZE (MIU2_REG_BASE + 0xD3)
180 #define MIU2_PROTECT0_ID0 (MIU2_REG_BASE + 0x2E)
181 #define MIU2_BW_REQUEST (MIU2_REG_BASE + 0x1A)
182 #define MIU2_BW_RESULT (MIU2_REG_BASE + 0x1C)
183 #define MIU2_PROTECT0_ID_ENABLE (MIU2_REG_BASE + 0x20)
184 #define MIU2_PROTECT1_ID_ENABLE (MIU2_REG_BASE + 0x22)
185 #define MIU2_PROTECT2_ID_ENABLE (MIU2_REG_BASE + 0x24)
186 #define MIU2_PROTECT3_ID_ENABLE (MIU2_REG_BASE + 0x26)
[all …]
H A DhalMIU.c1169 u32Reg = MIU2_REG_BASE; in HAL_MIU_Protect()
1299 u32Reg = MIU2_REG_BASE; in HAL_MIU_GetProtectInfo()
1514 u32Reg += MIU2_REG_BASE; in HAL_MIU_MaskReq()
1587 u32Reg += MIU2_REG_BASE; in HAL_MIU_UnMaskReq()
1624 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1638 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1652 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1666 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1680 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1917 u32RegAddr += MIU2_REG_BASE; in HAL_MIU_SetGroupPriority()
[all …]
/utopia/UTPA2-700.0.x/modules/miu/hal/manhattan/miu/
H A DregMIU.h119 #define MIU2_REG_BASE (0x62000UL) macro
202 #define MIU2_PROTECT_EN (MIU2_REG_BASE+0xD2)
203 #define MIU2_PROTECT_DDR_SIZE (MIU2_REG_BASE+0xD3)
204 #define MIU2_PROTECT0_ID0 (MIU2_REG_BASE+0x2E)
205 #define MIU2_BW_REQUEST (MIU2_REG_BASE+0x1A)
206 #define MIU2_BW_RESULT (MIU2_REG_BASE+0x1C)
207 #define MIU2_PROTECT0_ID_ENABLE (MIU2_REG_BASE+0x20)
208 #define MIU2_PROTECT1_ID_ENABLE (MIU2_REG_BASE+0x22)
209 #define MIU2_PROTECT2_ID_ENABLE (MIU2_REG_BASE+0x24)
210 #define MIU2_PROTECT3_ID_ENABLE (MIU2_REG_BASE+0x26)
[all …]
H A DhalMIU.c1194 u32Reg = MIU2_REG_BASE; in HAL_MIU_Protect()
1350 u32Reg = MIU2_REG_BASE; in HAL_MIU_GetProtectInfo()
1525 u32Reg += MIU2_REG_BASE; in HAL_MIU_MaskReq()
1567 u32Reg += MIU2_REG_BASE; in HAL_MIU_UnMaskReq()
1603 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1617 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1631 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1645 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1659 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1896 u32RegAddr += MIU2_REG_BASE; in HAL_MIU_SetGroupPriority()
[all …]
/utopia/UTPA2-700.0.x/modules/miu/hal/M7821/miu/
H A DregMIU.h119 #define MIU2_REG_BASE (0x62000UL) macro
214 #define MIU2_PROTECT_EN (MIU2_REG_BASE+0xD2)
215 #define MIU2_PROTECT_DDR_SIZE (MIU2_REG_BASE+0xD3)
216 #define MIU2_PROTECT0_ID0 (MIU2_REG_BASE+0x2E)
217 #define MIU2_BW_REQUEST (MIU2_REG_BASE+0x1A)
218 #define MIU2_BW_RESULT (MIU2_REG_BASE+0x1C)
219 #define MIU2_PROTECT0_ID_ENABLE (MIU2_REG_BASE+0x20)
220 #define MIU2_PROTECT1_ID_ENABLE (MIU2_REG_BASE+0x22)
221 #define MIU2_PROTECT2_ID_ENABLE (MIU2_REG_BASE+0x24)
222 #define MIU2_PROTECT3_ID_ENABLE (MIU2_REG_BASE+0x26)
[all …]
H A DhalMIU.c1277 u32Reg = MIU2_REG_BASE; in HAL_MIU_Protect()
1433 u32Reg = MIU2_REG_BASE; in HAL_MIU_GetProtectInfo()
1610 …32RegBase = (u8Miu == E_MIU_0 ? MIU_REG_BASE : (u8Miu == E_MIU_1 ? MIU1_REG_BASE : MIU2_REG_BASE)); in HAL_MIU_MaskReq()
1662 …32RegBase = (u8Miu == E_MIU_0 ? MIU_REG_BASE : (u8Miu == E_MIU_1 ? MIU1_REG_BASE : MIU2_REG_BASE)); in HAL_MIU_UnMaskReq()
1740 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(u32IdGroup); in HAL_MIU_SelMIU()
2001 u32RegAddr += MIU2_REG_BASE; in HAL_MIU_SetGroupPriority()
2046 u32Reg += MIU2_REG_BASE; in HAL_MIU_SetHPriorityMask()
/utopia/UTPA2-700.0.x/modules/miu/hal/maserati/miu/
H A DregMIU.h119 #define MIU2_REG_BASE (0x62000UL) macro
214 #define MIU2_PROTECT_EN (MIU2_REG_BASE+0xD2)
215 #define MIU2_PROTECT_DDR_SIZE (MIU2_REG_BASE+0xD3)
216 #define MIU2_PROTECT0_ID0 (MIU2_REG_BASE+0x2E)
217 #define MIU2_BW_REQUEST (MIU2_REG_BASE+0x1A)
218 #define MIU2_BW_RESULT (MIU2_REG_BASE+0x1C)
219 #define MIU2_PROTECT0_ID_ENABLE (MIU2_REG_BASE+0x20)
220 #define MIU2_PROTECT1_ID_ENABLE (MIU2_REG_BASE+0x22)
221 #define MIU2_PROTECT2_ID_ENABLE (MIU2_REG_BASE+0x24)
222 #define MIU2_PROTECT3_ID_ENABLE (MIU2_REG_BASE+0x26)
[all …]
H A DhalMIU.c1271 u32Reg = MIU2_REG_BASE; in HAL_MIU_Protect()
1427 u32Reg = MIU2_REG_BASE; in HAL_MIU_GetProtectInfo()
1604 …e = (u8Miu == E_MIU_0 ? MIU_REG_BASE : (u8Miu == E_MIU_1 ? MIU1_REG_BASE : MIU2_REG_BASE)); in HAL_MIU_MaskReq()
1656 …e = (u8Miu == E_MIU_0 ? MIU_REG_BASE : (u8Miu == E_MIU_1 ? MIU1_REG_BASE : MIU2_REG_BASE)); in HAL_MIU_UnMaskReq()
1734 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(u32IdGroup); in HAL_MIU_SelMIU()
1995 u32RegAddr += MIU2_REG_BASE; in HAL_MIU_SetGroupPriority()
2040 u32Reg += MIU2_REG_BASE; in HAL_MIU_SetHPriorityMask()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/mvd_v3/
H A DregMVD_EX.h115 #define MIU2_REG_BASE 0x62000UL macro
153 #define MIU2_RQ0_MASK_L (MIU2_REG_BASE + 0x23*2)
154 #define MIU2_RQ0_MASK_H (MIU2_REG_BASE + 0x23*2 +1)
155 #define MIU2_RQ1_MASK_L (MIU2_REG_BASE + 0x33*2)
156 #define MIU2_RQ1_MASK_H (MIU2_REG_BASE + 0x33*2 +1)
157 #define MIU2_RQ2_MASK_L (MIU2_REG_BASE + 0x43*2)
158 #define MIU2_RQ2_MASK_H (MIU2_REG_BASE + 0x43*2 +1)
159 #define MIU2_RQ3_MASK_L (MIU2_REG_BASE + 0x53*2)
160 #define MIU2_RQ3_MASK_H (MIU2_REG_BASE + 0x53*2 +1)
164 #define MIU2_SEL0_L (MIU2_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/mvd_v3/
H A DregMVD_EX.h115 #define MIU2_REG_BASE 0x62000UL macro
153 #define MIU2_RQ0_MASK_L (MIU2_REG_BASE + 0x23*2)
154 #define MIU2_RQ0_MASK_H (MIU2_REG_BASE + 0x23*2 +1)
155 #define MIU2_RQ1_MASK_L (MIU2_REG_BASE + 0x33*2)
156 #define MIU2_RQ1_MASK_H (MIU2_REG_BASE + 0x33*2 +1)
157 #define MIU2_RQ2_MASK_L (MIU2_REG_BASE + 0x43*2)
158 #define MIU2_RQ2_MASK_H (MIU2_REG_BASE + 0x43*2 +1)
159 #define MIU2_RQ3_MASK_L (MIU2_REG_BASE + 0x53*2)
160 #define MIU2_RQ3_MASK_H (MIU2_REG_BASE + 0x53*2 +1)
164 #define MIU2_SEL0_L (MIU2_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/mvd_v3/
H A DregMVD_EX.h115 #define MIU2_REG_BASE 0x62000UL macro
153 #define MIU2_RQ0_MASK_L (MIU2_REG_BASE + 0x23*2)
154 #define MIU2_RQ0_MASK_H (MIU2_REG_BASE + 0x23*2 +1)
155 #define MIU2_RQ1_MASK_L (MIU2_REG_BASE + 0x33*2)
156 #define MIU2_RQ1_MASK_H (MIU2_REG_BASE + 0x33*2 +1)
157 #define MIU2_RQ2_MASK_L (MIU2_REG_BASE + 0x43*2)
158 #define MIU2_RQ2_MASK_H (MIU2_REG_BASE + 0x43*2 +1)
159 #define MIU2_RQ3_MASK_L (MIU2_REG_BASE + 0x53*2)
160 #define MIU2_RQ3_MASK_H (MIU2_REG_BASE + 0x53*2 +1)
164 #define MIU2_SEL0_L (MIU2_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/mvd_v3/
H A DregMVD_EX.h115 #define MIU2_REG_BASE 0x62000UL macro
153 #define MIU2_RQ0_MASK_L (MIU2_REG_BASE + 0x23*2)
154 #define MIU2_RQ0_MASK_H (MIU2_REG_BASE + 0x23*2 +1)
155 #define MIU2_RQ1_MASK_L (MIU2_REG_BASE + 0x33*2)
156 #define MIU2_RQ1_MASK_H (MIU2_REG_BASE + 0x33*2 +1)
157 #define MIU2_RQ2_MASK_L (MIU2_REG_BASE + 0x43*2)
158 #define MIU2_RQ2_MASK_H (MIU2_REG_BASE + 0x43*2 +1)
159 #define MIU2_RQ3_MASK_L (MIU2_REG_BASE + 0x53*2)
160 #define MIU2_RQ3_MASK_H (MIU2_REG_BASE + 0x53*2 +1)
164 #define MIU2_SEL0_L (MIU2_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/mvd_v3/
H A DregMVD_EX.h115 #define MIU2_REG_BASE 0x62000UL macro
153 #define MIU2_RQ0_MASK_L (MIU2_REG_BASE + 0x23*2)
154 #define MIU2_RQ0_MASK_H (MIU2_REG_BASE + 0x23*2 +1)
155 #define MIU2_RQ1_MASK_L (MIU2_REG_BASE + 0x33*2)
156 #define MIU2_RQ1_MASK_H (MIU2_REG_BASE + 0x33*2 +1)
157 #define MIU2_RQ2_MASK_L (MIU2_REG_BASE + 0x43*2)
158 #define MIU2_RQ2_MASK_H (MIU2_REG_BASE + 0x43*2 +1)
159 #define MIU2_RQ3_MASK_L (MIU2_REG_BASE + 0x53*2)
160 #define MIU2_RQ3_MASK_H (MIU2_REG_BASE + 0x53*2 +1)
164 #define MIU2_SEL0_L (MIU2_REG_BASE + 0xF0)
[all …]
/utopia/UTPA2-700.0.x/modules/graphic/hal/mooney/gop/
H A DhalGOP.c642 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Read16Reg()
644 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Read16Reg()
730 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Write16Reg()
732 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Write16Reg()
2461 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_CMDQ_WriteCommand()
2463 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_CMDQ_WriteCommand()
/utopia/UTPA2-700.0.x/modules/graphic/hal/manhattan/gop/
H A DhalGOP.c688 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Read16Reg()
690 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Read16Reg()
776 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Write16Reg()
778 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Write16Reg()
2883 case (MIU2_REG_BASE & 0xFF00):
2885 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
/utopia/UTPA2-700.0.x/modules/graphic/hal/macan/gop/
H A DhalGOP.c719 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Read16Reg()
721 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Read16Reg()
807 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Write16Reg()
809 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Write16Reg()
3011 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_CMDQ_WriteCommand()
3013 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_CMDQ_WriteCommand()
/utopia/UTPA2-700.0.x/modules/graphic/hal/kastor/gop/
H A DhalGOP.c762 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Read16Reg()
764 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Read16Reg()
851 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Write16Reg()
853 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Write16Reg()
3227 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_CMDQ_WriteCommand()
3229 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_CMDQ_WriteCommand()
/utopia/UTPA2-700.0.x/modules/graphic/hal/curry/gop/
H A DhalGOP.c774 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Read16Reg()
776 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Read16Reg()
863 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Write16Reg()
865 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Write16Reg()
3463 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_CMDQ_WriteCommand()
3465 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_CMDQ_WriteCommand()
/utopia/UTPA2-700.0.x/modules/graphic/hal/kano/gop/
H A DhalGOP.c765 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Read16Reg()
767 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Read16Reg()
854 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_Write16Reg()
856 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_Write16Reg()
3538 case (MIU2_REG_BASE & 0xFF00): in HAL_GOP_CMDQ_WriteCommand()
3540 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset in HAL_GOP_CMDQ_WriteCommand()

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