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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regMIU.h 98 /// @brief MIU Control Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_MIU_H_ 103 #define _REG_MIU_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 #define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) 115 #define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) 116 117 #define MIU_REG_BASE (0x1200UL) 118 #define MIU1_REG_BASE (0x0600UL) 119 #define MIU2_REG_BASE (0x62000UL) 120 #define MIU3_REG_BASE (0x62400UL) 121 #define PM_REG_BASE (0x1E00UL) 122 #define MIU_ATOP_BASE (0x10D00UL) 123 #define MIU1_ATOP_BASE (0x61600UL) 124 #define MIU2_ATOP_BASE (0x62100UL) 125 #define MIU3_ATOP_BASE (0x62500UL) 126 #define CHIP_TOP_BASE (0x1E00UL) 127 #define MIU_ARB_REG_BASE (0x61500UL) 128 #define MIU1_ARB_REG_BASE (0x62200UL) 129 #define MIU2_ARB_REG_BASE (0x62300UL) 130 #define MIU_ARBB_REG_BASE (0x52000UL) 131 #define MIU1_ARBB_REG_BASE (0x52100UL) 132 #define MIU2_ARBB_REG_BASE (0x52200UL) 133 134 #define PM_CHIP_REVISION (PM_REG_BASE+0x03) // 0x1E03 135 #define DDR_FREQ_SET_0 (MIU_REG_BASE+0x20) // 0x1220 136 #define DDR_FREQ_SET_1 (MIU_REG_BASE+0x21) //0x1221 137 #define DDR_FREQ_DIV_1 (MIU_REG_BASE+0x25) //0x1225 138 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226 139 #define DDR_FREQ_LOOP_DIV_2 (MIU_REG_BASE+0x27) //0x1227 140 #define DDR_CLK_SELECT (MIU_REG_BASE+0x3e) //0x123E 141 #define DDR_FREQ_STATUS (MIU_REG_BASE+0x3f) //0x123F 142 143 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46) 144 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47) 145 #define MIU_RQ1L_MASK (MIU_REG_BASE+0x66) 146 #define MIU_RQ1H_MASK (MIU_REG_BASE+0x67) 147 #define MIU_RQ2L_MASK (MIU_REG_BASE+0x86) 148 #define MIU_RQ2H_MASK (MIU_REG_BASE+0x87) 149 #define REG_MIU_RQX_MASK(x) (0x46+0x20*x) 150 #define REG_MIU_ARB_RQX_MASK(x) (0x0+0x20*x) 151 #define REG_MIU_ARBB_RQX_MASK(x) (0x0+0x20*x) 152 #define REG_MIU_RQX_HPMASK(x) (0x48+0x20*x) 153 154 #define MIU_PROTECT_EN (MIU_REG_BASE+0xD2) 155 #define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE+0xD3) 156 #define MIU_PROTECT_DDR_SIZE_MASK BITS_RANGE(11:8) 157 #define MIU_PROTECT_DDR_32MB (0x50) 158 #define MIU_PROTECT_DDR_64MB (0x60) 159 #define MIU_PROTECT_DDR_128MB (0x70) 160 #define MIU_PROTECT_DDR_256MB (0x80) 161 #define MIU_PROTECT_DDR_512MB (0x90) 162 #define MIU_PROTECT_DDR_1024MB (0xA0) 163 #define MIU_PROTECT_DDR_2048MB (0xB0) 164 #define MIU_PROTECT_DDR_4096MB (0xC0) 165 #define MIU_PROTECT_DDR_8192MB (0xD0) 166 167 168 #define MIU_PROTECT0_ID0 (MIU_REG_BASE+0x2E) 169 #define MIU_BW_REQUEST (MIU_REG_BASE+0x1A) 170 #define MIU_BW_RESULT (MIU_REG_BASE+0x1C) 171 #define MIU_PROTECT0_ID_ENABLE (MIU_REG_BASE+0x20) 172 #define MIU_PROTECT1_ID_ENABLE (MIU_REG_BASE+0x22) 173 #define MIU_PROTECT2_ID_ENABLE (MIU_REG_BASE+0x24) 174 #define MIU_PROTECT3_ID_ENABLE (MIU_REG_BASE+0x26) 175 #define MIU_PROTECT0_MSB (MIU_REG_BASE+0xD0) 176 #define MIU_PROTECT0_START (MIU_REG_BASE+0xC0) 177 #define MIU_PROTECT1_START (MIU_REG_BASE+0xC4) 178 #define MIU_PROTECT2_START (MIU_REG_BASE+0xC8) 179 #define MIU_PROTECT3_START (MIU_REG_BASE+0xCC) 180 #define REG_MIU_PROTECT_LOADDR (0x6D << 1) //0xDE 181 #define REG_MIU_PROTECT_HIADDR (0x6E << 1) //0xDE 182 #define REG_MIU_GROUP_PRIORITY (0x7F << 1) 183 #define REG_MIU_PROTECT_STATUS (0x6F << 1) //0xDE 184 185 // MIU selection registers 186 #define REG_MIU_SEL0 (MIU_REG_BASE+0xf0) //0x12F0 187 #define REG_MIU_SEL1 (MIU_REG_BASE+0xf2) //0x12F1 188 #define REG_MIU_SEL2 (MIU_REG_BASE+0xf4) //0x12F2 189 #define REG_MIU_SEL3 (MIU_REG_BASE+0xf6) //0x12F3 190 #define REG_MIU_SELX(x) (0xF0+x*2) 191 192 #define REG_MIU_DDR_STATUS (MIU_ARB_REG_BASE+0x66) 193 194 //MIU1 195 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2) 196 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3) 197 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E) 198 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A) 199 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C) 200 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20) 201 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22) 202 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24) 203 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26) 204 #define MIU1_PROTECT0_MSB (MIU1_REG_BASE+0xD0) 205 #define MIU1_PROTECT0_START (MIU1_REG_BASE+0xC0) 206 #define MIU1_PROTECT1_START (MIU1_REG_BASE+0xC4) 207 #define MIU1_PROTECT2_START (MIU1_REG_BASE+0xC8) 208 #define MIU1_PROTECT3_START (MIU1_REG_BASE+0xCC) 209 210 211 #define REG_MIU1_DDR_STATUS (MIU1_ARB_REG_BASE+0x66) 212 213 //MIU2 214 #define MIU2_PROTECT_EN (MIU2_REG_BASE+0xD2) 215 #define MIU2_PROTECT_DDR_SIZE (MIU2_REG_BASE+0xD3) 216 #define MIU2_PROTECT0_ID0 (MIU2_REG_BASE+0x2E) 217 #define MIU2_BW_REQUEST (MIU2_REG_BASE+0x1A) 218 #define MIU2_BW_RESULT (MIU2_REG_BASE+0x1C) 219 #define MIU2_PROTECT0_ID_ENABLE (MIU2_REG_BASE+0x20) 220 #define MIU2_PROTECT1_ID_ENABLE (MIU2_REG_BASE+0x22) 221 #define MIU2_PROTECT2_ID_ENABLE (MIU2_REG_BASE+0x24) 222 #define MIU2_PROTECT3_ID_ENABLE (MIU2_REG_BASE+0x26) 223 #define MIU2_PROTECT0_MSB (MIU2_REG_BASE+0xD0) 224 #define MIU2_PROTECT0_START (MIU2_REG_BASE+0xC0) 225 #define MIU2_PROTECT1_START (MIU2_REG_BASE+0xC4) 226 #define MIU2_PROTECT2_START (MIU2_REG_BASE+0xC8) 227 #define MIU2_PROTECT3_START (MIU2_REG_BASE+0xCC) 228 229 #define REG_MIU2_DDR_STATUS (MIU2_ARB_REG_BASE+0x66) 230 231 //MIU2 232 #define MIU3_PROTECT_EN (MIU3_REG_BASE+0xD2) 233 #define MIU3_PROTECT_DDR_SIZE (MIU3_REG_BASE+0xD3) 234 #define MIU3_PROTECT0_ID0 (MIU3_REG_BASE+0x2E) 235 #define MIU3_BW_REQUEST (MIU3_REG_BASE+0x1A) 236 #define MIU3_BW_RESULT (MIU3_REG_BASE+0x1C) 237 #define MIU3_PROTECT0_ID_ENABLE (MIU3_REG_BASE+0x20) 238 #define MIU3_PROTECT1_ID_ENABLE (MIU3_REG_BASE+0x22) 239 #define MIU3_PROTECT2_ID_ENABLE (MIU3_REG_BASE+0x24) 240 #define MIU3_PROTECT3_ID_ENABLE (MIU3_REG_BASE+0x26) 241 #define MIU3_PROTECT0_MSB (MIU3_REG_BASE+0xD0) 242 #define MIU3_PROTECT0_START (MIU3_REG_BASE+0xC0) 243 #define MIU3_PROTECT1_START (MIU3_REG_BASE+0xC4) 244 #define MIU3_PROTECT2_START (MIU3_REG_BASE+0xC8) 245 #define MIU3_PROTECT3_START (MIU3_REG_BASE+0xCC) 246 247 #define REG_MIU_I64_MODE (BIT7) 248 #define REG_MIU_INIT_DONE (BIT15) 249 #define REG_MIU_DDR4 (BIT3) 250 251 //Protection Status 252 #define REG_MIU_PROTECT_LOG_CLR (BIT0) 253 #define REG_MIU_PROTECT_IRQ_MASK (BIT1) 254 #define REG_MIU_PROTECT_HIT_FALG (BIT4) 255 #define REG_MIU_PROTECT_HIT_ID 14:8 256 #define REG_MIU_PROTECT_HIT_NO 7:5 257 258 // MIU Scramble 259 #define REG_MIU_SCRAMBLE_EN (MIU_REG_BASE+0x06) 260 261 //MIU Bus Width 262 #define REG_MI64_FORCE (CHIP_TOP_BASE+0x40) 263 //------------------------------------------------------------------------------------------------- 264 //MAU 265 // 266 //------------------------------------------------------------------------------------------------- 267 #define RIUBASE_MAU0 0x1840UL 268 #define RIUBASE_MAU1 0x1860UL 269 270 271 //------------------------------------------------------------------------------------------------- 272 // MIU ATOP registers 273 //------------------------------------------------------------------------------------------------- 274 #define MIU_DDFSTEP (0x28)//0x110D28 275 #define MIU_SSC_EN (0x29)//0x110D29 276 #define MIU_DDFSPAN (0x2A)//0x110D2A 277 #define MIU_DDFSET (0x30) 278 //#define MIU_PLL_INPUT_DIV_2ND (0x34) // no this reg in Einstein 279 #define MIU_PLL_LOOP_DIV_2ND (0x34) 280 //xxx_div_first 281 #define MIU_PLLCTRL (0x36) 282 #define MIU_DDRPLL_DIV_FIRST (0x37) 283 284 //------------------------------------------------------------------------------------------------- 285 // Type and Structure 286 //------------------------------------------------------------------------------------------------- 287 288 289 #endif // _REG_MIU_H_ 290 291