1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_BANK_MASK 0x1FUL
117 #define GOP_DST_MASK 0xFUL
118
119 // Debug Log
120 #include "ULog.h"
121 MS_U32 u32GOPDbgLevel_hal;
122
123 // Debug Logs, level form low(INFO) to high(FATAL, always show)
124 // Function information, ex function entry
125 #define GOP_H_INFO(x, args...) if(u32GOPDbgLevel_hal>= E_GOP_Debug_Level_HIGH) {ULOGI("GOP HAL", x, ##args);}
126 // Warning, illegal paramter but can be self fixed in functions
127 #define GOP_H_WARN(x, args...) if(u32GOPDbgLevel_hal>= E_GOP_Debug_Level_HIGH){ULOGW("GOP HAL", x, ##args);}
128 // Need debug, illegal paramter.
129 #define GOP_H_DBUG(x, args...) if(u32GOPDbgLevel_hal>= E_GOP_Debug_Level_MED) {ULOGD("GOP HAL", x, ##args);}
130 // Error, function will be terminated but system not crash
131 #define GOP_H_ERR(x, args...) if(u32GOPDbgLevel_hal>= E_GOP_Debug_Level_LOW) {ULOGE("GOP HAL", x, ##args);}
132 // Critical, system crash. (ex. assert)
133 #define GOP_H_FATAL(x, args...) if(u32GOPDbgLevel_hal>= E_GOP_Debug_Level_LOW) {ULOGF("GOP HAL", x, ##args);}
134
135 #define GOP_ASSERT(x) {printf("\33[0;36m error in %s:%d \33[m \n",__FUNCTION__,__LINE__);}
136 //------------------------------------------------------------------------------
137 // Local Var
138 //------------------------------------------------------------------------------
139 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
140 {
141 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
142 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
143 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
144 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
145 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
146 };
147 #ifdef GOP_CMDQ_ENABLE
148 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
149 extern MS_BOOL bMIUSelect[MAX_GOP_SUPPORT];
150 #endif
151 GOP_CHIP_PROPERTY g_GopChipPro =
152 {
153 .bSetHSyncInverse = TRUE,
154 .bGop1GPalette = FALSE,
155 .bSetHPipeOfst = FALSE,
156 .bNeedCheckMVOP = FALSE,
157 .bNeedSetMUX1ToIP0 = FALSE,
158 .bNeedSetMUX3ToIP0 = FALSE,
159 .bNewMux = TRUE,
160 .bNewPalette = TRUE,
161 .bNewBwReg = TRUE,
162 .bGop2VStretch = TRUE,
163 .bIgnoreIPHPD = TRUE, //Uranus4 has handshack with XC, should not set HPD
164 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
165 .bhastilemode = TRUE,
166 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
167 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
168 .bGOPWithVscale = {TRUE, TRUE, TRUE, FALSE, FALSE}, //setting GOP with/without Vscale
169 .bGOPWithScaleDown = {TRUE, FALSE, TRUE, FALSE, FALSE},
170
171 .bDWINSupport = FALSE,
172 .DwinVer = 0x1,
173 .bTstPatternAlpha = TRUE,
174 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
175 .bFRCSupport = FALSE, /*OC path*/
176 .bGOPMixerToVE= FALSE, /*Mixer to VE path*/
177 .bBnkForceWrite = TRUE, /*Direct Bank Force Write*/
178 .bPixelModeSupport = TRUE, /*Pixel Mode Support*/
179 .bScalingDownSupport= TRUE,
180 .b2Pto1PSupport= TRUE,
181 .bTLBSupport= {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE},
182 .GOP_TestPattern_Vaild= E_GOP0,
183 .bInternalMIUSelect= {TRUE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
184
185 #ifdef ENABLE_GOP_T3DPATCH
186 .GOP_PD = 0x250,
187 #else
188 .GOP_PD = 0x17A,
189 #endif
190 .GOP_HDR_OP_PD = 0x0,
191 .GOP_IP_PD = 0x00,
192 .GOP_MVOP_PD = 0x69,
193 .GOP_VE_PD = 0x89,
194 .GOP_MIXER_PD = 0x0,
195 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
196 .GOP_VE_V_Offset = 0x0,
197
198 .GOP_MUX_Delta = 0x1,
199 .GOP_Mux_Offset = {0x0, 0x42, 0x36, 0x3C, 0x48},
200 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX1, E_GOP_MUX4},
201 .GOP_Mux_FRC_offset= 0x13,
202
203 .WordUnit = GOP_WordUnit,
204 .TotalGwinNum = GOP_TotalGwinNum,
205 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
206 .enGOP3DType = E_DRV_3D_DUP_FULL,
207 .bOpInterlace = FALSE,
208 .bGOPVscalePipeDelay = {FALSE, FALSE, FALSE, TRUE, TRUE, FALSE},
209 .bGOPAutoClkGating = TRUE,
210 };
211
212
213 //------------------------------------------------------------------------------
214 // Global Functions
215 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)216 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
217 {
218 GOP_TYPE->GOP0 = E_GOP0;
219 GOP_TYPE->GOP1 = E_GOP1;
220 GOP_TYPE->GOP2 = E_GOP2;
221 GOP_TYPE->GOP3 = E_GOP3;
222 GOP_TYPE->GOP4 = E_GOP4;
223 GOP_TYPE->GOP5 = E_GOP5;
224 GOP_TYPE->DWIN = E_GOP_Dwin;
225 GOP_TYPE->MIXER = E_GOP_MIXER;
226 }
227
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)228 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
229 {
230 MS_U32 u32BankOffSet = 0;
231
232 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
233
234 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
235 {
236 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
237 }
238 else
239 {
240 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
241 }
242
243 return GOP_SUCCESS;
244 }
245
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)246 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
247 {
248 MS_U32 u32BankOffSet =0;
249 MS_U32 u32BitMask,Regval;
250
251 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
252
253 switch(pinpon_mode)
254 {
255 default:
256 case E_DRV_GOP_PINPON_G3D:
257 Regval = bEn << 5;
258 u32BitMask = GOP_BIT5;
259 break;
260 case E_DRV_GOP_PINPON_DWIN:
261 Regval = bEn << 6;
262 u32BitMask = GOP_BIT6;
263 break;
264 case E_DRV_GOP_PINPON_DIP:
265 Regval = bEn << 7;
266 u32BitMask = GOP_BIT7;
267 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT9,(GOP_BIT8|GOP_BIT9));
268 break;
269 case E_DRV_GOP_PINPON_DWIN0:
270 Regval = bEn << 7;
271 u32BitMask = GOP_BIT7;
272 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, 0x0,(GOP_BIT8|GOP_BIT9));
273 break;
274 case E_DRV_GOP_PINPON_DWIN1:
275 Regval = bEn << 7;
276 u32BitMask = GOP_BIT7;
277 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT8,(GOP_BIT8|GOP_BIT9));
278 break;
279 break;
280 }
281
282 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
283 return GOP_SUCCESS;
284 }
285
286
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)287 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
288 {
289 if (gop==E_GOP0)
290 *pBnkOfst = GOP_4G_OFST<<16;
291 else if (gop==E_GOP1)
292 *pBnkOfst = GOP_2G_OFST<<16;
293 else if (gop==E_GOP2)
294 *pBnkOfst = GOP_1G_OFST<<16;
295 else if (gop==E_GOP3)
296 *pBnkOfst = GOP_1GX_OFST<<16;
297 else if (gop==E_GOP4)
298 *pBnkOfst = GOP_1GS0_OFST<<16;
299 else if (gop==E_GOP_MIXER)
300 *pBnkOfst = 0xD<<16;
301 else
302 return FALSE;
303
304 return TRUE;
305 }
306
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)307 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
308 {
309 MS_U16 u16Mask0 = 0;
310 MS_U16 u16Mask1 = 0;
311 if (u16GopMask&GOP_BIT0)
312 {
313 u16Mask0 |= GOP_BIT12;
314 }
315 if (u16GopMask&GOP_BIT1)
316 {
317 u16Mask0 |= GOP_BIT13;
318 }
319 if (u16GopMask&GOP_BIT2)
320 {
321 u16Mask0 |= GOP_BIT14;
322 }
323 if (u16GopMask&GOP_BIT3)
324 {
325 u16Mask0 |= GOP_BIT15;
326 }
327 if (u16GopMask&GOP_BIT4)
328 {
329 u16Mask1 |= GOP_BIT4;
330 }
331 if (u16Mask0 != 0)
332 {
333 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
334 }
335 if (u16Mask1 != 0)
336 {
337 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, 0xFFFF , u16Mask1);
338 }
339 return GOP_SUCCESS;
340 }
341
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)342 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
343 {
344 switch(gop)
345 {
346 case E_GOP0:
347 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
348 break;
349 case E_GOP1:
350 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
351 break;
352 case E_GOP2:
353 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
354 break;
355 case E_GOP3:
356 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
357 break;
358 case E_GOP4:
359 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
360 break;
361 default:
362 break;
363 }
364 return GOP_SUCCESS;
365 }
366
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)367 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
368 {
369 MS_U16 u16GopAck = 0,reg_val =0;
370 switch(gop)
371 {
372 case E_GOP0:
373 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
374 if(reg_val&GOP_BIT12)
375 u16GopAck = FALSE;
376 else
377 u16GopAck = TRUE;
378 break;
379 case E_GOP1:
380 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
381 if(reg_val&GOP_BIT13)
382 u16GopAck = FALSE;
383 else
384 u16GopAck = TRUE;
385 break;
386 case E_GOP2:
387 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
388 if(reg_val&GOP_BIT14)
389 u16GopAck = FALSE;
390 else
391 u16GopAck = TRUE;
392 break;
393 case E_GOP3:
394 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
395 if(reg_val&GOP_BIT15)
396 u16GopAck = FALSE;
397 else
398 u16GopAck = TRUE;
399 break;
400 case E_GOP4:
401 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
402 if(reg_val&GOP_BIT4)
403 u16GopAck = FALSE;
404 else
405 u16GopAck = TRUE;
406 break;
407 default:
408 break;
409 }
410 return u16GopAck;
411 }
412
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)413 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
414 {
415 MS_U32 u32BankOffSet;
416
417 if (u8GOP < 3) /* only GOP0~GOP2 can support two linebuufer mode */
418 {
419 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
420 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_TWO_LINEBUFFER, bEnable?GOP_BIT12:0, GOP_BIT12);
421 }
422
423 return GOP_SUCCESS;
424 }
425
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)426 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
427 {
428 MS_U32 u32bankoff = 0;
429 MS_U16 mask_shift=0xFF;
430 MS_U16 u16RegVal=0xFF;
431 MS_U8 u8MIUSel=0xF;
432
433 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
434 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
435
436 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, 0xDFD0, GOP_REG_WORD_MASK); //set GOP DMA Burst length to "32", set DMA FIFO threhold to "0xD0"
437
438 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
439 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
440
441 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
442
443 if((u8GOPNum == 0)||(u8GOPNum == 1)||(u8GOPNum == 2))
444 {
445 if(u8GOPNum == 0)
446 {
447 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT13|GOP_BIT14);
448 }
449 else
450 {
451 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT14);
452 }
453 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_TWO_LINEBUFFER, GOP_BIT12, GOP_BIT12);
454
455 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK);
456 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, GOP_BIT2);
457 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, GOP_BIT8|GOP_BIT10|GOP_BIT12, (GOP_BIT8|GOP_BIT9)|(GOP_BIT10|GOP_BIT11)|(GOP_BIT12|GOP_BIT13));
458 }
459
460 /* enable GOP clock */
461 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM1_DISABLE_CLK|CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
462 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, BMASK(7:0)); /* GOP Line buffer sram clock */
463
464 switch(u8GOPNum)
465 {
466 case E_GOP0:
467 mask_shift = GOP_MIU_CLIENT_GOP0;
468 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
469 break;
470 case E_GOP1:
471 mask_shift = GOP_MIU_CLIENT_GOP1;
472 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
473 break;
474 case E_GOP2:
475 mask_shift = GOP_MIU_CLIENT_GOP2;
476 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
477 break;
478 case E_GOP3:
479 mask_shift = GOP_MIU_CLIENT_GOP3;
480 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK); /* GOP 3 */
481 break;
482 case E_GOP4:
483 mask_shift = GOP_MIU_CLIENT_GOP4;
484 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, 0, CKG_GOPG4_DISABLE_CLK_MASK); /* GOP 4 */
485 break;
486 case E_GOP5:
487 mask_shift = GOP_MIU_CLIENT_GOP5;
488 break;
489 case E_GOP_Dwin:
490 mask_shift = GOP_MIU_CLIENT_DWIN;
491 break;
492 default:
493 mask_shift = 0xFF;
494 break;
495 }
496
497
498 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
499 {
500 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal);
501 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
502 #ifdef GOP_MIU_GROUP2
503 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal);
504 u8MIUSel = u8MIUSel|(((u16RegVal>>mask_shift)&0x0000001UL)<<1);
505 #endif
506 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
507 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
508 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
509 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_IP_SEL, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
510 }
511
512 //OC_RM_alpha
513 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, GOP_BIT0, GOP_BIT0);
514 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
515 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
516 }
517
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)518 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
519 {
520 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
521 }
522
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)523 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
524 {
525 switch(u8GopNum)
526 {
527 case E_GOP0:
528 return (MS_U8)MAX_GOP0_GWIN;
529 break;
530 case E_GOP1:
531 return (MS_U8)MAX_GOP1_GWIN;
532 break;
533 case E_GOP2:
534 return (MS_U8)MAX_GOP2_GWIN;
535 break;
536 case E_GOP3:
537 return (MS_U8)MAX_GOP3_GWIN;
538 break;
539 case E_GOP4:
540 return (MS_U8)MAX_GOP4_GWIN;
541 break;
542 default:
543 GOP_ASSERT(0);
544 return 0xFF;
545 break;
546 }
547 }
548
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)549 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
550 {
551 MS_U8 u8GWinId = 0;
552
553 //Adjust GWIN ID by different Chip
554
555 switch(u8Gop)
556 {
557 case E_GOP0:
558 u8GWinId = GOP0_GwinIdBase + u8Idx;
559 break;
560 case E_GOP1:
561 u8GWinId = GOP1_GwinIdBase + u8Idx;
562 break;
563 case E_GOP2:
564 u8GWinId = GOP2_GwinIdBase + u8Idx;
565 break;
566 case E_GOP3:
567 u8GWinId = GOP3_GwinIdBase + u8Idx;
568 break;
569 case E_GOP4:
570 u8GWinId = GOP4_GwinIdBase + u8Idx;
571 break;
572 default:
573 break;
574 }
575 return u8GWinId;
576
577 }
578
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)579 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
580 {
581 switch(u8GOPNum)
582 {
583 case E_GOP0: // GOP4G
584 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
585 return GOP_SUCCESS;
586 case E_GOP1: // GOP2G
587 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
588 return GOP_SUCCESS;
589 case E_GOP2: // GOP1G
590 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
591 return GOP_SUCCESS;
592 case E_GOP3: // GOP1GX
593 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
594 return GOP_SUCCESS;
595 case E_GOP4: // GOP1GS
596 pGOPHalLocal->bank_offset = GOP_1GS0_OFST<<16;
597 return GOP_SUCCESS;
598 default:
599 GOP_ASSERT(0);
600 return GOP_FAIL;
601 }
602 }
603
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)604 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
605 {
606 MS_U16 u16Bank;
607 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
608 u16Bank &= ~BMASK(3:0);
609 u16Bank |= (u8bank&BMASK(3:0));
610 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
611 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL_EX);
612 u16Bank &= ~GOP_BIT4;
613 u16Bank |= ((u8bank&GOP_BIT4)<<GOP_BIT4);
614 GOP_WRITE2BYTE(GOP_BAK_SEL_EX, u16Bank);
615 }
616
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)617 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
618 {
619 MS_U16 u16GetBank;
620 u16GetBank = ((GOP_READ2BYTE(GOP_BAK_SEL_EX)& GOP_BIT8)>> GOP_BIT4)| (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
621 return (u16GetBank&GOP_BANK_MASK);
622 }
623
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)624 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
625 {
626 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
627 MS_U32 bank;
628 MS_U32 direct_addr;
629
630 GOP_H_INFO("HAL_GOP_Read16Reg[%td]\n", (ptrdiff_t)u32addr);
631
632 //* Gop driver should access another HW IP register
633 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
634 switch (u32addr & 0xFF00)
635 {
636 case GOP_REG_BASE:
637 {
638 bank = (u32addr & 0xFF0000) >> 8;
639
640 if(bank==0xE00)//GOP4: 0x121B00
641 {
642 bank=GOP_REG_GOP4_BK_OFFSET;
643 }
644 else if(bank==0xF00)//GWIN4: 0x121E00
645 {
646 bank=GOP_REG_GOP4_GW_OFFSET;
647 }
648 else if(bank==0x1000)//GOP4_ST
649 {
650 bank=GOP_REG_GOP4_ST_OFFSET;
651 }
652
653 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
654 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
655 break;
656 }
657 case SC1_REG_BASE:
658 {
659 if(g_GopChipPro.bXCDirrectBankSupport)
660 {
661 u16xcSubbank = (u32addr & 0xFF0000)>>8;
662 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
663 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
664 }
665 else
666 {
667 u16xcSubbank = (u32addr & 0xFF0000)>>16;
668 u16BankAddr = GOP_SC_BANKSEL+0;
669 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
670
671 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
672 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
673 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
674 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
675 }
676 break;
677 }
678 case GE_REG_BASE:
679 case CKG_REG_BASE:
680 case MIU0_REG_BASE:
681 case MIU_REG_BASE:
682 case MVOP_REG_BASE:
683 {
684 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
685 break;
686 }
687 #ifdef GOP_MIU_GROUP2
688 case (MIU2_REG_BASE & 0xFF00):
689 {
690 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
691 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
692
693 break;
694 }
695 #endif
696 default:
697 {
698 //Gop lib current do not support this HW ip base
699 GOP_ASSERT(0);
700 *pu16ret =0;
701 break;
702 }
703 }
704 }
705
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)706 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
707 {
708 MS_U16 u16tmp=0;
709 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
710 MS_U32 bank;
711 MS_U32 direct_addr;
712
713 GOP_H_INFO("HAL_GOP_Write16Reg[%04tx] = %04x\n", (ptrdiff_t)u32addr, u16val);
714
715 if(mask!=0xffff)
716 {
717 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
718 u16tmp &= ~mask;
719 u16val &= mask;
720 u16val |= u16tmp;
721 }
722
723 //* Gop driver should access another HW IP register
724 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
725 switch (u32addr & 0xFF00)
726 {
727 case GOP_REG_BASE:
728 {
729 bank = (u32addr & 0xFF0000) >> 8;
730
731 if(bank==0xE00)//GOP4: 0x121B00
732 {
733 bank=GOP_REG_GOP4_BK_OFFSET;
734 }
735 else if(bank==0xF00)//GWIN4: 0x121E00
736 {
737 bank=GOP_REG_GOP4_GW_OFFSET;
738 }
739 else if(bank==0x1000) //GOP4_ST
740 {
741 bank=GOP_REG_GOP4_ST_OFFSET;
742 }
743
744 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
745 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
746 break;
747 }
748 case SC1_REG_BASE:
749 if(g_GopChipPro.bXCDirrectBankSupport)
750 { /*Derrick Bank*/
751 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
752 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
753 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
754 }
755 else
756 { /*Sub Bank*/
757 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
758 u16BankAddr = GOP_SC_BANKSEL+0;
759 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
760
761 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
762 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
763 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
764 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
765 }
766 break;
767 case GE_REG_BASE:
768 case CKG_REG_BASE:
769 case MIU0_REG_BASE:
770 case MIU_REG_BASE:
771 {
772 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
773 break;
774 }
775 #ifdef GOP_MIU_GROUP2
776 case (MIU2_REG_BASE & 0xFF00):
777 {
778 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
779 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
780 break;
781 }
782 #endif
783 default:
784 {
785 //Gop lib current do not support this HW ip base
786 GOP_ASSERT(0);
787 break;
788 }
789
790 }
791 }
792
793
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)794 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
795 {
796 MS_U32 bank;
797 MS_U32 direct_addr;
798
799 GOP_H_INFO("HAL_GOP_Write32Reg[%tx] = %tx\n", (ptrdiff_t)u32addr, (ptrdiff_t)u32val);
800
801 //* Gop driver should access another HW IP register
802 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
803 switch (u32addr & 0xFF00)
804 {
805 case GOP_REG_BASE:
806 {
807 bank = (u32addr & 0xFF0000) >> 8;
808 if(bank==0xE00)//GOP4: 0x121B00
809 {
810 bank=GOP_REG_GOP4_BK_OFFSET;
811 }
812 else if(bank==0xF00)//GWIN4: 0x121E00
813 {
814 bank=GOP_REG_GOP4_GW_OFFSET;
815 }
816 else if(bank==0x1000) //GOP4_ST
817 {
818 bank=GOP_REG_GOP4_ST_OFFSET;
819 }
820
821 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
822 GOP_WRITE2BYTE((direct_addr&0xFFFFF), (u32val&0xFFFF));
823 GOP_WRITE2BYTE((direct_addr&0xFFFFF)+2, (u32val&0xFFFF0000)>>16);
824 break;
825 }
826
827 case GE_REG_BASE:
828 case SC1_REG_BASE:
829 case CKG_REG_BASE:
830 {
831 GOP_WRITE2BYTE((u32addr&0xFFFF), (u32val&0xFFFF));
832 GOP_WRITE2BYTE((u32addr&0xFFFF)+2, (u32val&0xFFFF0000)>>16);
833 break;
834 }
835
836 default:
837 {
838 //Gop lib current do not support this HW ip base
839 GOP_ASSERT(0);
840 break;
841 }
842
843 }
844 }
845
846 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
847
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)848 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
849 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
850 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
851 {
852 MS_U8 i=0;
853 GOP_H_INFO("GOP_Write32Pal : i= %02x, ARGB = %02x,%02x,%02x,%02x\n",u8Index, u8A, u8R, u8G, u8B);
854
855 /* Don't care high byte */
856 GOP_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
857
858 for(i =(GOP_WordUnit-1);i>4;i--)
859 {
860 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
861 }
862 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
863 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
864 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
865 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
866 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
867 *pREGMAP_Offset += GOP_WordUnit;
868
869 MsOS_FlushMemory(); //make sure cpu write data to dram
870
871 }
872
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)873 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
874 {
875 MS_U16 bpp=0;
876
877 switch ( fbFmt )
878 {
879 case E_DRV_GOP_COLOR_RGB555_BLINK :
880 case E_DRV_GOP_COLOR_RGB565 :
881 case E_DRV_GOP_COLOR_ARGB1555:
882 case E_DRV_GOP_COLOR_RGBA5551:
883 case E_DRV_GOP_COLOR_ARGB4444 :
884 case E_DRV_GOP_COLOR_RGBA4444 :
885 case E_DRV_GOP_COLOR_RGB555YUV422:
886 case E_DRV_GOP_COLOR_YUV422:
887 case E_DRV_GOP_COLOR_2266:
888 bpp = 16;
889 break;
890 case E_DRV_GOP_COLOR_ARGB8888 :
891 case E_DRV_GOP_COLOR_ABGR8888 :
892 bpp = 32;
893 break;
894
895 case E_DRV_GOP_COLOR_I8 :
896 bpp = 8;
897 break;
898
899 default :
900 //print err
901 GOP_ASSERT(0);
902 bpp = 0xFFFF;
903 break;
904 }
905 return bpp;
906
907 }
908
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)909 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
910 {
911 MS_U16 regval;
912 /*For compatibility
913 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
914 MS_U8 u8coef_cpt = u8coef;
915
916 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
917 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
918 {
919 switch(u8coef)
920 {
921 case 0x0 :
922 u8coef_cpt = u8coef<<2;
923 break;
924 case 0x3f :
925 u8coef_cpt = ((u8coef<<2)|0x3);
926 break;
927 default:
928 u8coef_cpt = ((u8coef<<2)|0x1);
929 break;
930 }
931 }
932
933 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
934 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
935 {
936 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef&0x3F)<<8);
937 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
938 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
939 }
940 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
941 else
942 {
943 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
944 {
945 regval = (MS_U16)(bEnable?(1<<14):0);
946 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
947 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
948 }
949 else if ((u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)))
950 {
951 regval = (MS_U16)(bEnable?(1<<14):0);
952 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
953 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
954 }
955 else
956 {
957 regval = (MS_U16)(bEnable?(1<<14):0);
958 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN0_CTRL, regval, 0x4000);
959 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u8coef, 0xFF);
960 }
961 }
962 }
963
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)964 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
965 {
966 pGOPHalLocal->va_mmio_base = addr;
967 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)968 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
969 {
970 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)971 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
972 {
973 }
974
975
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)976 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
977 {
978 /*A5 GOP dst type:
979 1: IP (Main)
980 0: IP (Sub)
981 2: OP
982 3: MVOP
983 4: MVOP (Sub)
984 6: FRC
985 11: InsideFRC
986 */
987 MS_U8 i=0, Cnt=0;
988 MS_U16 u16RegVal;
989 MS_U32 u32BankOffSet;
990 DRV_GOPDstType pGopDst;
991 MS_BOOL bEnable;
992 MS_U16 u16HSyncMask=GOP_BIT14;
993
994 if( GopNum >= MAX_GOP_SUPPORT)
995 {
996 return GOP_INVALID_PARAMETERS;
997 }
998
999 switch (eDstType)
1000 {
1001 case E_DRV_GOP_DST_IP0:
1002 u16RegVal = 0x0;
1003 bEnable = FALSE;
1004 u16HSyncMask=0;
1005 break;
1006
1007 case E_DRV_GOP_DST_IP0_SUB:
1008 u16RegVal = 0x1;
1009 bEnable = FALSE;
1010 u16HSyncMask=0;
1011 break;
1012
1013 case E_DRV_GOP_DST_OP0:
1014 u16RegVal = 0x2;
1015 bEnable = FALSE;
1016 u16HSyncMask=GOP_BIT14;
1017 break;
1018
1019 case E_DRV_GOP_DST_VOP:
1020 u16RegVal = 0x3;
1021 bEnable = FALSE;
1022 u16HSyncMask=GOP_BIT14;
1023 break;
1024
1025 case E_DRV_GOP_DST_VOP_SUB:
1026 u16RegVal = 0x4;
1027 bEnable = FALSE;
1028 u16HSyncMask=GOP_BIT14;
1029 break;
1030
1031 case E_DRV_GOP_DST_FRC:
1032 u16RegVal = 0x6;
1033 bEnable = TRUE;
1034 u16HSyncMask=GOP_BIT14;
1035 break;
1036
1037 case E_DRV_GOP_DST_VE:
1038 u16RegVal = 0x7;
1039 bEnable = TRUE;
1040 u16HSyncMask=GOP_BIT14;
1041 break;
1042 case E_DRV_GOP_DST_DIP:
1043 u16RegVal = 0x8;
1044 bEnable = TRUE;
1045 u16HSyncMask=GOP_BIT14;
1046 break;
1047 default:
1048 return GOP_FUN_NOT_SUPPORTED;
1049 }
1050 if(bOnlyCheck == FALSE)
1051 {
1052 pGOPHalLocal->pHALShared->GOP_Dst[GopNum] = eDstType;
1053
1054 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1055 HAL_GOP_SetGOP2Pto1P(pGOPHalLocal, GopNum, bEnable);
1056 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0));
1057
1058 //for Monaco, IP need set Vsync inverse in IP
1059 if (eDstType == E_DRV_GOP_DST_IP0)
1060 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, (MS_U16)GOP_BIT1, GOP_BIT1);
1061 else
1062 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, (MS_U16)~GOP_BIT1, GOP_BIT1);
1063 //For Bypass
1064 for(i=0; i<MAX_GOP_SUPPORT ;i++)
1065 {
1066 HAL_GOP_GetGOPDst(pGOPHalLocal, i, &pGopDst);
1067 if(pGopDst == E_DRV_GOP_DST_FRC)
1068 {
1069 Cnt++;
1070 }
1071 }
1072
1073 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
1074 }
1075 return GOP_SUCCESS;
1076 }
1077
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)1078 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
1079 {
1080 return GOP_FUN_NOT_SUPPORTED;
1081 }
1082
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)1083 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
1084 {
1085 return GOP_FUN_NOT_SUPPORTED;
1086 }
1087
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1088 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1089 {
1090 /*T8
1091 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
1092 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1093 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
1094 */
1095 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3, gop1gs=4;
1096 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gs<<(GOP_MUX_SHIFT*4))|(gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
1097 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
1098 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1099 return GOP_SUCCESS;
1100 }
1101
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1102 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1103 {
1104 MS_U16 u16GopMux=0;
1105 switch(eGopMux)
1106 {
1107 case E_GOP_MUX0:
1108 case E_GOP_MUX1:
1109 case E_GOP_MUX2:
1110 case E_GOP_MUX3:
1111 case E_GOP_MUX4:
1112 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1113 *u8GOPNum = (u16GopMux >> (eGopMux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1114 break;
1115 case E_GOP_IP0_MUX:
1116 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1117 *u8GOPNum = (u16GopMux&GOP_IP_MAIN_MUX_MASK)>>GOP_IP_MAIN_MUX_SHIFT;
1118 break;
1119 case E_GOP_IP0_SUB_MUX:
1120 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1121 *u8GOPNum = (u16GopMux&GOP_IP_SUB_MUX_MASK)>>GOP_IP_SUB_MUX_SHIFT;
1122 break;
1123 case E_GOP_VOP0_MUX:
1124 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1125 *u8GOPNum = (u16GopMux&GOP_IP_VOP0_MUX_MASK)>>GOP_IP_VOP0_MUX_SHIFT;
1126 break;
1127 case E_GOP_VOP0_SUB_MUX:
1128 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1129 *u8GOPNum = (u16GopMux&GOP_IP_VOP1_MUX_MASK)>>GOP_IP_VOP1_MUX_SHIFT;
1130 break;
1131 case E_GOP_Mix_MUX0:
1132 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1133 *u8GOPNum = (u16GopMux&GOP_Mix_MUX0_MASK)>>GOP_Mix_MUX0_SHIFT;
1134 break;
1135 case E_GOP_Mix_MUX1:
1136 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1137 *u8GOPNum = (u16GopMux&GOP_Mix_MUX1_MASK)>>GOP_Mix_MUX1_SHIFT;
1138 break;
1139 case E_GOP_VE0_MUX:
1140 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1141 *u8GOPNum = (u16GopMux&GOP_VE0_MUX_MASK)>>GOP_VE0_MUX_SHIFT;
1142 break;
1143 case E_GOP_VE1_MUX:
1144 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1145 *u8GOPNum = (u16GopMux&GOP_VE1_MUX_MASK)>>GOP_VE1_MUX_SHIFT;
1146 break;
1147 case E_GOP_DIP_MUX:
1148 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1149 *u8GOPNum = (u16GopMux&GOP_DIP_MUX_MASK)>>GOP_DIP_MUX_SHIFT;
1150 break;
1151 case E_GOP_FRC_MUX0:
1152 case E_GOP_FRC_MUX1:
1153 case E_GOP_FRC_MUX2:
1154 case E_GOP_FRC_MUX3:
1155 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1156 *u8GOPNum = (u16GopMux >> ((eGopMux%E_GOP_FRC_MUX0)*GOP_FRC_MUX_SHIFT))& GOP_FRC_REGMUX_MASK;
1157 break;
1158 case E_GOP_IP1_MUX:
1159 case E_GOP_VOP1_MUX:
1160 case E_GOP_BYPASS_MUX0:
1161 case E_GOP_OP1_MUX:
1162 case E_GOP_GS_MUX:
1163 case E_GOP_DUALRATE_OP_MUX0:
1164 case E_GOP_DUALRATE_OP_MUX1:
1165 case E_GOP_DUALRATE_OP_MUX2:
1166 break;
1167 default:
1168 GOP_H_ERR("[%s]ERROR, not support the mux[%d]\n",__FUNCTION__,eGopMux);
1169 break;
1170 }
1171 }
1172
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1173 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1174 {
1175 MS_U16 u16Ret[4]={0};
1176
1177 switch(eGopMux)
1178 {
1179 case E_GOP_MUX0:
1180 case E_GOP_MUX1:
1181 case E_GOP_MUX2:
1182 case E_GOP_MUX3:
1183 case E_GOP_MUX4:
1184 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1185 break;
1186 case E_GOP_IP0_MUX:
1187 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
1188 break;
1189 case E_GOP_IP1_MUX:
1190 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_SUB_MUX_SHIFT, GOP_IP_SUB_MUX_MASK);
1191 break;
1192 case E_GOP_VOP0_MUX:
1193 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
1194 break;
1195 case E_GOP_VOP1_MUX:
1196 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
1197 break;
1198 case E_GOP_Mix_MUX0:
1199 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX0_SHIFT, GOP_Mix_MUX0_MASK);
1200 break;
1201 case E_GOP_Mix_MUX1:
1202 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX1_SHIFT, GOP_Mix_MUX1_MASK);
1203 break;
1204 case E_GOP_VE0_MUX:
1205 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE0_MUX_SHIFT, GOP_VE0_MUX_MASK);
1206 break;
1207 case E_GOP_VE1_MUX:
1208 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE1_MUX_SHIFT, GOP_VE1_MUX_MASK);
1209 break;
1210 case E_GOP_DIP_MUX:
1211 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1212 break;
1213 case E_GOP_FRC_MUX0:
1214 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1215 break;
1216 case E_GOP_FRC_MUX1:
1217 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1218 break;
1219 case E_GOP_FRC_MUX2:
1220 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1221 break;
1222 case E_GOP_FRC_MUX3:
1223 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1224 break;
1225 case E_GOP_BYPASS_MUX0:
1226 //Check MUX is using? Checking from priority high to low
1227 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, &u16Ret[0]);
1228 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, &u16Ret[1]);
1229 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, &u16Ret[2]);
1230 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, &u16Ret[3]);
1231
1232 //Checking if un-use
1233 if((u16Ret[0] & GOP_BIT0) ==0)
1234 {
1235 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)));
1236 }
1237 else if((u16Ret[1] & GOP_BIT0) ==0)
1238 {
1239 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)));
1240 }
1241 else if((u16Ret[2] & GOP_BIT0) ==0)
1242 {
1243 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)));
1244 }
1245 else if((u16Ret[3] & GOP_BIT0) ==0)
1246 {
1247 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)));
1248 }
1249 else
1250 {
1251 GOP_H_ERR("[%s][%d]FRC mux is already full.\n",__FUNCTION__,__LINE__);
1252 }
1253 break;
1254 break;
1255 default:
1256 GOP_H_ERR("[%s]ERROR mux setting\n",__FUNCTION__);
1257 break;
1258 }
1259 }
1260
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1261 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1262 {
1263 /* GOP OP Path enable to SC Setting
1264 A5: GOP OP Path blending with SC sequence
1265 mux1-->mux0-->mux2-->mux3
1266 */
1267 MS_U16 muxValue=0, regval=0;
1268
1269 DRV_GOPDstType pGopDst = E_DRV_GOP_DST_INVALID;
1270 MS_U16 u164K2KMuxValue=0;
1271
1272 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1273 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1274
1275 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1276 {
1277 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1278 }
1279
1280 if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1281 {
1282 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12);
1283 }
1284
1285 if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1286 {
1287 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1288 }
1289
1290 if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1291 {
1292 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1293 }
1294
1295 if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1296 {
1297 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1298 }
1299
1300 /*For FRC mux switch*/
1301 HAL_GOP_GetGOPDst(pGOPHalLocal, gopNum, &pGopDst);
1302 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u164K2KMuxValue);
1303 if (gopNum== (u164K2KMuxValue & GOP_MUX0_MASK))
1304 {
1305 /* Switch FRC blending */
1306 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1307 }
1308
1309 if (gopNum== ((u164K2KMuxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1310 {
1311 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1312 }
1313
1314 if (gopNum== ((u164K2KMuxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1315 {
1316 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1317 }
1318
1319 if (gopNum== ((u164K2KMuxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1320 {
1321 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1322 }
1323
1324 return GOP_SUCCESS;
1325 }
1326
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1327 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1328 {
1329 MS_U32 u32pBankOffSet=0;
1330 MS_U16 u16Regval;
1331
1332 if(g_GopChipPro.b2Pto1PSupport)
1333 {
1334 _GetBnkOfstByGop(gopNum, &u32pBankOffSet);
1335 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, &u16Regval);
1336 HAL_GOP_Write16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, bEnable?(u16Regval |0x0800):(u16Regval & ~0x0800), 0x0800);
1337 }
1338 return GOP_SUCCESS;
1339 }
1340
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1341 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1342 {
1343 /* GOP OP Path enable to SC Setting
1344 A5: GOP OP Path blending with SC sequence
1345 mux1-->mux0-->mux2-->mux3
1346 */
1347 MS_U16 muxValue=0, regval=0;
1348
1349 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1350 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1351 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1352 {
1353 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
1354 }
1355 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1356 {
1357 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x1000):(regval & ~0x1000), 0x3000);
1358 }
1359 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1360 {
1361 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
1362 }
1363 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1364 {
1365 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
1366 }
1367 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1368 {
1369 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x4000):(regval & ~0x4000), 0xc000);
1370 }
1371 else
1372 {
1373 return GOP_FAIL;
1374 }
1375 return GOP_SUCCESS;
1376 }
1377
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1378 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1379 {
1380 MS_U16 muxValue=0, regval=0;
1381
1382 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1383 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1384 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1385 {
1386 *pbEnable = (regval & GOP_BIT4) == GOP_BIT4;
1387 }
1388 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1389 {
1390 *pbEnable = (regval & GOP_BIT12) == GOP_BIT12;
1391 }
1392 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1393 {
1394 *pbEnable = (regval & GOP_BIT6) == GOP_BIT6;
1395 }
1396 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1397 {
1398 *pbEnable = (regval & GOP_BIT8) == GOP_BIT8;
1399 }
1400 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1401 {
1402 *pbEnable = (regval & GOP_BIT14) == GOP_BIT14;
1403 }
1404 else
1405 {
1406 return GOP_FAIL;
1407 }
1408 return GOP_SUCCESS;
1409 }
1410
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1411 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1412 {
1413 /*T8
1414 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1415 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1416 */
1417 MS_U16 Mux3Gop, muxValue=0, i;
1418 MS_U16 MuxShift;
1419
1420 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX3;
1421
1422 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1423 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1424 {
1425 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1426 {
1427 Mux3Gop = (muxValue&GOP_MUX3_MASK)>> MuxShift; //save mux2 gop
1428
1429 muxValue &= ~GOP_MUX3_MASK; //clear mux2 setting
1430 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1431 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1432 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1433 break;
1434
1435 }
1436
1437 }
1438 return GOP_SUCCESS;
1439 }
1440
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1441 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1442 {
1443 /*T8 GOP dst type:
1444 0: IP (Main)
1445 1: IP (Sub)
1446 2: OP
1447 3: MVOP
1448 */
1449
1450 /* Monaco clkgen setting */
1451 /******************
1452 0: odclk
1453 1: idclk_f2 (ipm)
1454 2: idclk_f1 (ips)
1455 3: ocmixer
1456 4: ve
1457 5 : mvop main
1458 6 : mvop sub
1459 ******************/
1460
1461 switch(eDstType)
1462 {
1463 case E_DRV_GOP_DST_IP0:
1464
1465 if (gopNum==E_GOP1)
1466 {
1467 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1468 }
1469 else if (gopNum ==E_GOP2)
1470 {
1471 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1472 }
1473 else if (gopNum ==E_GOP3)
1474 {
1475 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
1476 }
1477 else if (gopNum ==E_GOP4)
1478 {
1479 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
1480 }
1481 else if (gopNum==E_GOP0)
1482 {
1483 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1484 }
1485 else
1486 {
1487 GOP_ASSERT(0);
1488 return GOP_INVALID_PARAMETERS;
1489 }
1490 break;
1491
1492 case E_DRV_GOP_DST_IP0_SUB:
1493 if (gopNum==E_GOP1)
1494 {
1495 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1496 }
1497 else if (gopNum==E_GOP2)
1498 {
1499 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK1, CKG_GOPG2_MASK);
1500 }
1501 else if (gopNum==E_GOP3)
1502 {
1503 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK1, CKG_GOPG3_MASK);
1504 }
1505 else if (gopNum ==E_GOP4)
1506 {
1507 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK1, CKG_GOPG4_MASK);
1508 }
1509 else if (gopNum==E_GOP0)
1510 {
1511 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK1, CKG_GOPG0_MASK);
1512 }
1513 else
1514 {
1515 GOP_ASSERT(0);
1516 return GOP_INVALID_PARAMETERS;
1517 }
1518 break;
1519
1520
1521 case E_DRV_GOP_DST_OP0:
1522 if (gopNum==E_GOP1)
1523 {
1524 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
1525 }
1526 else if (gopNum==E_GOP2)
1527 {
1528 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
1529 }
1530 else if (gopNum==E_GOP3)
1531 {
1532 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
1533 }
1534 else if (gopNum ==E_GOP4)
1535 {
1536 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_ODCLK, CKG_GOPG4_MASK);
1537 }
1538 else if (gopNum==E_GOP0)
1539 {
1540 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
1541 }
1542 else
1543 {
1544 GOP_ASSERT(0);
1545 return GOP_INVALID_PARAMETERS;
1546 }
1547 break;
1548 case E_DRV_GOP_DST_DIP:
1549 if (gopNum==E_GOP1)
1550 {
1551 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_FCLK, CKG_GOPG1_MASK);
1552 }
1553 else if (gopNum==E_GOP2)
1554 {
1555 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_FCLK, CKG_GOPG2_MASK);
1556 }
1557 else if (gopNum==E_GOP3)
1558 {
1559 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_FCLK, CKG_GOPG3_MASK);
1560 }
1561 else if (gopNum ==E_GOP4)
1562 {
1563 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_FCLK, CKG_GOPG4_MASK);
1564 }
1565 else if (gopNum==E_GOP0)
1566 {
1567 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_FCLK, CKG_GOPG0_MASK);
1568 }
1569 else
1570 {
1571 GOP_ASSERT(0);
1572 return GOP_INVALID_PARAMETERS;
1573 }
1574
1575 break;
1576
1577 case E_DRV_GOP_DST_VOP:
1578 if (gopNum==E_GOP1)
1579 {
1580 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1581 }
1582 else if (gopNum ==E_GOP2)
1583 {
1584 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1585 }
1586 else if (gopNum ==E_GOP3)
1587 {
1588 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
1589 }
1590 else if (gopNum ==E_GOP4)
1591 {
1592 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
1593 }
1594 else if (gopNum==E_GOP0)
1595 {
1596 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1597 }
1598 else
1599 {
1600 GOP_ASSERT(0);
1601 return GOP_INVALID_PARAMETERS;
1602 }
1603
1604 break;
1605 case E_DRV_GOP_DST_FRC:
1606 if (gopNum==E_GOP1)
1607 {
1608 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OCC_FRCCLK, CKG_GOPG1_MASK);
1609 }
1610 else if (gopNum==E_GOP0)
1611 {
1612 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OCC_FRCCLK, CKG_GOPG0_MASK);
1613 }
1614 else if (gopNum==E_GOP2)
1615 {
1616 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OCC_FRCCLK, CKG_GOPG2_MASK);
1617 }
1618 else if (gopNum==E_GOP3)
1619 {
1620 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OCC_FRCCLK, CKG_GOPG3_MASK);
1621 }
1622 else if (gopNum ==E_GOP4)
1623 {
1624 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OCC_FRCCLK, CKG_GOPG4_MASK);
1625 }
1626 else
1627 {
1628 GOP_ASSERT(0);
1629 return GOP_INVALID_PARAMETERS;
1630 }
1631
1632 break;
1633
1634 case E_DRV_GOP_DST_MIXER2VE:
1635 //HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPMIXER_CLK, CKG_GOPMIXER_VECLK, CKG_GOPMIXER_MASK);
1636
1637 if(gopNum == 0)
1638 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
1639 else if(gopNum == 1)
1640 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
1641 else if(gopNum == 2)
1642 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
1643 else if(gopNum == 3)
1644 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
1645 else if(gopNum == 4)
1646 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MIXERCLK_VE, CKG_GOPG4_MASK);
1647
1648 break;
1649
1650 case E_DRV_GOP_DST_VE:
1651 if(gopNum == 0)
1652 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
1653 else if(gopNum == 1)
1654 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
1655 else if(gopNum == 2)
1656 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
1657 else if(gopNum == 3)
1658 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
1659 else if(gopNum == 4)
1660 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MIXERCLK_VE, CKG_GOPG4_MASK);
1661
1662 break;
1663
1664 default:
1665 GOP_ASSERT(0);
1666 return GOP_ENUM_NOT_SUPPORTED;
1667 }
1668 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
1669 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
1670
1671 return GOP_SUCCESS;
1672 }
1673
1674
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1675 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1676 {
1677 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
1678 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1679 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
1680 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1681 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
1682 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1683 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
1684 else
1685 return GOP_INVALID_PARAMETERS;
1686
1687 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
1688 return GOP_SUCCESS;
1689 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1690 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
1691 {
1692 if (bEnable)
1693 {
1694 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
1695 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
1696 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
1697 }
1698 else
1699 {
1700 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
1701 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
1702 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
1703 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
1704 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
1705 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
1706 }
1707
1708 return GOP_SUCCESS;
1709 }
1710
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1711 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1712 {
1713 return GOP_FUN_NOT_SUPPORTED;
1714 }
1715
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)1716 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
1717 {
1718 return GOP_FUN_NOT_SUPPORTED;
1719 }
1720
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)1721 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
1722 {
1723 return GOP_FUN_NOT_SUPPORTED;
1724 }
1725
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)1726 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
1727 {
1728 MS_U32 u32GopIdx;
1729
1730 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
1731 pGOPHalLocal->pHALShared = pHALShared;
1732
1733 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
1734 {
1735 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
1736 }
1737 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
1738 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
1739 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1740 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1741 {
1742 }
1743
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)1744 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
1745 {
1746 MS_U8 u8Miu=0xff;
1747 MS_U16 u16RegVal_L=0;
1748 #ifdef GOP_MIU_GROUP2
1749 MS_U16 u16RegVal_H=0;
1750 #endif
1751
1752 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal_L);
1753 #ifdef GOP_MIU_GROUP2
1754 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
1755 #endif
1756 if (gwinid<MAX_GOP0_GWIN) //gop0
1757 {
1758 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
1759 #ifdef GOP_MIU_GROUP2
1760 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
1761 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
1762 #else
1763 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
1764 #endif
1765 }
1766 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
1767 {
1768 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
1769 #ifdef GOP_MIU_GROUP2
1770 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
1771 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
1772 #else
1773 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
1774 #endif
1775 }
1776 else if (gwinid==GOP2_GwinIdBase) //gop2
1777 {
1778 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
1779 #ifdef GOP_MIU_GROUP2
1780 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
1781 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
1782 #else
1783 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
1784 #endif
1785 }
1786 else if (gwinid==GOP3_GwinIdBase) //gop3
1787 {
1788 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
1789 #ifdef GOP_MIU_GROUP2
1790 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
1791 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
1792 #else
1793 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
1794 #endif
1795 }
1796 else if (gwinid==GOP4_GwinIdBase) //gop4
1797 {
1798 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP4);
1799 #ifdef GOP_MIU_GROUP2
1800 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP4);
1801 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP4)<<1;
1802 #else
1803 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4);
1804 #endif
1805 }
1806 else
1807 {
1808 return GOP_FAIL;
1809 }
1810
1811 if (u8Miu <= 2)
1812 {
1813 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
1814 }
1815 else
1816 {
1817 GOP_H_ERR("[%s] ERROR GOP miu client\n",__FUNCTION__);
1818 return GOP_FAIL;
1819 }
1820 return GOP_SUCCESS;
1821 }
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)1822 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
1823 {
1824 MS_U8 u8Miu=0xff;
1825 MS_U16 u16RegVal_L=0;
1826 MS_U32 u32BnkOfst=0xFFFF;
1827 #ifdef GOP_MIU_GROUP2
1828 MS_U16 u16RegVal_H=0;
1829 #endif
1830
1831 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
1832 {
1833 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
1834 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal_L);
1835
1836 u8Miu= (u16RegVal_L& (GOP_BIT2|GOP_BIT3)) >>2;
1837 }
1838 else
1839 {
1840 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal_L);
1841
1842 #ifdef GOP_MIU_GROUP2
1843 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
1844 #endif
1845 switch (gopnum)
1846 {
1847 case 0:
1848 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
1849 #ifdef GOP_MIU_GROUP2
1850 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
1851 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
1852 #else
1853 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
1854 #endif
1855 break;
1856 case 1:
1857 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
1858 #ifdef GOP_MIU_GROUP2
1859 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
1860 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
1861 #else
1862 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
1863 #endif
1864 break;
1865
1866 case 2:
1867 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
1868 #ifdef GOP_MIU_GROUP2
1869 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
1870 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
1871 #else
1872 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
1873 #endif
1874 break;
1875
1876 case 3:
1877 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
1878 #ifdef GOP_MIU_GROUP2
1879 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
1880 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
1881 #else
1882 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
1883 #endif
1884 break;
1885 case 4:
1886 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP4);
1887 #ifdef GOP_MIU_GROUP2
1888 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP4);
1889 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP4)<<1;
1890 #else
1891 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4);
1892 #endif
1893 break;
1894 default:
1895 return 0xff;
1896 break;
1897 }
1898
1899 if(u8Miu > MAX_GOP_MIUSEL )
1900 {
1901 GOP_H_ERR("[%s] ERROR GOP miu client\n",__FUNCTION__);
1902 return 0xff;
1903 }
1904
1905 }
1906 return u8Miu;
1907 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)1908 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
1909 {
1910 MS_U16 u16Regval;
1911 MS_U32 u32pBankOffSet=0;
1912 GOP_Result ret;
1913
1914 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
1915 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
1916
1917 switch (u16Regval&GOP_DST_MASK)
1918 {
1919 case 0:
1920 *pGopDst = E_DRV_GOP_DST_IP0;
1921 ret = GOP_SUCCESS;
1922 break;
1923 case 1:
1924 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
1925 ret = GOP_SUCCESS;
1926 break;
1927 case 2:
1928 *pGopDst = E_DRV_GOP_DST_OP0;
1929 ret = GOP_SUCCESS;
1930 break;
1931 case 3:
1932 *pGopDst = E_DRV_GOP_DST_VOP;
1933 ret = GOP_SUCCESS;
1934 break;
1935 case 4:
1936 *pGopDst = E_DRV_GOP_DST_VOP_SUB;
1937 ret = GOP_SUCCESS;
1938 break;
1939 case 6:
1940 *pGopDst = E_DRV_GOP_DST_FRC;
1941 ret = GOP_SUCCESS;
1942 break;
1943 case 11:
1944 *pGopDst = E_DRV_GOP_DST_BYPASS;
1945 ret = GOP_SUCCESS;
1946 break;
1947 case 8:
1948 *pGopDst = E_DRV_GOP_DST_DIP;
1949 ret = GOP_SUCCESS;
1950 break;
1951 default:
1952 *pGopDst = E_DRV_GOP_DST_INVALID;
1953 ret = GOP_FAIL;
1954 break;
1955 }
1956
1957 return ret;
1958
1959 }
1960
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)1961 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
1962 {
1963 MS_U16 muxValue=0;
1964 MS_U16 u16RegVal= 0, u16RegMsk = 0;
1965
1966 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
1967
1968 switch(ipSelGop)
1969 {
1970 case MS_DRV_IP0_SEL_GOP0:
1971 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
1972 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
1973 u16RegVal |= GOP_BIT12;//mux0
1974 else
1975 u16RegVal |= GOP_BIT13;//mux1
1976 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1977 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
1978 break;
1979
1980 case MS_DRV_IP0_SEL_GOP1:
1981 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
1982 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
1983 u16RegVal |= GOP_BIT12;//mux0
1984 else
1985 u16RegVal |= GOP_BIT13;//mux1
1986 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1987 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
1988 break;
1989 case MS_DRV_IP0_SEL_GOP2:
1990 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
1991 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
1992 u16RegVal |= GOP_BIT12;//mux0
1993 else
1994 u16RegVal |= GOP_BIT13;//mux1
1995 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1996 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
1997 break;
1998
1999 case MS_DRV_NIP_SEL_GOP0:
2000 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2001 {
2002 u16RegVal = ~GOP_BIT12;//mux0
2003 u16RegMsk = GOP_BIT12;
2004 }
2005 else
2006 {
2007 u16RegVal = ~GOP_BIT13;//mux1
2008 u16RegMsk = GOP_BIT13;
2009 }
2010 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2011 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2012 break;
2013
2014 case MS_DRV_NIP_SEL_GOP1:
2015 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2016 {
2017 u16RegVal = ~GOP_BIT12;//mux0
2018 u16RegMsk = GOP_BIT12;
2019 }
2020 else
2021 {
2022 u16RegVal = ~GOP_BIT13;//mux1
2023 u16RegMsk = GOP_BIT13;
2024 }
2025 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2026 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2027
2028 break;
2029 case MS_DRV_NIP_SEL_GOP2:
2030 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2031 {
2032 u16RegVal = ~GOP_BIT12;//mux0
2033 u16RegMsk = GOP_BIT12;
2034 }
2035 else
2036 {
2037 u16RegVal = ~GOP_BIT13;//mux1
2038 u16RegMsk = GOP_BIT13;
2039 }
2040 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2041 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2042
2043 break;
2044 case MS_DRV_MVOP_SEL:
2045 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2046 u16RegVal |= GOP_BIT12; //mux0
2047 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2048 break;
2049 default:
2050 GOP_H_ERR("[%s] ERROR invalid source select\n",__FUNCTION__);
2051 break;
2052 }
2053 if(0 != u16RegMsk)
2054 {
2055 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
2056 }
2057 }
2058
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2059 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2060 {
2061 return GOP_FUN_NOT_SUPPORTED;
2062 }
2063
2064
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2065 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2066 {
2067 return GOP_FUN_NOT_SUPPORTED;
2068 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)2069 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
2070 {
2071 return GOP_FUN_NOT_SUPPORTED;
2072 }
2073
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2074 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
2075 {
2076 return GOP_FUN_NOT_SUPPORTED;
2077 }
2078
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)2079 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
2080 {
2081 return GOP_FUN_NOT_SUPPORTED;
2082 }
2083
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)2084 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
2085 {
2086 return GOP_FUN_NOT_SUPPORTED;
2087 }
2088
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)2089 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
2090 {
2091 return GOP_FUN_NOT_SUPPORTED;
2092 }
2093
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)2094 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
2095 {
2096 return GOP_FUN_NOT_SUPPORTED;
2097 }
2098
2099
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2100 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2101 {
2102 MS_U32 u32BankOffSet =0;
2103
2104 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2105
2106 if (bEn)
2107 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
2108 else
2109 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
2110
2111 return GOP_SUCCESS;
2112 }
2113
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2114 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2115 {
2116 MS_U32 u32BankOffSet =0;
2117
2118 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2119
2120 if (bEn)
2121 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
2122 else
2123 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
2124
2125 return GOP_SUCCESS;
2126 }
2127
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)2128 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
2129 {
2130 MS_U16 u16Val =0x0;
2131 if (u8win < GOP1_GwinIdBase)
2132 {
2133 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
2134 *pEnable = (MS_BOOL)(u16Val>>15);
2135 }
2136 else if (u8win < GOP2_GwinIdBase)
2137 {
2138 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
2139 *pEnable = (MS_BOOL)(u16Val>>15);
2140 }
2141 else if (u8win < GOP3_GwinIdBase)
2142 {
2143 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
2144 *pEnable = (MS_BOOL)(u16Val>>15);
2145 }
2146 else if (u8win < GOP4_GwinIdBase)
2147 {
2148 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
2149 *pEnable = (MS_BOOL)(u16Val>>15);
2150 }
2151 else if (u8win < GOP5_GwinIdBase)
2152 {
2153 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
2154 *pEnable = (MS_BOOL)(u16Val>>15);
2155 }
2156 else
2157 {
2158 GOP_H_ERR("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2159 return GOP_INVALID_PARAMETERS;
2160 }
2161
2162 return GOP_SUCCESS;
2163 }
2164
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)2165 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
2166 {
2167 MS_U16 u16Val = bEnable << 15;
2168 if (u8win < GOP1_GwinIdBase)
2169 {
2170 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), u16Val, GOP_BIT15);
2171 }
2172 else if (u8win < GOP2_GwinIdBase)
2173 {
2174 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), u16Val, GOP_BIT15);
2175 }
2176 else if (u8win < GOP3_GwinIdBase)
2177 {
2178 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u16Val, GOP_BIT15);
2179 }
2180 else if (u8win < GOP4_GwinIdBase)
2181 {
2182 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u16Val, GOP_BIT15);
2183 }
2184 else if (u8win < GOP5_GwinIdBase)
2185 {
2186 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u16Val, GOP_BIT15);
2187 }
2188 else
2189 {
2190 GOP_H_ERR("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2191 return GOP_INVALID_PARAMETERS;
2192 }
2193 return GOP_SUCCESS;
2194 }
2195
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)2196 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
2197 {
2198 MS_U16 u16Reg = 0;
2199 MS_U32 u32WordBase = 0;
2200 MS_U32 u32BankOffSet=0;
2201
2202 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2203
2204 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
2205
2206 if(u16Reg & GOP_BIT7)
2207 {
2208 u32WordBase = 1;
2209 }
2210 else
2211 {
2212 u32WordBase = GOP_WordUnit;
2213 }
2214
2215 u32SubAddr /= u32WordBase;
2216
2217 if(u8GOP == E_GOP2)
2218 {
2219 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2220 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2221 }
2222 else if(u8GOP == E_GOP3)
2223 {
2224 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2225 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2226
2227 }
2228 else if(u8GOP == E_GOP4)
2229 {
2230 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2231 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2232 }
2233 else if(u8GOP == E_GOP1)
2234 {
2235 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2236 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2237 }
2238 else //gop0
2239 {
2240 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2241 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2242 }
2243
2244 return GOP_SUCCESS;
2245
2246 }
2247
2248 //------------------------------------------------------------------------------
2249 /// Set VE output with OSD
2250 /// @return none
2251 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)2252 GOP_Result HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
2253 {
2254 #ifndef MSOS_TYPE_LINUX_KERNEL
2255 MS_U32 u32Reg = GOP_VE_TVS_OSD_EN;
2256 MS_U16 u16Val = BIT(2)|BIT(3);
2257
2258 if( EN_OSD_0 == eOSD)
2259 {
2260 u32Reg = GOP_VE_TVS_OSD_EN;
2261 }
2262 else if( EN_OSD_1 == eOSD)
2263 {
2264 u32Reg = GOP_VE_TVS_OSD1_EN;
2265 }
2266
2267 if(bEnable) // enable OSD
2268 {
2269 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, ~u16Val, u16Val);
2270 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(5), BIT(5));
2271 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(1), BIT(1));
2272 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(0), BIT(0));
2273 }
2274 else // disable OSD
2275 {
2276 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, 0x0, BIT(0));
2277 }
2278 #endif
2279 return GOP_SUCCESS;
2280 }
2281
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)2282 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
2283 {
2284 MS_U16 regval = 0x0;
2285
2286 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, ®val);
2287 // there are only 2 mux, the 3rd gop will be set to 2nd mux(osd1).
2288 if((gopNum != (regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8)>>6)) && (gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9)))
2289 {
2290 // if have to overwrite one, overwriting INIT VALUE is better.
2291 if (VE_MUX_INIT_VALUE == ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8))>>6))
2292 {
2293 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6), (GOP_BIT6|GOP_BIT7|GOP_BIT8));
2294 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_0, gopNum);
2295 }
2296 else
2297 {
2298 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2299 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_1, gopNum);
2300 }
2301 }
2302 else if(gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9))
2303 {
2304 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2305 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_1, gopNum);
2306 }
2307 else
2308 {
2309 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6) , (GOP_BIT6|GOP_BIT7|GOP_BIT8));
2310 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_0, gopNum);
2311 }
2312 return GOP_SUCCESS;
2313
2314 }
2315
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)2316 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
2317 {
2318 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2319 MS_U16 u16MVOPMirrorCfg = 0;
2320 MS_U16 u16ScalerMirrorCfg = 0;
2321
2322 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
2323 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
2324 if(bHorizontal) // Horizontal
2325 {
2326 if(u16MVOPMirrorCfg & GOP_BIT1)
2327 {
2328 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2329 }
2330 else if(u16ScalerMirrorCfg & GOP_BIT12)
2331 {
2332 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2333 }
2334 }
2335 else //vertical
2336 {
2337 if(u16MVOPMirrorCfg & GOP_BIT0)
2338 {
2339 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2340 }
2341 else if(u16ScalerMirrorCfg & GOP_BIT13)
2342 {
2343 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2344 }
2345 }
2346 return enMirrorType;
2347 }
2348
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)2349 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
2350 {
2351 MS_U32 u32BankOffSet =0;
2352
2353 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2354 HAL_GOP_Write16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_3D_MIDDLE, u16Middle, GOP_REG_WORD_MASK);
2355 return GOP_SUCCESS;
2356 }
2357
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)2358 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
2359 {
2360 MS_U8 i=0, eGopMux=0, FRCMuxOffset=0;
2361 MS_U16 u16Val=0;
2362 MS_U16 u16Mux[MAX_GOP_MUX];
2363
2364 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16Val);
2365 u16Mux[0] =( u16Val & GOP_MUX0_MASK);
2366 u16Mux[1] =( u16Val & GOP_MUX1_MASK) >> (GOP_MUX_SHIFT*1);
2367 u16Mux[2] =( u16Val & GOP_MUX2_MASK) >> (GOP_MUX_SHIFT*2);
2368 u16Mux[3] =( u16Val & GOP_MUX3_MASK) >> (GOP_MUX_SHIFT*3);
2369 u16Mux[4] =( u16Val & GOP_MUX4_MASK) >> (GOP_MUX_SHIFT*4);
2370
2371 switch(u8GOP)
2372 {
2373 case E_GOP0:
2374 case E_GOP1:
2375 case E_GOP2:
2376 case E_GOP3:
2377 case E_GOP4:
2378 for(i=0; i<MAX_GOP_MUX; i++)
2379 {
2380 if(u8GOP == u16Mux[i])
2381 {
2382 eGopMux = i;
2383 if(eGopMux == 4)
2384 {
2385 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, bOCEn<<15, GOP_BIT15);
2386 }
2387 else
2388 {
2389 FRCMuxOffset = 12 + eGopMux;
2390 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, bOCEn<<FRCMuxOffset, 1<<FRCMuxOffset);
2391 }
2392 }
2393 }
2394 break;
2395 default:
2396 return GOP_FAIL;
2397 break;
2398 }
2399
2400 return GOP_SUCCESS;
2401 }
2402
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)2403 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
2404 {
2405 return GOP_FUN_NOT_SUPPORTED;
2406 }
2407
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)2408 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
2409 {
2410 return GOP_FUN_NOT_SUPPORTED;
2411 }
2412
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)2413 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
2414 {
2415 return GOP_FUN_NOT_SUPPORTED;
2416 }
2417
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)2418 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
2419 {
2420 return GOP_FUN_NOT_SUPPORTED;
2421 }
2422
2423 /********************************************************************************/
2424 ///Test Pattern
2425 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)2426 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
2427 {
2428 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
2429 {
2430 return GOP_SUCCESS;
2431 }
2432 else
2433 {
2434 return GOP_FAIL;
2435 }
2436
2437 }
2438
2439
2440 /********************************************************************************/
2441 ///GOP Scaling down (internal)
2442 /********************************************************************************/
2443
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2444 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
2445 {
2446 MS_U16 u16MG_mask=0;
2447 MS_U16 u16Val=0;
2448 MS_U16 u16LB_mask=0;
2449 MS_U16 u16enable=0;
2450
2451 if(u8GOP==0)
2452 {
2453 u16MG_mask=CKG_GOPG0_MG_MASK;
2454 u16Val=GOP_BIT2;
2455 u16LB_mask=CKG_LB_SRAM1_MASK;
2456 u16enable=GOP_BIT2;
2457 }
2458 else if(u8GOP==2)
2459 {
2460 u16MG_mask=CKG_GOPG2_MG_MASK;
2461 u16Val=GOP_BIT6;
2462 u16LB_mask=CKG_LB_SRAM2_MASK;
2463 u16enable=GOP_BIT6;
2464 }
2465 else
2466 {
2467 GOP_H_ERR("[%s] Error message GOP not support scaling down!!",__FUNCTION__);
2468 return GOP_FAIL;
2469 }
2470 if(bEn==TRUE)
2471 {
2472 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, u16Val, u16MG_mask);
2473 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, u16enable, u16LB_mask);
2474 }
2475 else
2476 {
2477 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, u16MG_mask);
2478 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, u16LB_mask);
2479 }
2480 return TRUE;
2481 }
2482
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)2483 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
2484 {
2485 MS_U32 ratio;
2486 MS_U32 u32BankOffSet=0xFFFF;
2487 MS_U16 u16VScalReg;
2488
2489 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2490 if(bEnable ==TRUE)
2491 {
2492 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, &u16VScalReg);
2493 if( u16VScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
2494 {
2495 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, 0x1000 , GOP_REG_WORD_MASK);
2496 GOP_H_WARN("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
2497 }
2498 //Set scaling down ratio
2499 ratio = (dst * 0x100000) / src;
2500 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, ratio);
2501 }
2502 else
2503 {
2504 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, 0);
2505 }
2506
2507 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
2508 {
2509 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
2510 }
2511 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, bEnable , GOP_BIT0);
2512 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_H_OUTPUTSIZE, dst, GOP_REG_WORD_MASK);
2513
2514 return GOP_SUCCESS;
2515
2516 }
2517
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)2518 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
2519 {
2520 MS_U32 ratio =0;
2521 MS_U32 u32BankOffSet=0xFFFF;
2522 MS_U16 u16HScalReg;
2523
2524 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2525 if(bEnable ==TRUE)
2526 {
2527 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, &u16HScalReg);
2528 if( u16HScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
2529 {
2530 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, 0x1000 , GOP_REG_WORD_MASK);
2531 GOP_H_WARN("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
2532 }
2533 ratio = (dst * 0x100000) / src;
2534 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, ratio);
2535 }
2536 else
2537 {
2538 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, 0);
2539 }
2540
2541 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
2542 {
2543 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
2544 }
2545 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, (bEnable<<4) , GOP_BIT4);
2546 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SVM_VEND, dst, GOP_REG_WORD_MASK);
2547
2548 return GOP_SUCCESS;
2549
2550 }
2551
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)2552 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
2553 {
2554 MS_U32 u32BankOffSet=0;
2555
2556 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2557 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
2558 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
2559 return GOP_SUCCESS;
2560 }
2561
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)2562 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
2563 {
2564 MS_U32 u32BankOffSet=0;
2565 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
2566
2567 if (u32GopIdx < MAX_GOP_SUPPORT)
2568 {
2569 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
2570 }
2571 else
2572 {
2573 GOP_H_DBUG("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
2574 *u16Val = 0;
2575 }
2576 return GOP_SUCCESS;
2577 }
2578
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)2579 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
2580 {
2581 MS_U32 u32BankOffSet=0;
2582 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
2583
2584 if (u32GopIdx < MAX_GOP_SUPPORT)
2585 {
2586 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
2587 }
2588 else
2589 {
2590 GOP_H_DBUG("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
2591 }
2592 return GOP_SUCCESS;
2593 }
2594
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)2595 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
2596 {
2597 switch(u32PowerState)
2598 {
2599 case E_POWER_SUSPEND:
2600 {
2601 //CLK
2602 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
2603 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
2604 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
2605 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP4CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
2606 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
2607 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[5]));
2608
2609 //SRAM
2610 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, &(pGOP_STRPrivate->GS_GopReg[0]));
2611 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_MG, &(pGOP_STRPrivate->GS_GopReg[1]));
2612 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->GS_GopReg[2]));
2613
2614 //XC
2615 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
2616 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
2617 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
2618 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
2619 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
2620 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
2621 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
2622 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
2623 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
2624 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
2625 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
2626 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCALPHA, &(pGOP_STRPrivate->XC_GopReg[11]));
2627 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[12]));
2628 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[13]));
2629 }
2630 break;
2631 case E_POWER_RESUME:
2632 {
2633 //CLK
2634 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
2635 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
2636 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
2637 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
2638 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
2639 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[5], GOP_REG_WORD_MASK);
2640
2641 //SRAM
2642 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, pGOP_STRPrivate->GS_GopReg[0], GOP_REG_WORD_MASK);
2643 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, pGOP_STRPrivate->GS_GopReg[1], GOP_REG_WORD_MASK);
2644 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->GS_GopReg[2], GOP_REG_WORD_MASK);
2645
2646 //XC
2647 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
2648 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
2649 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
2650 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
2651 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
2652 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
2653 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
2654 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
2655 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
2656 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
2657 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
2658 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, pGOP_STRPrivate->XC_GopReg[11], GOP_BIT2);
2659 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[12], GOP_REG_WORD_MASK);
2660 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[13], GOP_BIT11);
2661 }
2662 break;
2663 default:
2664 break;
2665 }
2666 return GOP_SUCCESS;
2667 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)2668 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
2669 {
2670 return GOP_FUN_NOT_SUPPORTED;
2671 }
2672
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)2673 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
2674 {
2675 return GOP_FUN_NOT_SUPPORTED;
2676 }
2677
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)2678 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
2679 {
2680 return GOP_FUN_NOT_SUPPORTED;
2681 }
2682
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)2683 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
2684 {
2685 return GOP_FUN_NOT_SUPPORTED;
2686 }
2687
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)2688 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
2689 {
2690 MS_U32 u32BankOffSet=0xFFFF;
2691 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2692
2693 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
2694 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
2695 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
2696
2697 return GOP_SUCCESS;
2698 }
2699
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)2700 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
2701 {
2702 MS_U32 u32BankOffSet=0xFFFF;
2703 MS_U16 mask_shift=0xFF;
2704 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2705
2706 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOP]==TRUE)
2707 {
2708 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
2709 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
2710 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
2711 }
2712 else
2713 {
2714 switch(u8GOP)
2715 {
2716 case E_GOP0:
2717 mask_shift = GOP_MIU_CLIENT_GOP0;
2718 break;
2719 case E_GOP1:
2720 mask_shift = GOP_MIU_CLIENT_GOP1;
2721 break;
2722 case E_GOP2:
2723 mask_shift = GOP_MIU_CLIENT_GOP2;
2724 break;
2725 case E_GOP3:
2726 mask_shift = GOP_MIU_CLIENT_GOP3;
2727 break;
2728 case E_GOP4:
2729 mask_shift = GOP_MIU_CLIENT_GOP4;
2730 break;
2731 case E_GOP5:
2732 mask_shift = GOP_MIU_CLIENT_GOP5;
2733 break;
2734 case E_GOP_Dwin:
2735 mask_shift = GOP_MIU_CLIENT_DWIN;
2736 break;
2737 default:
2738 mask_shift = 0xFF;
2739 MS_CRITICAL_MSG(printf("ERROR gop miu client\n"));
2740 break;
2741
2742 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, miusel<<mask_shift, 1<<mask_shift );
2743 #ifdef GOP_MIU_GROUP2
2744 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
2745 #endif
2746 }
2747 }
2748 return GOP_SUCCESS;
2749 }
2750
HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * bInterlace)2751 GOP_Result HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *bInterlace)
2752 {
2753 MS_U16 reg_val = 0;
2754
2755 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_MAIN_INTERLACE, ®_val);
2756 if(reg_val & BIT(11))
2757 *bInterlace = TRUE;
2758 else
2759 *bInterlace = FALSE;
2760 return GOP_SUCCESS;
2761 }
2762
HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * pbHDREnable)2763 GOP_Result HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *pbHDREnable)
2764 {
2765 *pbHDREnable= FALSE;
2766 return GOP_FUN_NOT_SUPPORTED
2767 }
2768
2769 GOP_Result HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 u8win, MS_U16 hstart, MS_U16 hend, MS_U16 vstart, MS_U16 vend)
2770 {
2771 GOP_Result ret = GOP_SUCCESS;
2772
2773 switch(u8GOP)
2774 {
2775 case E_GOP0:
2776 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
2777 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HEND(u8win), hend, GOP_REG_WORD_MASK);
2778 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VSTR(u8win), vstart, GOP_REG_WORD_MASK);
2779 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VEND(u8win), vend, GOP_REG_WORD_MASK);
2780 break;
2781
2782 case E_GOP1:
2783 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
2784 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HEND(u8win), hend, GOP_REG_WORD_MASK);
2785 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VSTR(u8win), vstart, GOP_REG_WORD_MASK); // 1 pixel
2786 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VEND(u8win), vend, GOP_REG_WORD_MASK); // 1 pixel
2787 break;
2788
2789 case E_GOP2:
2790 case E_GOP3:
2791 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HSTR:GOP_1GX_HSTR, hstart, GOP_REG_WORD_MASK); // word pixels
2792 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HEND:GOP_1GX_HEND, hend, GOP_REG_WORD_MASK); // word pixels
2793 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VSTR:GOP_1GX_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
2794 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VEND:GOP_1GX_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
2795 break;
2796
2797 case E_GOP4:
2798 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, hstart, GOP_REG_WORD_MASK);
2799 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, hend, GOP_REG_WORD_MASK);
2800 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
2801 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
2802 break;
2803
2804 default:
2805 GOP_H_DBUG("invalid Gwin number:%d\n",u8win);
2806 break;
2807 }
2808
2809 return ret;
2810 }
2811
2812 GOP_Result HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8* u8Core)
2813 {
2814 return GOP_FUN_NOT_SUPPORTED;
2815 }
2816
2817 GOP_Result Hal_SetCropWindow(
2818 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
2819 MS_U8 u8GOP,
2820 EN_GOP_CROP_CTL crop_mode
2821 )
2822 {
2823 return GOP_FUN_NOT_SUPPORTED;
2824 }
2825
2826 #ifdef GOP_CMDQ_ENABLE
2827 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
2828 {
2829 MS_U16 u16xcSubbank=0;
2830 MS_U32 bank;
2831 MS_U32 direct_addr;
2832
2833 switch (u32addr & 0xFF00)
2834 {
2835 case GOP_REG_BASE:
2836 {
2837 bank = (u32addr & 0xFF0000) >> 8;
2838
2839 if(bank==0xE00)//GOP4: 0x121B00
2840 {
2841 bank=GOP_REG_GOP4_BK_OFFSET;
2842 }
2843 else if(bank==0xF00)//GWIN4: 0x121E00
2844 {
2845 bank=GOP_REG_GOP4_GW_OFFSET;
2846 }
2847 else if(bank==0x1000) //GOP4_ST
2848 {
2849 bank=GOP_REG_GOP4_ST_OFFSET;
2850 }
2851
2852 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
2853
2854 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
2855 cmdq_struct[(*number)].destionation_value = u16val;
2856 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
2857 cmdq_struct[(*number)].operation = 0x57;
2858 (*number)++;
2859 break;
2860 }
2861 case SC1_REG_BASE:
2862 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
2863 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
2864
2865 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
2866 cmdq_struct[(*number)].destionation_value = u16val;
2867 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
2868 cmdq_struct[(*number)].operation = 0x57;
2869 (*number)++;
2870 break;
2871 case GE_REG_BASE:
2872 case CKG_REG_BASE:
2873 case MIU_REG_BASE:
2874 {
2875 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
2876 cmdq_struct[(*number)].destionation_value = u16val;
2877 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
2878 cmdq_struct[(*number)].operation = 0x57;
2879 (*number)++;
2880 break;
2881 }
2882 #ifdef GOP_MIU_GROUP2
2883 case (MIU2_REG_BASE & 0xFF00):
2884 {
2885 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
2886
2887 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
2888 cmdq_struct[(*number)].destionation_value = u16val;
2889 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
2890 cmdq_struct[(*number)].operation = 0x57;
2891 (*number)++;
2892 break;
2893 }
2894 #endif
2895 default:
2896 {
2897 //Gop lib current do not support this HW ip base
2898 GOP_ASSERT(0);
2899 break;
2900 }
2901
2902 }
2903 return GOP_SUCCESS;
2904 }
2905 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
2906 {
2907 MS_U32 u32BankOffSet;
2908 MS_U16 u16RegVal1 = 0;
2909 MS_BOOL bCheckValidGop = FALSE;
2910 MS_U8 u8CheckTimeCnt = 0;
2911 MS_U8 u8CurrentCmdGop = 0;
2912
2913 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
2914 {
2915 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
2916 {
2917 u8CurrentCmdGop = 0;
2918 }
2919 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
2920 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
2921 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
2922 {
2923 bCheckValidGop = FALSE;
2924 }
2925 else
2926 {
2927 bCheckValidGop = TRUE;
2928 break;
2929 }
2930
2931 // if current gop not init, use next gop instead, check order 0->2->1->3
2932 switch (u8CurrentCmdGop)
2933 {
2934 case 0:
2935 u8CurrentCmdGop = 2;
2936 break;
2937 case 1:
2938 u8CurrentCmdGop = 0;
2939 break;
2940 case 2:
2941 u8CurrentCmdGop = 3;
2942 break;
2943 case 3:
2944 u8CurrentCmdGop = 1;
2945 break;
2946 default:
2947 u8CurrentCmdGop = 0;
2948 break;
2949 }
2950 u8CheckTimeCnt++;
2951 }
2952 if (!bCheckValidGop)
2953 {
2954 GOP_H_DBUG("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
2955 }
2956 *u32GopIdx = u8CurrentCmdGop;
2957 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
2958 (*number)++;
2959 return GOP_SUCCESS;
2960 }
2961 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
2962 {
2963 CH_Struct ch_fire;
2964 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,u32FireBankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
2965 MS_U16 u16ret = 0,u16ret1 = 0;
2966 int i = 0;
2967
2968
2969 _GetBnkOfstByGop(0, &u32BankOffSet);
2970 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
2971 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
2972 #if 0 //for Debug
2973 for(i=0;i<(*number);i++)
2974 {
2975 GOP_H_INFO("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
2976 }
2977 #endif
2978 ch_fire.Command_Number = *number;
2979 ch_fire.Pointer_To_CAFArray = target;
2980 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
2981 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
2982 {
2983 Receive_Return_Value = 0;
2984 MDrv_CMDQ_Printf_Crash_Command();
2985 }
2986 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
2987 MsOS_DelayTask(1);
2988 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
2989 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
2990
2991 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
2992 timer1 = MsOS_GetSystemTime();
2993 timer2 = MsOS_GetSystemTime();
2994 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
2995 {
2996 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
2997 MsOS_DelayTask(1);
2998 timer2 = MsOS_GetSystemTime();
2999 }
3000 if(u16ret1 != (u16ret+1))
3001 {
3002 GOP_H_DBUG("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
3003 MDrv_CMDQ_Printf_Crash_Command();
3004 }
3005 return GOP_SUCCESS;
3006 }
3007
3008 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
3009 {
3010 CAF_Struct fire_struct[24];
3011 MS_U32 u32BankOffSet;
3012 MS_U32 number = 0;
3013 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
3014 MS_U16 u16RegMiu=0, u16RegCoreEna=0;
3015 MS_U32 fireGOP=0;
3016
3017 _GetBnkOfstByGop(gop, &u32BankOffSet);
3018
3019 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal1);
3020 #ifdef GOP_MIU_GROUP2
3021 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3022 #endif
3023 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3024 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3025
3026 switch(gop)
3027 {
3028 case E_GOP0:
3029 {
3030 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3031 break;
3032 }
3033 case E_GOP1:
3034 {
3035 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3036 break;
3037 }
3038 case E_GOP2:
3039 {
3040 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3041 break;
3042 }
3043 case E_GOP3:
3044 {
3045 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3046 break;
3047 }
3048 case E_GOP4:
3049 {
3050 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3051 break;
3052 }
3053 default:
3054 {
3055 GOP_ASSERT(0);
3056 break;
3057 }
3058 }
3059 if(bMIUSelect[gop] == TRUE)
3060 {
3061 if(u16MIUSelect[gop] == 0)
3062 {
3063 u16RegVal1 &= ~(1<<u16MiuClient);
3064 u16RegVal3 &= ~(1<<u16MiuClient);
3065 }
3066 else if(u16MIUSelect[gop] == 1)
3067 {
3068 u16RegVal1 |= (1<<u16MiuClient);
3069 u16RegVal3 &= ~(1<<u16MiuClient);
3070 }
3071 else if(u16MIUSelect[gop] == 2)
3072 {
3073 u16RegVal1 &= ~(1<<u16MiuClient);
3074 u16RegVal3 |= (1<<u16MiuClient);
3075 }
3076 else if(u16MIUSelect[gop] == 3)
3077 {
3078 u16RegVal1 |= (1<<u16MiuClient);
3079 u16RegVal3 |= (1<<u16MiuClient);
3080 }
3081 bMIUSelect[gop] = FALSE;
3082 }
3083 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3084 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3085 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_SC_MIU_SEL,u16RegVal1,0xFFFF);
3086 #ifdef GOP_MIU_GROUP2
3087 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3088 #endif
3089 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3090 return GOP_SUCCESS;
3091 }
3092
3093 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
3094 {
3095 CAF_Struct fire_struct[24];
3096 MS_U32 u32BankOffSet;
3097 MS_U32 number = 0;
3098 MS_U8 gop;
3099 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
3100 MS_U32 fireGOP=0;
3101
3102 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal1);
3103 #ifdef GOP_MIU_GROUP2
3104 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3105 #endif
3106 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3107
3108 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
3109 {
3110 switch(gop)
3111 {
3112 case E_GOP0:
3113 {
3114 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3115 break;
3116 }
3117 case E_GOP1:
3118 {
3119 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3120 break;
3121 }
3122 case E_GOP2:
3123 {
3124 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3125 break;
3126 }
3127 case E_GOP3:
3128 {
3129 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3130 break;
3131 }
3132 case E_GOP4:
3133 {
3134 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3135 break;
3136 }
3137 default:
3138 {
3139 continue;
3140 }
3141 }
3142 if( ( u16GopMask & (1<<gop) ) )
3143 {
3144 _GetBnkOfstByGop(gop, &u32BankOffSet);
3145 if(bMIUSelect[gop] == TRUE)
3146 {
3147 if(u16MIUSelect[gop] == 0)
3148 {
3149 u16RegVal1 &= ~(1<<u16MiuClient);
3150 u16RegVal3 &= ~(1<<u16MiuClient);
3151 }
3152 else if(u16MIUSelect[gop] == 1)
3153 {
3154 u16RegVal1 |= (1<<u16MiuClient);
3155 u16RegVal3 &= ~(1<<u16MiuClient);
3156 }
3157 else if(u16MIUSelect[gop] == 2)
3158 {
3159 u16RegVal1 &= ~(1<<u16MiuClient);
3160 u16RegVal3 |= (1<<u16MiuClient);
3161 }
3162 else if(u16MIUSelect[gop] == 3)
3163 {
3164 u16RegVal1 |= (1<<u16MiuClient);
3165 u16RegVal3 |= (1<<u16MiuClient);
3166 }
3167 bMIUSelect[gop] = FALSE;
3168 }
3169 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3170 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3171 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3172 }
3173 }
3174 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_SC_MIU_SEL,u16RegVal1,0xFFFF);
3175 #ifdef GOP_MIU_GROUP2
3176 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3177 #endif
3178 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3179 return GOP_SUCCESS;
3180 }
3181 #endif
3182
3183 GOP_Result HAL_GOP_SetDbgLevel(EN_GOP_DEBUG_LEVEL level)
3184 {
3185 u32GOPDbgLevel_hal= level;
3186 return GOP_SUCCESS;
3187 }
3188