1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
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15 //
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17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2008 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (��MStar Confidential Information��) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
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89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 #include "MsCommon.h"
100 #include "MsTypes.h"
101 #include "drvMIU.h"
102 #include "regMIU.h"
103 #include "halMIU.h"
104 #include "halCHIP.h"
105
106 //-------------------------------------------------------------------------------------------------
107 // Driver Compiler Options
108 //-------------------------------------------------------------------------------------------------
109
110
111 //-------------------------------------------------------------------------------------------------
112 // Local Defines
113 //-------------------------------------------------------------------------------------------------
114 #define MIU_HAL_ERR(x, args...) {printf(x, ##args);}
115 #define HAL_MIU_SSC_DBG(x) // x
116
117 //[MIU][HAL][005] Update MIU Client Table [START]
118 #define MIU_CLIENT_GP0 \
119 /* 0 */ MIU_CLIENT_NONE, \
120 /* 1 */ MIU_CLIENT_VIVALDI9_DECODER_R, \
121 /* 2 */ MIU_CLIENT_SECAU_R2_RW, \
122 /* 3 */ MIU_CLIENT_USB3_RW,\
123 /* 4 */ MIU_CLIENT_SECURE_R2_RW,\
124 /* 5 */ MIU_CLIENT_AU_R2_RW, \
125 /* 6 */ MIU_CLIENT_VD_R2D_RW,\
126 /* 7 */ MIU_CLIENT_PM51_RW, \
127 /* 8 */ MIU_CLIENT_VD_R2I_R, \
128 /* 9 */ MIU_CLIENT_USB_UHC0_RW, \
129 /*10 */ MIU_CLIENT_USB_UHC1_RW, \
130 /*11 */ MIU_CLIENT_USB_UHC2_RW, \
131 /*12 */ MIU_CLIENT_MVD_BBU_RW, \
132 /*13 */ MIU_CLIENT_EMAC_RW, \
133 /*14 */ MIU_CLIENT_BDMA_RW, \
134 /*15 */ MIU_CLIENT_DUMMY
135
136 #define MIU_CLIENT_GP1 \
137 /* 0 */ MIU_CLIENT_VIVALDI9_MAD_RW, \
138 /* 1 */ MIU_CLIENT_DEMOD_W, \
139 /* 2 */ MIU_CLIENT_DUMMY, \
140 /* 3 */ MIU_CLIENT_JPD720P_RW, \
141 /* 4 */ MIU_CLIENT_FRC_R2, \
142 /* 5 */ MIU_CLIENT_MIIC0_RW,\
143 /* 6 */ MIU_CLIENT_UART_DMA_RW, \
144 /* 7 */ MIU_CLIENT_USB30_1_RW, \
145 /* 8 */ MIU_CLIENT_TSP_ORZ_W, \
146 /* 9 */ MIU_CLIENT_TSP_ORZ_R, \
147 /*10 */ MIU_CLIENT_DUMMY, \
148 /*11 */ MIU_CLIENT_VD_TTXSL_W, \
149 /*12 */ MIU_CLIENT_VD_COMB_W, \
150 /*13 */ MIU_CLIENT_VD_COMB_R, \
151 /*14 */ MIU_CLIENT_USB_UHC3_RW, \
152 /*15 */ MIU_CLIENT_DUMMY
153
154 #define MIU_CLIENT_GP2 \
155 /* 0 */ MIU_CLIENT_CMD_QUEUE_RW, \
156 /* 1 */ MIU_CLIENT_CMD_QUEUE1_RW, \
157 /* 2 */ MIU_CLIENT_DUMMY, \
158 /* 3 */ MIU_CLIENT_DUMMY, \
159 /* 4 */ MIU_CLIENT_MVD_RW, \
160 /* 5 */ MIU_CLIENT_AESDMA_RW, \
161 /* 6 */ MIU_CLIENT_GPD_RW, \
162 /* 7 */ MIU_CLIENT_MFE0_W, \
163 /* 8 */ MIU_CLIENT_MFE1_R, \
164 /* 9 */ MIU_CLIENT_NAND_RW, \
165 /*10 */ MIU_CLIENT_SDIO_RW, \
166 /*11 */ MIU_CLIENT_DSCRMB_RW, \
167 /*12 */ MIU_CLIENT_TSP_FIQ_RW, \
168 /*13 */ MIU_CLIENT_TSP_ORZ_W, \
169 /*14 */ MIU_CLIENT_TSP_ORZ_R,\
170 /*15 */ MIU_CLIENT_TSO_RW
171
172 #define MIU_CLIENT_GP3 \
173 /* 0 */ MIU_CLIENT_DUMMY, \
174 /* 1 */ MIU_CLIENT_DUMMY, \
175 /* 2 */ MIU_CLIENT_DUMMY, \
176 /* 3 */ MIU_CLIENT_DUMMY, \
177 /* 4 */ MIU_CLIENT_DUMMY, \
178 /* 5 */ MIU_CLIENT_DUMMY, \
179 /* 6 */ MIU_CLIENT_DUMMY, \
180 /* 7 */ MIU_CLIENT_DUMMY, \
181 /* 8 */ MIU_CLIENT_DUMMY, \
182 /* 9 */ MIU_CLIENT_DUMMY, \
183 /*10 */ MIU_CLIENT_DUMMY, \
184 /*11 */ MIU_CLIENT_DUMMY, \
185 /*12 */ MIU_CLIENT_DUMMY, \
186 /*13 */ MIU_CLIENT_DUMMY, \
187 /*14 */ MIU_CLIENT_DUMMY, \
188 /*15 */ MIU_CLIENT_DUMMY
189
190 #define MIU_CLIENT_GP4 \
191 /* 0 */ MIU_CLIENT_HVD_BBU_R, \
192 /* 1 */ MIU_CLIENT_GE_RW, \
193 /* 2 */ MIU_CLIENT_HVD_RW, \
194 /* 3 */ MIU_CLIENT_SECHVD_RW, \
195 /* 4 */ MIU_CLIENT_EVD_RW,\
196 /* 5 */ MIU_CLIENT_DUMMY, \
197 /* 6 */ MIU_CLIENT_MVD_RTO_RW, \
198 /* 7 */ MIU_CLIENT_DUMMY, \
199 /* 8 */ MIU_CLIENT_DUMMY, \
200 /* 9 */ MIU_CLIENT_DUMMY, \
201 /*10 */ MIU_CLIENT_DUMMY, \
202 /*11 */ MIU_CLIENT_DUMMY, \
203 /*12 */ MIU_CLIENT_DUMMY, \
204 /*13 */ MIU_CLIENT_DUMMY, \
205 /*14 */ MIU_CLIENT_DUMMY, \
206 /*15 */ MIU_CLIENT_DUMMY
207
208 /* FRC Support MIU1,2 only */
209 #define MIU_CLIENT_GP5 \
210 /* 0 */ MIU_CLIENT_DUMMY, \
211 /* 1 */ MIU_CLIENT_DUMMY, \
212 /* 2 */ MIU_CLIENT_DUMMY, \
213 /* 3 */ MIU_CLIENT_DUMMY, \
214 /* 4 */ MIU_CLIENT_DUMMY, \
215 /* 5 */ MIU_CLIENT_DUMMY, \
216 /* 6 */ MIU_CLIENT_DUMMY, \
217 /* 7 */ MIU_CLIENT_DUMMY, \
218 /* 8 */ MIU_CLIENT_DUMMY, \
219 /* 9 */ MIU_CLIENT_DUMMY, \
220 /*10 */ MIU_CLIENT_DUMMY, \
221 /*11 */ MIU_CLIENT_DUMMY, \
222 /*12 */ MIU_CLIENT_DUMMY, \
223 /*13 */ MIU_CLIENT_DUMMY, \
224 /*14 */ MIU_CLIENT_DUMMY, \
225 /*15 */ MIU_CLIENT_DUMMY
226
227 #define MIU_CLIENT_GP6 \
228 /* 0 */ MIU_CLIENT_SC_IPMAIN_RW, \
229 /* 1 */ MIU_CLIENT_SC_OPMAIN_RW, \
230 /* 2 */ MIU_CLIENT_MVOP_128BIT_R, \
231 /* 3 */ MIU_CLIENT_MFDEC_R, \
232 /* 4 */ MIU_CLIENT_SECMFDEC_R, \
233 /* 5 */ MIU_CLIENT_GOP0_R, \
234 /* 6 */ MIU_CLIENT_GOP1_R, \
235 /* 7 */ MIU_CLIENT_GOP2_R, \
236 /* 8 */ MIU_CLIENT_GOP3_R, \
237 /* 9 */ MIU_CLIENT_MC2D_RW, \
238 /*10 */ MIU_CLIENT_T3D_RW, \
239 /*11 */ MIU_CLIENT_VE_W, \
240 /*12 */ MIU_CLIENT_SC1_OPMAIN_RW, \
241 /*13 */ MIU_CLIENT_SC_OD_RW, \
242 /*14 */ MIU_CLIENT_SC1_IPMAIN_RW, \
243 /*15 */ MIU_CLIENT_SC_IPMAIN2_RW
244
245 #define MIU_CLIENT_GP7 \
246 /* 0 */ MIU_CLIENT_MIPS_RW, \
247 /* 1 */ MIU_CLIENT_G3D_RW
248
249 #define MIU1_CLIENT_GP0 \
250 /* 0 */ MIU_CLIENT_NONE, \
251 /* 1 */ MIU_CLIENT_VIVALDI9_DECODER_R, \
252 /* 2 */ MIU_CLIENT_SECAU_R2_RW, \
253 /* 3 */ MIU_CLIENT_USB3_RW,\
254 /* 4 */ MIU_CLIENT_SECURE_R2_RW,\
255 /* 5 */ MIU_CLIENT_AU_R2_RW, \
256 /* 6 */ MIU_CLIENT_VD_R2D_RW,\
257 /* 7 */ MIU_CLIENT_PM51_RW, \
258 /* 8 */ MIU_CLIENT_VD_R2I_R, \
259 /* 9 */ MIU_CLIENT_USB_UHC0_RW, \
260 /*10 */ MIU_CLIENT_USB_UHC1_RW, \
261 /*11 */ MIU_CLIENT_USB_UHC2_RW, \
262 /*12 */ MIU_CLIENT_MVD_BBU_RW, \
263 /*13 */ MIU_CLIENT_EMAC_RW, \
264 /*14 */ MIU_CLIENT_BDMA_RW, \
265 /*15 */ MIU_CLIENT_DUMMY
266
267 #define MIU1_CLIENT_GP1 \
268 /* 0 */ MIU_CLIENT_VIVALDI9_MAD_RW, \
269 /* 1 */ MIU_CLIENT_DEMOD_W, \
270 /* 2 */ MIU_CLIENT_DUMMY, \
271 /* 3 */ MIU_CLIENT_JPD720P_RW, \
272 /* 4 */ MIU_CLIENT_FRC_R2, \
273 /* 5 */ MIU_CLIENT_MIIC0_RW,\
274 /* 6 */ MIU_CLIENT_UART_DMA_RW, \
275 /* 7 */ MIU_CLIENT_USB30_1_RW, \
276 /* 8 */ MIU_CLIENT_TSP_ORZ_W, \
277 /* 9 */ MIU_CLIENT_TSP_ORZ_R, \
278 /*10 */ MIU_CLIENT_DUMMY, \
279 /*11 */ MIU_CLIENT_VD_TTXSL_W, \
280 /*12 */ MIU_CLIENT_VD_COMB_W, \
281 /*13 */ MIU_CLIENT_VD_COMB_R, \
282 /*14 */ MIU_CLIENT_USB_UHC3_RW, \
283 /*15 */ MIU_CLIENT_DUMMY
284
285 #define MIU1_CLIENT_GP2 \
286 /* 0 */ MIU_CLIENT_CMD_QUEUE_RW, \
287 /* 1 */ MIU_CLIENT_CMD_QUEUE1_RW, \
288 /* 2 */ MIU_CLIENT_DUMMY, \
289 /* 3 */ MIU_CLIENT_DUMMY, \
290 /* 4 */ MIU_CLIENT_MVD_RW, \
291 /* 5 */ MIU_CLIENT_AESDMA_RW, \
292 /* 6 */ MIU_CLIENT_GPD_RW, \
293 /* 7 */ MIU_CLIENT_MFE0_W, \
294 /* 8 */ MIU_CLIENT_MFE1_R, \
295 /* 9 */ MIU_CLIENT_NAND_RW, \
296 /*10 */ MIU_CLIENT_SDIO_RW, \
297 /*11 */ MIU_CLIENT_DSCRMB_RW, \
298 /*12 */ MIU_CLIENT_TSP_FIQ_RW, \
299 /*13 */ MIU_CLIENT_TSP_ORZ_W, \
300 /*14 */ MIU_CLIENT_TSP_ORZ_R,\
301 /*15 */ MIU_CLIENT_TSO_RW
302
303 #define MIU1_CLIENT_GP3 \
304 /* 0 */ MIU_CLIENT_DUMMY, \
305 /* 1 */ MIU_CLIENT_DUMMY, \
306 /* 2 */ MIU_CLIENT_DUMMY, \
307 /* 3 */ MIU_CLIENT_DUMMY, \
308 /* 4 */ MIU_CLIENT_DUMMY, \
309 /* 5 */ MIU_CLIENT_DUMMY, \
310 /* 6 */ MIU_CLIENT_DUMMY, \
311 /* 7 */ MIU_CLIENT_DUMMY, \
312 /* 8 */ MIU_CLIENT_DUMMY, \
313 /* 9 */ MIU_CLIENT_DUMMY, \
314 /*10 */ MIU_CLIENT_DUMMY, \
315 /*11 */ MIU_CLIENT_DUMMY, \
316 /*12 */ MIU_CLIENT_DUMMY, \
317 /*13 */ MIU_CLIENT_DUMMY, \
318 /*14 */ MIU_CLIENT_DUMMY, \
319 /*15 */ MIU_CLIENT_DUMMY
320
321 #define MIU1_CLIENT_GP4 \
322 /* 0 */ MIU_CLIENT_HVD_BBU_R, \
323 /* 1 */ MIU_CLIENT_GE_RW, \
324 /* 2 */ MIU_CLIENT_HVD_RW, \
325 /* 3 */ MIU_CLIENT_SECHVD_RW, \
326 /* 4 */ MIU_CLIENT_EVD_RW,\
327 /* 5 */ MIU_CLIENT_DUMMY, \
328 /* 6 */ MIU_CLIENT_MVD_RTO_RW, \
329 /* 7 */ MIU_CLIENT_DUMMY, \
330 /* 8 */ MIU_CLIENT_DUMMY, \
331 /* 9 */ MIU_CLIENT_DUMMY, \
332 /*10 */ MIU_CLIENT_DUMMY, \
333 /*11 */ MIU_CLIENT_DUMMY, \
334 /*12 */ MIU_CLIENT_DUMMY, \
335 /*13 */ MIU_CLIENT_DUMMY, \
336 /*14 */ MIU_CLIENT_DUMMY, \
337 /*15 */ MIU_CLIENT_DUMMY
338
339 #define MIU1_CLIENT_GP5 \
340 /* 0 */ MIU_CLIENT_FRC_FSCM2_RW, \
341 /* 1 */ MIU_CLIENT_FRC_FSCM3_RW, \
342 /* 2 */ MIU_CLIENT_FRC_IPM0_W, \
343 /* 3 */ MIU_CLIENT_FRC_IPM1_W, \
344 /* 4 */ MIU_CLIENT_FRC_OPM0_R, \
345 /* 5 */ MIU_CLIENT_FRC_OPM1_R, \
346 /* 6 */ MIU_CLIENT_FRC_OPME0_R, \
347 /* 7 */ MIU_CLIENT_FRC_OPME1_R, \
348 /* 8 */ MIU_CLIENT_FRC_OPMI0_R, \
349 /* 9 */ MIU_CLIENT_FRC_OPMI1_R, \
350 /*10 */ MIU_CLIENT_FRC_ME_W, \
351 /*11 */ MIU_CLIENT_FRC_ME_R, \
352 /*12 */ MIU_CLIENT_FRC_HR_W, \
353 /*13 */ MIU_CLIENT_FRC_HR_R, \
354 /*14 */ MIU_CLIENT_FRC_MI_MERGE_RW, \
355 /*15 */ MIU_CLIENT_DUMMY
356
357 #define MIU1_CLIENT_GP6 \
358 /* 0 */ MIU_CLIENT_SC_IPMAIN_RW, \
359 /* 1 */ MIU_CLIENT_SC_OPMAIN_RW, \
360 /* 2 */ MIU_CLIENT_MVOP_128BIT_R, \
361 /* 3 */ MIU_CLIENT_MFDEC_R, \
362 /* 4 */ MIU_CLIENT_SECMFDEC_R, \
363 /* 5 */ MIU_CLIENT_GOP0_R, \
364 /* 6 */ MIU_CLIENT_GOP1_R, \
365 /* 7 */ MIU_CLIENT_GOP2_R, \
366 /* 8 */ MIU_CLIENT_GOP3_R, \
367 /* 9 */ MIU_CLIENT_MC2D_RW, \
368 /*10 */ MIU_CLIENT_T3D_RW, \
369 /*11 */ MIU_CLIENT_VE_W, \
370 /*12 */ MIU_CLIENT_SC1_OPMAIN_RW, \
371 /*13 */ MIU_CLIENT_SC_OD_RW, \
372 /*14 */ MIU_CLIENT_SC1_IPMAIN_RW, \
373 /*15 */ MIU_CLIENT_SC_IPMAIN2_RW
374
375 #define MIU1_CLIENT_GP7 \
376 /* 0 */ MIU_CLIENT_MIPS_RW, \
377 /* 1 */ MIU_CLIENT_G3D_RW
378
379 #define MIU2_CLIENT_GP0 \
380 /* 0 */ MIU_CLIENT_NONE, \
381 /* 1 */ MIU_CLIENT_DUMMY, \
382 /* 2 */ MIU_CLIENT_DUMMY, \
383 /* 3 */ MIU_CLIENT_USB3_RW,\
384 /* 4 */ MIU_CLIENT_SECURE_R2_RW,\
385 /* 5 */ MIU_CLIENT_DUMMY, \
386 /* 6 */ MIU_CLIENT_VD_R2D_RW,\
387 /* 7 */ MIU_CLIENT_PM51_RW, \
388 /* 8 */ MIU_CLIENT_VD_R2I_R, \
389 /* 9 */ MIU_CLIENT_USB_UHC0_RW, \
390 /*10 */ MIU_CLIENT_USB_UHC1_RW, \
391 /*11 */ MIU_CLIENT_USB_UHC2_RW, \
392 /*12 */ MIU_CLIENT_MVD_BBU_RW, \
393 /*13 */ MIU_CLIENT_DUMMY, \
394 /*14 */ MIU_CLIENT_BDMA_RW, \
395 /*15 */ MIU_CLIENT_DUMMY
396
397 #define MIU2_CLIENT_GP1 \
398 /* 0 */ MIU_CLIENT_DUMMY, \
399 /* 1 */ MIU_CLIENT_DUMMY, \
400 /* 2 */ MIU_CLIENT_DUMMY, \
401 /* 3 */ MIU_CLIENT_JPD720P_RW, \
402 /* 4 */ MIU_CLIENT_FRC_R2, \
403 /* 5 */ MIU_CLIENT_MIIC0_RW,\
404 /* 6 */ MIU_CLIENT_UART_DMA_RW, \
405 /* 7 */ MIU_CLIENT_USB30_1_RW, \
406 /* 8 */ MIU_CLIENT_DUMMY, \
407 /* 9 */ MIU_CLIENT_DUMMY, \
408 /*10 */ MIU_CLIENT_DUMMY, \
409 /*11 */ MIU_CLIENT_DUMMY, \
410 /*12 */ MIU_CLIENT_DUMMY, \
411 /*13 */ MIU_CLIENT_DUMMY, \
412 /*14 */ MIU_CLIENT_USB_UHC3_RW, \
413 /*15 */ MIU_CLIENT_DUMMY
414
415 #define MIU2_CLIENT_GP2 \
416 /* 0 */ MIU_CLIENT_CMD_QUEUE_RW, \
417 /* 1 */ MIU_CLIENT_CMD_QUEUE1_RW, \
418 /* 2 */ MIU_CLIENT_DUMMY, \
419 /* 3 */ MIU_CLIENT_DUMMY, \
420 /* 4 */ MIU_CLIENT_MVD_RW, \
421 /* 5 */ MIU_CLIENT_AESDMA_RW, \
422 /* 6 */ MIU_CLIENT_DUMMY, \
423 /* 7 */ MIU_CLIENT_MFE0_W, \
424 /* 8 */ MIU_CLIENT_MFE1_R, \
425 /* 9 */ MIU_CLIENT_NAND_RW, \
426 /*10 */ MIU_CLIENT_SDIO_RW, \
427 /*11 */ MIU_CLIENT_DSCRMB_RW, \
428 /*12 */ MIU_CLIENT_DUMMY, \
429 /*13 */ MIU_CLIENT_DUMMY, \
430 /*14 */ MIU_CLIENT_DUMMY,\
431 /*15 */ MIU_CLIENT_DUMMY
432
433 #define MIU2_CLIENT_GP3 \
434 /* 0 */ MIU_CLIENT_DUMMY, \
435 /* 1 */ MIU_CLIENT_DUMMY, \
436 /* 2 */ MIU_CLIENT_DUMMY, \
437 /* 3 */ MIU_CLIENT_DUMMY, \
438 /* 4 */ MIU_CLIENT_DUMMY, \
439 /* 5 */ MIU_CLIENT_DUMMY, \
440 /* 6 */ MIU_CLIENT_DUMMY, \
441 /* 7 */ MIU_CLIENT_DUMMY, \
442 /* 8 */ MIU_CLIENT_DUMMY, \
443 /* 9 */ MIU_CLIENT_DUMMY, \
444 /*10 */ MIU_CLIENT_DUMMY, \
445 /*11 */ MIU_CLIENT_DUMMY, \
446 /*12 */ MIU_CLIENT_DUMMY, \
447 /*13 */ MIU_CLIENT_DUMMY, \
448 /*14 */ MIU_CLIENT_DUMMY, \
449 /*15 */ MIU_CLIENT_DUMMY
450
451 #define MIU2_CLIENT_GP4 \
452 /* 0 */ MIU_CLIENT_DUMMY, \
453 /* 1 */ MIU_CLIENT_GE_RW, \
454 /* 2 */ MIU_CLIENT_DUMMY, \
455 /* 3 */ MIU_CLIENT_DUMMY, \
456 /* 4 */ MIU_CLIENT_DUMMY, \
457 /* 5 */ MIU_CLIENT_DUMMY, \
458 /* 6 */ MIU_CLIENT_MVD_RTO_RW, \
459 /* 7 */ MIU_CLIENT_DUMMY, \
460 /* 8 */ MIU_CLIENT_DUMMY, \
461 /* 9 */ MIU_CLIENT_DUMMY, \
462 /*10 */ MIU_CLIENT_DUMMY, \
463 /*11 */ MIU_CLIENT_DUMMY, \
464 /*12 */ MIU_CLIENT_DUMMY, \
465 /*13 */ MIU_CLIENT_DUMMY, \
466 /*14 */ MIU_CLIENT_DUMMY, \
467 /*15 */ MIU_CLIENT_DUMMY
468
469 #define MIU2_CLIENT_GP5 \
470 /* 0 */ MIU_CLIENT_FRC_FSCM2_RW, \
471 /* 1 */ MIU_CLIENT_FRC_FSCM3_RW, \
472 /* 2 */ MIU_CLIENT_FRC_IPM0_W, \
473 /* 3 */ MIU_CLIENT_FRC_IPM1_W, \
474 /* 4 */ MIU_CLIENT_FRC_OPM0_R, \
475 /* 5 */ MIU_CLIENT_FRC_OPM1_R, \
476 /* 6 */ MIU_CLIENT_FRC_OPME0_R, \
477 /* 7 */ MIU_CLIENT_FRC_OPME1_R, \
478 /* 8 */ MIU_CLIENT_FRC_OPMI0_R, \
479 /* 9 */ MIU_CLIENT_FRC_OPMI1_R, \
480 /*10 */ MIU_CLIENT_FRC_ME_W, \
481 /*11 */ MIU_CLIENT_FRC_ME_R, \
482 /*12 */ MIU_CLIENT_FRC_HR_W, \
483 /*13 */ MIU_CLIENT_FRC_HR_R, \
484 /*14 */ MIU_CLIENT_FRC_MI_MERGE_RW, \
485 /*15 */ MIU_CLIENT_DUMMY
486
487 #define MIU2_CLIENT_GP6 \
488 /* 0 */ MIU_CLIENT_SC_IPMAIN_RW, \
489 /* 1 */ MIU_CLIENT_SC_OPMAIN_RW, \
490 /* 2 */ MIU_CLIENT_MVOP_128BIT_R, \
491 /* 3 */ MIU_CLIENT_MFDEC_R, \
492 /* 4 */ MIU_CLIENT_SECMFDEC_R, \
493 /* 5 */ MIU_CLIENT_GOP0_R, \
494 /* 6 */ MIU_CLIENT_GOP1_R, \
495 /* 7 */ MIU_CLIENT_GOP2_R, \
496 /* 8 */ MIU_CLIENT_GOP3_R, \
497 /* 9 */ MIU_CLIENT_MC2D_RW, \
498 /*10 */ MIU_CLIENT_T3D_RW, \
499 /*11 */ MIU_CLIENT_VE_W, \
500 /*12 */ MIU_CLIENT_SC1_OPMAIN_RW, \
501 /*13 */ MIU_CLIENT_SC_OD_RW, \
502 /*14 */ MIU_CLIENT_SC1_IPMAIN_RW, \
503 /*15 */ MIU_CLIENT_SC_IPMAIN2_RW
504
505 #define MIU2_CLIENT_GP7 \
506 /* 0 */ MIU_CLIENT_MIPS_RW, \
507 /* 1 */ MIU_CLIENT_G3D_RW
508 //[MIU][HAL][005] Update MIU Client Table [END]
509
510 #define KHz (1000UL)
511 #define MHz (1000000UL)
512 #define MPPL (432)
513 #define DDR_FACTOR (524288)
514 #define DDFSPAN_FACTOR (131072)
515 #define IDNUM_KERNELPROTECT (8)
516
517 //-------------------------------------------------------------------------------------------------
518 // Local Structures
519 //-------------------------------------------------------------------------------------------------
520 //[MIU][HAL][006] Check data structure of MIU client table [START]
521 const eMIUClientID clientTbl[MIU_MAX_DEVICE][MIU_MAX_TBL_CLIENT] =
522 {
523 {MIU_CLIENT_GP0, MIU_CLIENT_GP1, MIU_CLIENT_GP2, MIU_CLIENT_GP3, MIU_CLIENT_GP4, MIU_CLIENT_GP5, MIU_CLIENT_GP6, MIU_CLIENT_GP7}
524 ,{MIU1_CLIENT_GP0, MIU1_CLIENT_GP1, MIU1_CLIENT_GP2, MIU1_CLIENT_GP3, MIU1_CLIENT_GP4, MIU1_CLIENT_GP5, MIU1_CLIENT_GP6, MIU1_CLIENT_GP7}
525 ,{MIU2_CLIENT_GP0, MIU2_CLIENT_GP1, MIU2_CLIENT_GP2, MIU2_CLIENT_GP3, MIU2_CLIENT_GP4, MIU2_CLIENT_GP5, MIU2_CLIENT_GP6, MIU2_CLIENT_GP7}
526 };
527 //[MIU][HAL][006] Check data structure of MIU client table [END]
528
529 //[MIU][HAL][007] Check kernel protect table [START]
530 MS_U8 clientId_KernelProtect[IDNUM_KERNELPROTECT] =
531 {
532 MIU_CLIENT_MIPS_RW, MIU_CLIENT_NAND_RW, MIU_CLIENT_USB_UHC0_RW, MIU_CLIENT_USB_UHC1_RW,
533 MIU_CLIENT_USB_UHC2_RW, MIU_CLIENT_NONE, MIU_CLIENT_NONE, MIU_CLIENT_NONE
534 };
535 //[MIU][HAL][007] Check kernel protect table [END]
536 //-------------------------------------------------------------------------------------------------
537 // Global Variables
538 //-------------------------------------------------------------------------------------------------
539
540 //-------------------------------------------------------------------------------------------------
541 // Local Variables
542 //-------------------------------------------------------------------------------------------------
543 static MS_VIRT _gMIU_MapBase = 0xBF200000; //default set to MIPS platfrom
544 static MS_VIRT _gPM_MapBase = 0xBF000000; //default set to MIPS platfrom
545
546 MS_BOOL IDEnables[MIU_MAX_DEVICE][MIU_MAX_PROTECT_BLOCK][MIU_MAX_PROTECT_ID] = {{{0},{0},{0},{0}}, {{0},{0},{0},{0}}, {{0},{0},{0},{0}}}; //ID enable for protect block 0~3
547 MS_U32 IDs[MIU_MAX_DEVICE][MIU_MAX_PROTECT_ID] = {{0}, {0}, {0}}; //IDs for protection
548 //-------------------------------------------------------------------------------------------------
549 // Debug Functions
550 //-------------------------------------------------------------------------------------------------
551
552 //-------------------------------------------------------------------------------------------------
553 // Local Functions
554 //-------------------------------------------------------------------------------------------------
555
556 //-------------------------------------------------------------------------------------------------
557 // Type and Structure Declaration
558 //-------------------------------------------------------------------------------------------------
559
560 //-------------------------------------------------------------------------------------------------
561 // Global Functions
562 //-------------------------------------------------------------------------------------------------
HAL_MIU_SetIOMapBase(MS_VIRT virtBase)563 void HAL_MIU_SetIOMapBase(MS_VIRT virtBase)
564 {
565 _gMIU_MapBase = virtBase;
566 HAL_MIU_SSC_DBG(printf("MIU _gMIU_MapBase= %lx\n", _gMIU_MapBase));
567 }
568
HAL_MIU_SetPMIOMapBase(MS_VIRT virtBase)569 void HAL_MIU_SetPMIOMapBase(MS_VIRT virtBase)
570 {
571 _gPM_MapBase = virtBase;
572 HAL_MIU_SSC_DBG(printf("MIU _gPM_MapBase= %lx\n", _gPM_MapBase));
573 }
574
HAL_MIU_GetClientInfo(MS_U8 u8MiuDev,eMIUClientID eClientID)575 MS_S16 HAL_MIU_GetClientInfo(MS_U8 u8MiuDev, eMIUClientID eClientID)
576 {
577 MS_U8 idx;
578
579 if (MIU_MAX_DEVICE <= u8MiuDev)
580 {
581 printf("Wrong MIU device:%u\n", u8MiuDev);
582 return (-1);
583 }
584
585 for (idx = 0; idx < MIU_MAX_TBL_CLIENT; idx++)
586 if (eClientID == clientTbl[u8MiuDev][idx])
587 return idx;
588 return (-1);
589 }
590
591 ////////////////////////////////////////////////////////////////////////////////
592 /// @brief \b Function \b Name: HAL_MIU_ReadByte
593 /// @brief \b Function \b Description: read 1 Byte data
594 /// @param <IN> \b u32RegAddr: register address
595 /// @param <OUT> \b None :
596 /// @param <RET> \b MS_U8
597 /// @param <GLOBAL> \b None :
598 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ReadByte(MS_U32 u32RegAddr)599 MS_U8 HAL_MIU_ReadByte(MS_U32 u32RegAddr)
600 {
601 return ((volatile MS_U8*)(_gMIU_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
602 }
603
604
605 ////////////////////////////////////////////////////////////////////////////////
606 /// @brief \b Function \b Name: HAL_MIU_PM_ReadByte
607 /// @brief \b Function \b Description: read 1 Byte data
608 /// @param <IN> \b u32RegAddr: register address
609 /// @param <OUT> \b None :
610 /// @param <RET> \b MS_U8
611 /// @param <GLOBAL> \b None :
612 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_PM_ReadByte(MS_U32 u32RegAddr)613 MS_U8 HAL_MIU_PM_ReadByte(MS_U32 u32RegAddr)
614 {
615 return ((volatile MS_U8*)(_gPM_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)];
616 }
617
618 ////////////////////////////////////////////////////////////////////////////////
619 /// @brief \b Function \b Name: HAL_MIU_Read4Byte
620 /// @brief \b Function \b Description: read 2 Byte data
621 /// @param <IN> \b u32RegAddr: register address
622 /// @param <OUT> \b None :
623 /// @param <RET> \b MS_U16
624 /// @param <GLOBAL> \b None :
625 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Read2Byte(MS_U32 u32RegAddr)626 MS_U16 HAL_MIU_Read2Byte(MS_U32 u32RegAddr)
627 {
628 return ((volatile MS_U16*)(_gMIU_MapBase))[u32RegAddr];
629 }
630
631
632 ////////////////////////////////////////////////////////////////////////////////
633 /// @brief \b Function \b Name: HAL_MIU_Read4Byte
634 /// @brief \b Function \b Description: read 4 Byte data
635 /// @param <IN> \b u32RegAddr: register address
636 /// @param <OUT> \b None :
637 /// @param <RET> \b MS_U32
638 /// @param <GLOBAL> \b None :
639 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Read4Byte(MS_U32 u32RegAddr)640 MS_U32 HAL_MIU_Read4Byte(MS_U32 u32RegAddr)
641 {
642 return (HAL_MIU_Read2Byte(u32RegAddr) | HAL_MIU_Read2Byte(u32RegAddr+2) << 16);
643 }
644
645
646 ////////////////////////////////////////////////////////////////////////////////
647 /// @brief \b Function \b Name: HAL_MIU_WriteByte
648 /// @brief \b Function \b Description: write 1 Byte data
649 /// @param <IN> \b u32RegAddr: register address
650 /// @param <IN> \b u8Val : 1 byte data
651 /// @param <OUT> \b None :
652 /// @param <RET> \b TRUE: Ok FALSE: Fail
653 /// @param <GLOBAL> \b None :
654 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_WriteByte(MS_U32 u32RegAddr,MS_U8 u8Val)655 MS_BOOL HAL_MIU_WriteByte(MS_U32 u32RegAddr, MS_U8 u8Val)
656 {
657 if (!u32RegAddr)
658 {
659 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
660 return FALSE;
661 }
662
663 ((volatile MS_U8*)(_gMIU_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val;
664 return TRUE;
665 }
666
667
668 ////////////////////////////////////////////////////////////////////////////////
669 /// @brief \b Function \b Name: HAL_MIU_Write2Byte
670 /// @brief \b Function \b Description: write 2 Byte data
671 /// @param <IN> \b u32RegAddr: register address
672 /// @param <IN> \b u16Val : 2 byte data
673 /// @param <OUT> \b None :
674 /// @param <RET> \b TRUE: Ok FALSE: Fail
675 /// @param <GLOBAL> \b None :
676 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Write2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)677 MS_BOOL HAL_MIU_Write2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
678 {
679 if (!u32RegAddr)
680 {
681 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
682 return FALSE;
683 }
684
685 ((volatile MS_U16*)(_gMIU_MapBase))[u32RegAddr] = u16Val;
686 return TRUE;
687 }
688
689
690 ////////////////////////////////////////////////////////////////////////////////
691 /// @brief \b Function \b Name: HAL_BDMA_Write4Byte
692 /// @brief \b Function \b Description: write 4 Byte data
693 /// @param <IN> \b u32RegAddr: register address
694 /// @param <IN> \b u32Val : 4 byte data
695 /// @param <OUT> \b None :
696 /// @param <RET> \b TRUE: Ok FALSE: Fail
697 /// @param <GLOBAL> \b None :
698 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Write4Byte(MS_U32 u32RegAddr,MS_U32 u32Val)699 MS_BOOL HAL_MIU_Write4Byte(MS_U32 u32RegAddr, MS_U32 u32Val)
700 {
701 if (!u32RegAddr)
702 {
703 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
704 return FALSE;
705 }
706
707 HAL_MIU_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF);
708 HAL_MIU_Write2Byte(u32RegAddr+2, u32Val >> 16);
709 return TRUE;
710 }
711
712
713 ////////////////////////////////////////////////////////////////////////////////
714 /// @brief \b Function \b Name: HAL_BDMA_WriteByte
715 /// @brief \b Function \b Description: write 1 Byte data
716 /// @param <IN> \b u32RegAddr: register address
717 /// @param <IN> \b u8Val : 1 byte data
718 /// @param <OUT> \b None :
719 /// @param <RET> \b TRUE: Ok FALSE: Fail
720 /// @param <GLOBAL> \b None :
721 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_WriteRegBit(MS_U32 u32RegAddr,MS_U8 u8Mask,MS_BOOL bEnable)722 MS_BOOL HAL_MIU_WriteRegBit(MS_U32 u32RegAddr, MS_U8 u8Mask, MS_BOOL bEnable)
723 {
724 MS_U8 u8Val = HAL_MIU_ReadByte(u32RegAddr);
725 if (!u32RegAddr)
726 {
727 MIU_HAL_ERR("%s reg error!\n", __FUNCTION__);
728 return FALSE;
729 }
730
731 u8Val = HAL_MIU_ReadByte(u32RegAddr);
732 u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask);
733 HAL_MIU_WriteByte(u32RegAddr, u8Val);
734 return TRUE;
735 }
736
HAL_MIU_Write2BytesBit(MS_U32 u32RegOffset,MS_BOOL bEnable,MS_U16 u16Mask)737 void HAL_MIU_Write2BytesBit(MS_U32 u32RegOffset, MS_BOOL bEnable, MS_U16 u16Mask)
738 {
739 MS_U16 val = HAL_MIU_Read2Byte(u32RegOffset);
740 val = (bEnable) ? (val | u16Mask) : (val & ~u16Mask);
741 HAL_MIU_Write2Byte(u32RegOffset, val);
742 }
743
HAL_MIU_SetProtectID(MS_U32 u32Reg,MS_U8 u8MiuDev,MS_U32 u32ClientID)744 void HAL_MIU_SetProtectID(MS_U32 u32Reg, MS_U8 u8MiuDev, MS_U32 u32ClientID)
745 {
746 MS_S16 sVal = HAL_MIU_GetClientInfo(u8MiuDev, (eMIUClientID)u32ClientID);
747 MS_S16 sIDVal;
748
749 if (0 > sVal)
750 sVal = 0;
751
752 sIDVal = HAL_MIU_ReadByte(u32Reg);
753 sIDVal &= 0x80;
754 sIDVal |= sVal;
755 HAL_MIU_WriteByte(u32Reg, sIDVal);
756
757 }
758
HAL_MIU_SetGroupID(MS_U8 u8MiuSel,MS_U8 u8Blockx,MS_U8 * pu8ProtectId,MS_U32 u32RegAddrID,MS_U32 u32RegAddrIDenable)759 MS_BOOL HAL_MIU_SetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegAddrIDenable)
760 {
761 MS_U32 u32index0, u32index1;
762 MS_U8 u8ID;
763 MS_U8 u8isfound0, u8isfound1;
764 MS_U16 u16idenable;
765
766 //reset IDenables for protect u8Blockx
767 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
768 {
769 IDEnables[u8MiuSel][u8Blockx][u32index0] = 0;
770 }
771
772 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
773 {
774 u8ID = pu8ProtectId[u32index0];
775
776 //Unused ID
777 if(u8ID == 0)
778 continue;
779
780 u8isfound0 = FALSE;
781
782 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++)
783 {
784 if(IDs[u8MiuSel][u32index1] == u8ID)
785 {
786 //ID reused former setting
787 IDEnables[u8MiuSel][u8Blockx][u32index1] = 1;
788 u8isfound0 = TRUE;
789 break;
790 }
791 }
792
793
794 //Need to create new ID in IDs
795 if(u8isfound0 != TRUE)
796 {
797 u8isfound1 = FALSE;
798
799 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_ID; u32index1++)
800 {
801 if(IDs[u8MiuSel][u32index1] == 0)
802 {
803 IDs[u8MiuSel][u32index1] = u8ID;
804 IDEnables[u8MiuSel][u8Blockx][u32index1] = 1;
805 u8isfound1 = TRUE;
806 break;
807 }
808 }
809
810 //ID overflow
811 if(u8isfound1 == FALSE)
812 return FALSE;
813 }
814 }
815
816 u16idenable = 0;
817
818 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
819 {
820 if(IDEnables[u8MiuSel][u8Blockx][u32index0] == 1)
821 u16idenable |= (1<<u32index0);
822 }
823
824 HAL_MIU_Write2Byte(u32RegAddrIDenable, u16idenable);
825
826 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
827 {
828 HAL_MIU_SetProtectID(u32RegAddrID + u32index0, u8MiuSel, IDs[u8MiuSel][u32index0]);
829 }
830
831 return TRUE;
832 }
833
HAL_MIU_SetGroupID2(MS_U8 u8MiuSel,MS_U8 u8Blockx,MS_U32 * pu32ProtectId,MS_U32 u32RegAddrID,MS_U32 u32RegAddrIDenable)834 MS_BOOL HAL_MIU_SetGroupID2(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U32 *pu32ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegAddrIDenable)
835 {
836 return TRUE;
837 }
838
839
HAL_MIU_ResetGroupID(MS_U8 u8MiuSel,MS_U8 u8Blockx,MS_U8 * pu8ProtectId,MS_U32 u32RegAddrID,MS_U32 u32RegAddrIDenable)840 MS_BOOL HAL_MIU_ResetGroupID(MS_U8 u8MiuSel, MS_U8 u8Blockx, MS_U8 *pu8ProtectId, MS_U32 u32RegAddrID, MS_U32 u32RegAddrIDenable)
841 {
842 MS_U32 u32index0, u32index1;
843 MS_U8 u8isIDNoUse;
844 MS_U16 u16idenable;
845
846 //reset IDenables for protect u8Blockx
847 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
848 {
849 IDEnables[u8MiuSel][u8Blockx][u32index0] = 0;
850 }
851
852 u16idenable = 0x0;
853
854 HAL_MIU_Write2Byte(u32RegAddrIDenable, u16idenable);
855
856 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
857 {
858 u8isIDNoUse = FALSE;
859
860 for(u32index1 = 0; u32index1 < MIU_MAX_PROTECT_BLOCK; u32index1++)
861 {
862 if(IDEnables[u8MiuSel][u32index1][u32index0] == 1)
863 {
864 //protect ID is still be used
865 u8isIDNoUse = FALSE;
866 break;
867 }
868 u8isIDNoUse = TRUE;
869 }
870
871 if(u8isIDNoUse == TRUE)
872 IDs[u8MiuSel][u32index0] = 0;
873 }
874
875 for(u32index0 = 0; u32index0 < MIU_MAX_PROTECT_ID; u32index0++)
876 {
877 HAL_MIU_SetProtectID(u32RegAddrID + u32index0, u8MiuSel, IDs[u8MiuSel][u32index0]);
878 }
879
880 return TRUE;
881 }
882
883 ////////////////////////////////////////////////////////////////////////////////
884 /// @brief \b Function \b Name: HAL_MIU_GetDefaultClientID_KernelProtect()
885 /// @brief \b Function \b Description: Get default client id array pointer for protect kernel
886 /// @param <RET> \b : The pointer of Array of client IDs
887 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GetDefaultClientID_KernelProtect()888 MS_U8* HAL_MIU_GetDefaultClientID_KernelProtect()
889 {
890 if(IDNUM_KERNELPROTECT > 0)
891 return (MS_U8 *)&clientId_KernelProtect[0];
892
893 return NULL;
894 }
895
896 ////////////////////////////////////////////////////////////////////////////////
897 /// @brief \b Function \b Name: HAL_MIU_ProtectAlign()
898 /// @brief \b Function \b Description: Get the page shift for MIU protect
899 /// @param <*u32PageShift>\b IN: Page shift
900 /// @param <RET> \b OUT: None
901 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ProtectAlign(void)902 MS_U32 HAL_MIU_ProtectAlign(void)
903 {
904 MS_U32 u32PageShift;
905
906 u32PageShift = MIU_PAGE_SHIFT;
907 return u32PageShift;
908 }
909
910 ////////////////////////////////////////////////////////////////////////////////
911 /// @brief \b Function \b Name: HAL_MIU_Dram_Size()
912 /// @brief \b Function \b Description: Set up Dram size for MIU protect
913 /// @param MiuID \b IN : MIU ID
914 /// @param DramSize \b IN : Specified Dram size for MIU protect
915 /// @param <OUT> \b None :
916 /// @param <RET> \b None :
917 /// @param <GLOBAL> \b None :
918 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Dram_Size(MS_U8 MiuID,MS_U8 DramSize)919 MS_BOOL HAL_MIU_Dram_Size(MS_U8 MiuID, MS_U8 DramSize)
920 {
921 MS_U32 u32RegAddr;
922
923
924 if(E_MIU_2 == (MIU_ID)MiuID)
925 {
926 u32RegAddr = MIU2_PROTECT_DDR_SIZE;
927 switch (DramSize)
928 {
929 case E_MIU_DDR_32MB:
930 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_32MB);
931 break;
932 case E_MIU_DDR_64MB:
933 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_64MB);
934 break;
935 case E_MIU_DDR_128MB:
936 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_128MB);
937 break;
938 case E_MIU_DDR_256MB:
939 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_256MB);
940 break;
941 case E_MIU_DDR_512MB:
942 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_512MB);
943 break;
944 case E_MIU_DDR_1024MB:
945 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_1024MB);
946 break;
947 case E_MIU_DDR_2048MB:
948 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_2048MB);
949 break;
950 case E_MIU_DDR_4096MB:
951 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_4096MB);
952 break;
953 case E_MIU_DDR_8192MB:
954 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_8192MB);
955 break;
956 default:
957 return false;
958 }
959 }
960 else if(E_MIU_1 == (MIU_ID)MiuID)
961 {
962 u32RegAddr = MIU1_PROTECT_DDR_SIZE;
963 switch (DramSize)
964 {
965 case E_MIU_DDR_32MB:
966 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_32MB);
967 break;
968 case E_MIU_DDR_64MB:
969 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_64MB);
970 break;
971 case E_MIU_DDR_128MB:
972 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_128MB);
973 break;
974 case E_MIU_DDR_256MB:
975 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_256MB);
976 break;
977 case E_MIU_DDR_512MB:
978 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_512MB);
979 break;
980 case E_MIU_DDR_1024MB:
981 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_1024MB);
982 break;
983 case E_MIU_DDR_2048MB:
984 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_2048MB);
985 break;
986 case E_MIU_DDR_4096MB:
987 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_4096MB);
988 break;
989 case E_MIU_DDR_8192MB:
990 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_8192MB);
991 break;
992 default:
993 return false;
994 }
995 }
996 else if(E_MIU_0 == (MIU_ID)MiuID)
997 {
998 u32RegAddr = MIU_PROTECT_DDR_SIZE;
999 switch (DramSize)
1000 {
1001 case E_MIU_DDR_32MB:
1002 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_32MB);
1003 break;
1004 case E_MIU_DDR_64MB:
1005 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_64MB);
1006 break;
1007 case E_MIU_DDR_128MB:
1008 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_128MB);
1009 break;
1010 case E_MIU_DDR_256MB:
1011 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_256MB);
1012 break;
1013 case E_MIU_DDR_512MB:
1014 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_512MB);
1015 break;
1016 case E_MIU_DDR_1024MB:
1017 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_1024MB);
1018 break;
1019 case E_MIU_DDR_2048MB:
1020 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_2048MB);
1021 break;
1022 case E_MIU_DDR_4096MB:
1023 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_4096MB);
1024 break;
1025 case E_MIU_DDR_8192MB:
1026 HAL_MIU_WriteByte(u32RegAddr, MIU_PROTECT_DDR_8192MB);
1027 break;
1028 default:
1029 return false;
1030 }
1031 }
1032 else
1033 {
1034 printf("%s not support MIU%u!\n", __FUNCTION__, MiuID );
1035 return FALSE;
1036 }
1037
1038 return true;
1039 }
1040
1041 ////////////////////////////////////////////////////////////////////////////////
1042 /// @brief \b Function \b Name: HAL_MIU_Dram_ReadSize()
1043 /// @brief \b Function \b Description: Set up Dram size for MIU protect
1044 /// @param MiuID \b IN : MIU ID
1045 /// @param DramSize \b IN : Specified Dram size for MIU protect
1046 /// @param <OUT> \b None :
1047 /// @param <RET> \b None :
1048 /// @param <GLOBAL> \b None :
1049 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Dram_ReadSize(MS_U8 MiuID,MIU_DDR_SIZE * pDramSize)1050 MS_BOOL HAL_MIU_Dram_ReadSize(MS_U8 MiuID, MIU_DDR_SIZE *pDramSize)
1051 {
1052 MS_U32 u32RegAddr;
1053 MS_U8 DramSize;
1054
1055 if (E_MIU_2 == (MIU_ID)MiuID)
1056 {
1057 u32RegAddr = MIU2_PROTECT_DDR_SIZE;
1058 }
1059 else if(E_MIU_1 == (MIU_ID)MiuID)
1060 {
1061 u32RegAddr = MIU1_PROTECT_DDR_SIZE;
1062 }
1063 else
1064 {
1065 u32RegAddr = MIU_PROTECT_DDR_SIZE;
1066 }
1067 DramSize = HAL_MIU_ReadByte(u32RegAddr);
1068 DramSize &= 0xF0;
1069 switch (DramSize)
1070 {
1071 case MIU_PROTECT_DDR_32MB:
1072 *pDramSize = E_MIU_DDR_32MB;
1073 break;
1074 case MIU_PROTECT_DDR_64MB:
1075 *pDramSize = E_MIU_DDR_64MB;
1076 break;
1077 case MIU_PROTECT_DDR_128MB:
1078 *pDramSize = E_MIU_DDR_128MB;
1079 break;
1080 case MIU_PROTECT_DDR_256MB:
1081 *pDramSize = E_MIU_DDR_256MB;
1082 break;
1083 case MIU_PROTECT_DDR_512MB:
1084 *pDramSize = E_MIU_DDR_512MB;
1085 break;
1086 case MIU_PROTECT_DDR_1024MB:
1087 *pDramSize = E_MIU_DDR_1024MB;
1088 break;
1089 case MIU_PROTECT_DDR_2048MB:
1090 *pDramSize = E_MIU_DDR_2048MB;
1091 break;
1092 case MIU_PROTECT_DDR_4096MB:
1093 *pDramSize = E_MIU_DDR_4096MB;
1094 break;
1095 case MIU_PROTECT_DDR_8192MB:
1096 *pDramSize = E_MIU_DDR_8192MB;
1097 break;
1098 default:
1099 return FALSE;
1100 }
1101 return TRUE;
1102 }
1103
1104 ////////////////////////////////////////////////////////////////////////////////
1105 /// @brief \b Function \b Name: MDrv_MIU_GetClinetNumber()
1106 /// @brief \b Function \b Description: Get the number of clients for specific MIU block
1107 /// @param DramSize \b IN : MIU Block to protect (0 ~ 3)
1108 /// @param <OUT> \b None :
1109 /// @param <RET> \b None :
1110 /// @param <GLOBAL> \b None :
1111 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ClinetNumber(MS_U8 u8Blockx)1112 MS_U8 HAL_MIU_ClinetNumber(MS_U8 u8Blockx)
1113 {
1114 MS_U8 u8ClientNumber;
1115
1116 switch (u8Blockx)
1117 {
1118 case E_MIU_BLOCK_0:
1119 u8ClientNumber = MIU_BLOCK0_CLIENT_NUMBER;
1120 break;
1121 case E_MIU_BLOCK_1:
1122 u8ClientNumber = MIU_BLOCK1_CLIENT_NUMBER;
1123 break;
1124 case E_MIU_BLOCK_2:
1125 u8ClientNumber = MIU_BLOCK2_CLIENT_NUMBER;
1126 break;
1127 case E_MIU_BLOCK_3:
1128 u8ClientNumber = MIU_BLOCK3_CLIENT_NUMBER;
1129 break;
1130 default:
1131 u8ClientNumber = 0;
1132 }
1133
1134 return u8ClientNumber;
1135 }
1136
1137 ////////////////////////////////////////////////////////////////////////////////
1138 /// @brief \b Function \b Name: HAL_MIU_Protect()
1139 /// @brief \b Function \b Description: Enable/Disable MIU Protection mode
1140 /// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4)
1141 /// @param *pu8ProtectId \b IN : Allow specified client IDs to write
1142 /// @param u32Start \b IN : Starting address
1143 /// @param u32End \b IN : End address
1144 /// @param bSetFlag \b IN : Disable or Enable MIU protection
1145 /// - -Disable(0)
1146 /// - -Enable(1)
1147 /// @param <OUT> \b None :
1148 /// @param <RET> \b None :
1149 /// @param <GLOBAL> \b None :
1150 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Protect(MS_U8 u8Blockx,MS_U8 * pu8ProtectId,MS_PHY phy64Start,MS_PHY phy64End,MS_BOOL bSetFlag)1151 MS_BOOL HAL_MIU_Protect(
1152 MS_U8 u8Blockx,
1153 MS_U8 *pu8ProtectId,
1154 MS_PHY phy64Start,
1155 MS_PHY phy64End,
1156 MS_BOOL bSetFlag
1157 )
1158 {
1159 MS_U32 u32RegAddr;
1160 MS_U32 u32Reg;
1161 MS_U32 u32RegAddrStar;
1162 MS_U32 u32RegAddrMSB;
1163 MS_U32 u32RegAddrIDenable;
1164 MS_U32 u32MiuProtectEn;
1165 MS_PHY phy64StartOffset;
1166 MS_PHY phy64EndOffset;
1167 MS_U16 u16Data;
1168 MS_U16 u16Data1;
1169 MS_U16 u16Data2;
1170 MS_U8 u8Data;
1171 MS_U8 u8MiuSel;
1172
1173 // Get MIU selection and offset
1174 _phy_to_miu_offset(u8MiuSel, phy64EndOffset, phy64End - 1) // minus 1 to avoid end address boundary issue
1175 _phy_to_miu_offset(u8MiuSel, phy64StartOffset, phy64Start)
1176
1177 phy64Start = phy64StartOffset;
1178 phy64End = phy64EndOffset + 1; // plus 1 back to get correct end offset
1179
1180 // Incorrect Block ID
1181 if(u8Blockx >= E_MIU_BLOCK_NUM)
1182 {
1183 MIU_HAL_ERR("Err: Out of the number of protect device\n")
1184 return false;
1185 }
1186 else if(((phy64Start & ((1 << MIU_PAGE_SHIFT) -1)) != 0) || ((phy64End & ((1 << MIU_PAGE_SHIFT) -1)) != 0))
1187 {
1188 MIU_HAL_ERR("Err: Protected address should be aligned to 8KB\n")
1189 return false;
1190 }
1191 else if(phy64Start >= phy64End)
1192 {
1193 MIU_HAL_ERR("Err: Start address is equal to or more than end address\n")
1194 return false;
1195 }
1196
1197
1198 //write_enable
1199 u8Data = 1 << u8Blockx;
1200 if(u8MiuSel == E_CHIP_MIU_0)
1201 {
1202 u32RegAddrMSB = MIU_PROTECT0_MSB;
1203 u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1204
1205 u32RegAddr = MIU_PROTECT0_ID0;
1206 u32MiuProtectEn=MIU_PROTECT_EN;
1207 u32Reg = MIU_REG_BASE;
1208
1209 switch (u8Blockx)
1210 {
1211 case E_MIU_BLOCK_0:
1212 u32RegAddrStar = MIU_PROTECT0_START;
1213 u32RegAddrIDenable = MIU_PROTECT0_ID_ENABLE;
1214 u16Data2 = (u16Data1 & 0xFFF0);
1215 break;
1216 case E_MIU_BLOCK_1:
1217 u32RegAddrStar = MIU_PROTECT1_START;
1218 u32RegAddrIDenable = MIU_PROTECT1_ID_ENABLE;
1219 u16Data2 = (u16Data1 & 0xFF0F);
1220 break;
1221 case E_MIU_BLOCK_2:
1222 u32RegAddrStar = MIU_PROTECT2_START;
1223 u32RegAddrIDenable = MIU_PROTECT2_ID_ENABLE;
1224 u16Data2 = (u16Data1 & 0xF0FF);
1225 break;
1226 case E_MIU_BLOCK_3:
1227 u32RegAddrStar = MIU_PROTECT3_START;
1228 u32RegAddrIDenable = MIU_PROTECT3_ID_ENABLE;
1229 u16Data2 = (u16Data1 & 0x0FFF);
1230 break;
1231 default:
1232 return false;
1233 }
1234 }
1235 else if(u8MiuSel == E_CHIP_MIU_1)
1236 {
1237 u32RegAddrMSB = MIU1_PROTECT0_MSB;
1238 u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1239
1240 u32RegAddr = MIU1_PROTECT0_ID0;
1241 u32MiuProtectEn=MIU1_PROTECT_EN;
1242 u32Reg = MIU1_REG_BASE;
1243
1244 switch (u8Blockx)
1245 {
1246 case E_MIU_BLOCK_0:
1247 u32RegAddrStar = MIU1_PROTECT0_START;
1248 u32RegAddrIDenable = MIU1_PROTECT0_ID_ENABLE;
1249 u16Data2 = (u16Data1 & 0xFFF0);
1250 break;
1251 case E_MIU_BLOCK_1:
1252 u32RegAddrStar = MIU1_PROTECT1_START;
1253 u32RegAddrIDenable = MIU1_PROTECT1_ID_ENABLE;
1254 u16Data2 = (u16Data1 & 0xFF0F);
1255 break;
1256 case E_MIU_BLOCK_2:
1257 u32RegAddrStar = MIU1_PROTECT2_START;
1258 u32RegAddrIDenable = MIU1_PROTECT2_ID_ENABLE;
1259 u16Data2 = (u16Data1 & 0xF0FF);
1260 break;
1261 case E_MIU_BLOCK_3:
1262 u32RegAddrStar = MIU1_PROTECT3_START;
1263 u32RegAddrIDenable = MIU1_PROTECT3_ID_ENABLE;
1264 u16Data2 = (u16Data1 & 0x0FFF);
1265 break;
1266 default:
1267 return false;
1268 }
1269 }
1270 else if(u8MiuSel == E_CHIP_MIU_2)
1271 {
1272 u32RegAddrMSB = MIU2_PROTECT0_MSB;
1273 u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1274
1275 u32RegAddr = MIU2_PROTECT0_ID0;
1276 u32MiuProtectEn=MIU2_PROTECT_EN;
1277 u32Reg = MIU2_REG_BASE;
1278
1279 switch (u8Blockx)
1280 {
1281 case E_MIU_BLOCK_0:
1282 u32RegAddrStar = MIU2_PROTECT0_START;
1283 u32RegAddrIDenable = MIU2_PROTECT0_ID_ENABLE;
1284 u16Data2 = (u16Data1 & 0xFFF0);
1285 break;
1286 case E_MIU_BLOCK_1:
1287 u32RegAddrStar = MIU2_PROTECT1_START;
1288 u32RegAddrIDenable = MIU2_PROTECT1_ID_ENABLE;
1289 u16Data2 = (u16Data1 & 0xFF0F);
1290 break;
1291 case E_MIU_BLOCK_2:
1292 u32RegAddrStar = MIU2_PROTECT2_START;
1293 u32RegAddrIDenable = MIU2_PROTECT2_ID_ENABLE;
1294 u16Data2 = (u16Data1 & 0xF0FF);
1295 break;
1296 case E_MIU_BLOCK_3:
1297 u32RegAddrStar = MIU2_PROTECT3_START;
1298 u32RegAddrIDenable = MIU2_PROTECT3_ID_ENABLE;
1299 u16Data2 = (u16Data1 & 0x0FFF);
1300 break;
1301 default:
1302 return false;
1303 }
1304 }
1305 else if(u8MiuSel == E_CHIP_MIU_3)
1306 {
1307 u32RegAddrMSB = MIU3_PROTECT0_MSB;
1308 u16Data1 = HAL_MIU_Read2Byte(u32RegAddrMSB);
1309
1310 u32RegAddr = MIU3_PROTECT0_ID0;
1311 u32MiuProtectEn=MIU3_PROTECT_EN;
1312 u32Reg = MIU3_REG_BASE;
1313
1314 switch (u8Blockx)
1315 {
1316 case E_MIU_BLOCK_0:
1317 u32RegAddrStar = MIU3_PROTECT0_START;
1318 u32RegAddrIDenable = MIU3_PROTECT0_ID_ENABLE;
1319 u16Data2 = (u16Data1 & 0xFFF0);
1320 break;
1321 case E_MIU_BLOCK_1:
1322 u32RegAddrStar = MIU3_PROTECT1_START;
1323 u32RegAddrIDenable = MIU3_PROTECT1_ID_ENABLE;
1324 u16Data2 = (u16Data1 & 0xFF0F);
1325 break;
1326 case E_MIU_BLOCK_2:
1327 u32RegAddrStar = MIU3_PROTECT2_START;
1328 u32RegAddrIDenable = MIU3_PROTECT2_ID_ENABLE;
1329 u16Data2 = (u16Data1 & 0xF0FF);
1330 break;
1331 case E_MIU_BLOCK_3:
1332 u32RegAddrStar = MIU3_PROTECT3_START;
1333 u32RegAddrIDenable = MIU3_PROTECT3_ID_ENABLE;
1334 u16Data2 = (u16Data1 & 0x0FFF);
1335 break;
1336 default:
1337 return false;
1338 }
1339 }
1340 else
1341 {
1342 printf("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel );
1343 return FALSE;
1344 }
1345
1346 // Disable MIU protect
1347 HAL_MIU_WriteRegBit(u32MiuProtectEn,u8Data,DISABLE);
1348
1349 if ( bSetFlag )
1350 {
1351 // Set Protect IDs
1352 if(HAL_MIU_SetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegAddr, u32RegAddrIDenable) == FALSE)
1353 {
1354 return FALSE;
1355 }
1356
1357 // Set BIT29,30 of start/end address
1358 u16Data2 = u16Data2 | (MS_U16)((phy64Start >> 29) << (u8Blockx*4));
1359 u16Data1 = u16Data2 | (MS_U16)(((phy64End - 1) >> 29) << (u8Blockx*4+2));
1360 HAL_MIU_Write2Byte(u32RegAddrMSB, u16Data1);
1361
1362 // Start Address
1363 u16Data = (MS_U16)(phy64Start >> MIU_PAGE_SHIFT); //8k/unit
1364 HAL_MIU_Write2Byte(u32RegAddrStar , u16Data);
1365
1366 // End Address
1367 u16Data = (MS_U16)((phy64End >> MIU_PAGE_SHIFT)-1); //8k/unit;
1368 HAL_MIU_Write2Byte(u32RegAddrStar + 2, u16Data);
1369
1370 // Enable MIU protect
1371 HAL_MIU_WriteRegBit(u32MiuProtectEn, u8Data, ENABLE);
1372 }
1373 else
1374 {
1375 // Reset Protect IDs
1376 HAL_MIU_ResetGroupID(u8MiuSel, u8Blockx, pu8ProtectId, u32RegAddr, u32RegAddrIDenable);
1377 }
1378
1379 // clear log
1380 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, TRUE, REG_MIU_PROTECT_LOG_CLR);
1381 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, FALSE, REG_MIU_PROTECT_LOG_CLR);
1382
1383 return TRUE;
1384 }
1385
1386 ////////////////////////////////////////////////////////////////////////////////
1387 /// @brief \b Function \b Name: HAL_MIU_ProtectEx()
1388 /// @brief \b Function \b Description: Enable/Disable MIU Protection mode
1389 /// @param u8Blockx \b IN : MIU Block to protect (0 ~ 4)
1390 /// @param *pu8ProtectId \b IN : Allow specified client IDs to write
1391 /// @param u32Start \b IN : Starting address
1392 /// @param u32End \b IN : End address
1393 /// @param bSetFlag \b IN : Disable or Enable MIU protection
1394 /// - -Disable(0)
1395 /// - -Enable(1)
1396 /// @param <OUT> \b None :
1397 /// @param <RET> \b None :
1398 /// @param <GLOBAL> \b None :
1399 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ProtectEx(MS_U8 u8Blockx,MS_U32 * pu32ProtectId,MS_PHY u32Start,MS_PHY u32End,MS_BOOL bSetFlag)1400 MS_BOOL HAL_MIU_ProtectEx(
1401 MS_U8 u8Blockx,
1402 MS_U32 *pu32ProtectId,
1403 MS_PHY u32Start,
1404 MS_PHY u32End,
1405 MS_BOOL bSetFlag
1406 )
1407 {
1408 return TRUE;
1409 }
1410
1411
1412 #define GET_HIT_BLOCK(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_NO)
1413 #define GET_HIT_CLIENT(regval) BITS_RANGE_VAL(regval, REG_MIU_PROTECT_HIT_ID)
1414
HAL_MIU_GetProtectInfo(MS_U8 u8MiuDev,MIU_PortectInfo * pInfo)1415 MS_BOOL HAL_MIU_GetProtectInfo(MS_U8 u8MiuDev, MIU_PortectInfo *pInfo)
1416 {
1417 MS_U16 ret = 0;
1418 MS_U16 loaddr = 0;
1419 MS_U16 hiaddr = 0;
1420 MS_U32 u32Address = 0;
1421 MS_U32 u32Reg ;
1422
1423 if(u8MiuDev == E_MIU_0)
1424 {
1425 u32Reg = MIU_REG_BASE;
1426 }
1427 else if(u8MiuDev == E_MIU_1)
1428 {
1429 u32Reg = MIU1_REG_BASE;
1430 }
1431 else if(u8MiuDev == E_MIU_2)
1432 {
1433 u32Reg = MIU2_REG_BASE;
1434 }
1435 else
1436 {
1437 printf("%s not support MIU%u!\n", __FUNCTION__, u8MiuDev );
1438 return FALSE;
1439 }
1440
1441 if (!pInfo)
1442 return FALSE;
1443
1444 ret = HAL_MIU_Read2Byte(u32Reg+REG_MIU_PROTECT_STATUS);
1445 loaddr = HAL_MIU_Read2Byte(u32Reg+REG_MIU_PROTECT_LOADDR);
1446 hiaddr = HAL_MIU_Read2Byte(u32Reg+REG_MIU_PROTECT_HIADDR);
1447
1448 pInfo->bHit = false;
1449
1450 if (REG_MIU_PROTECT_HIT_FALG & ret)
1451 {
1452 pInfo->bHit = TRUE;
1453
1454 pInfo->u8Block = (MS_U8)GET_HIT_BLOCK(ret);
1455 pInfo->u8Group = (MS_U8)(GET_HIT_CLIENT(ret) >> 4);
1456 pInfo->u8ClientID = (MS_U8)(GET_HIT_CLIENT(ret) & 0x0F);
1457 u32Address = (MS_U32)((hiaddr << 16) | loaddr) ;
1458 u32Address = u32Address * MIU_PROTECT_ADDRESS_UNIT;
1459 printf("MIU%u Block:%u Group:%u ClientID:%u Hitted_Address:0x%tX<->0x%tX\n", u8MiuDev,
1460 pInfo->u8Block, pInfo->u8Group, pInfo->u8ClientID, (ptrdiff_t)u32Address, (ptrdiff_t)(u32Address + MIU_PROTECT_ADDRESS_UNIT - 1));
1461
1462 //clear log
1463 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, TRUE, REG_MIU_PROTECT_LOG_CLR);
1464 HAL_MIU_Write2BytesBit(u32Reg+REG_MIU_PROTECT_STATUS, FALSE, REG_MIU_PROTECT_LOG_CLR);
1465 }
1466
1467 return TRUE;
1468 }
1469
1470 ////////////////////////////////////////////////////////////////////////////////
1471 /// @brief \b Function \b Name: HAL_MIU_SetSsc()
1472 /// @brief \b Function \b Description: MDrv_MIU_SetSsc, @Step & Span
1473 /// @param u16Fmodulation \b IN : 20KHz ~ 40KHz (Input Value = 20 ~ 40)
1474 /// @param u16FDeviation \b IN : under 0.1% ~ 2% (Input Value = 1 ~ 20)
1475 /// @param bEnable \b IN :
1476 /// @param None \b OUT :
1477 /// @param None \b RET :
1478 /// @param None \b GLOBAL :
1479 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetSsc(MS_U8 u8MiuDev,MS_U16 u16Fmodulation,MS_U16 u16FDeviation,MS_BOOL bEnable)1480 MS_BOOL HAL_MIU_SetSsc(MS_U8 u8MiuDev, MS_U16 u16Fmodulation, MS_U16 u16FDeviation, MS_BOOL bEnable)
1481 {
1482 MS_U32 uDDFSET, uDDR_MHz, uDDFStep, uRegBase = MIU_ATOP_BASE;
1483 MS_U16 u16DDFSpan;
1484 MS_U16 u16Input_DIV_First,u16Input_DIV_Second,u16Loop_DIV_First,u16Loop_DIV_Second;
1485 MS_U8 u8Temp,i;
1486
1487 //Pre check the input
1488 if(u8MiuDev == E_MIU_0)
1489 {
1490 uRegBase = MIU_ATOP_BASE;
1491 }
1492 else if(u8MiuDev == E_MIU_1)
1493 {
1494 uRegBase = MIU1_ATOP_BASE;
1495 }
1496 else if(u8MiuDev == E_MIU_2)
1497 {
1498 uRegBase = MIU2_ATOP_BASE;
1499 }
1500 else
1501 {
1502 printf("%s not support MIU%u!\n", __FUNCTION__, u8MiuDev );
1503 return FALSE;
1504 }
1505
1506 HAL_MIU_SSC_DBG(printf("MMIO base:%lx uRegBase:%lx\n", _gMIU_MapBase, uRegBase));
1507
1508 if ((u16Fmodulation<20)||(u16Fmodulation>40))
1509 {
1510 MIU_HAL_ERR("SSC u16Fmodulation Error...(20KHz - 40KHz)\n");
1511 return 0;
1512 }
1513
1514 if ((u16FDeviation<1)||(u16FDeviation>20))
1515 {
1516 MIU_HAL_ERR("SSC u16FDeviation Error...(0.1%% - 2%% ==> 1 ~20)\n");
1517 return 0;
1518 }
1519
1520 HAL_MIU_SSC_DBG(printf("---> u16Fmodulation = %d u16FDeviation = %d \n",(int)u16Fmodulation,(int)u16FDeviation));
1521 //<1>.Caculate DDFM = (Loop_DIV_First * Loop_DIV_Second)/(Input_DIV_First * Input_DIV_Second);
1522 //Prepare Input_DIV_First
1523 u8Temp = ((MS_U16)(HAL_MIU_Read2Byte(uRegBase+MIU_DDRPLL_DIV_FIRST)&0x3)); //Bit 9,8 (0x110D36)
1524 u16Input_DIV_First = 0x01;
1525 for (i=0;i<u8Temp;i++)
1526 u16Input_DIV_First = u16Input_DIV_First << 1;
1527 //Prepare Input_DIV_Second
1528 u16Input_DIV_Second = 0;// no mapping in Einstein(HAL_MIU_ReadByte(uRegBase+MIU_PLL_INPUT_DIV_2ND)); //Bit 0~7 (0x101222)
1529 if (u16Input_DIV_Second == 0)
1530 u16Input_DIV_Second = 1;
1531 //Prepare Loop_DIV_First
1532 u8Temp = ((HAL_MIU_ReadByte(uRegBase+MIU_DDRPLL_DIV_FIRST)&0xC)>>2); //Bit 11,10 (0x110D36)
1533 u16Loop_DIV_First = 0x01;
1534 for (i=0;i<u8Temp;i++)
1535 u16Loop_DIV_First = u16Loop_DIV_First << 1;
1536
1537 //Prepare Loop_DIV_Second
1538 u16Loop_DIV_Second = (HAL_MIU_ReadByte(uRegBase+MIU_PLL_LOOP_DIV_2ND))&0x1F; //Bit 0~4 (0x101223)
1539 if (u16Loop_DIV_Second == 0)
1540 u16Loop_DIV_Second = 1;
1541
1542 //<2>.From DDFSET register to get DDRPLL
1543 uDDFSET = HAL_MIU_Read4Byte(uRegBase+MIU_DDFSET) & 0x00ffffff;
1544 //DDRPLL = MPPL * DDR_FACTOR * Loop_First * Loop_Second / DDFSET * Input_First * Input_Second
1545 HAL_MIU_SSC_DBG(printf("---> Loop_First:%u Loop_Second:%u\n", u16Loop_DIV_First, u16Loop_DIV_Second));
1546 HAL_MIU_SSC_DBG(printf("---> Input_first:%u Input_second:%u\n", u16Input_DIV_First, u16Input_DIV_Second));
1547 uDDR_MHz = (MPPL * DDR_FACTOR * u16Loop_DIV_First * u16Loop_DIV_Second)/ (uDDFSET*u16Input_DIV_First*u16Input_DIV_Second);
1548 HAL_MIU_SSC_DBG(printf("---> uDDFSET = 0x%lx\n",uDDFSET));
1549 HAL_MIU_SSC_DBG(printf("---> DDR_MHZ = 0x%lx (%d MHz)\n",uDDR_MHz,(int)uDDR_MHz));
1550
1551 //<3>.Caculate DDFSPAN = (MPLL * DDFSPAN_FACTOR * MHz) / (DDFSET * Fmodulation * KHz)
1552 u16DDFSpan = (MS_U32)((DDFSPAN_FACTOR * MPPL/u16Fmodulation)* 1000/uDDFSET);
1553 HAL_MIU_SSC_DBG(printf("---> DDFSPAN = 0x%x (%d)\n",u16DDFSpan,(int)u16DDFSpan));
1554 if (u16DDFSpan > 0x3FFF)
1555 {
1556 u16DDFSpan = 0x3FFF;
1557 HAL_MIU_SSC_DBG(printf("??? DDFSPAN overflow > 0x3FFF, Fource set to 0x03FF\n"));
1558 }
1559
1560 //Write to Register
1561 HAL_MIU_Write2Byte(uRegBase+MIU_DDFSPAN,u16DDFSpan);
1562 //<4>.Caculate DDFSTEP = (FDeviation*DDFSET/10)/(DDFSPAN*100)
1563 uDDFStep = (MS_U32)((u16FDeviation * (uDDFSET/10))/(u16DDFSpan*100));
1564 HAL_MIU_SSC_DBG(printf("---> DDFSTEP = 0x%lx (%lu)\n",uDDFStep,uDDFStep));
1565 //Write to Register
1566 uDDFStep &= (0x03FF);
1567 HAL_MIU_Write2Byte(uRegBase+MIU_DDFSTEP,(HAL_MIU_Read2Byte(uRegBase+MIU_DDFSTEP) & (~0x03FF))|uDDFStep);
1568
1569 //<5>.Set ENABLE
1570 if(bEnable == ENABLE)
1571 HAL_MIU_WriteByte(uRegBase+MIU_SSC_EN,(HAL_MIU_ReadByte(uRegBase+MIU_SSC_EN)|0xC0));
1572 else
1573 HAL_MIU_WriteByte(uRegBase+MIU_SSC_EN,(HAL_MIU_ReadByte(uRegBase+MIU_SSC_EN)&(~0xC0))|0x80);
1574
1575 return 1;
1576 }
1577
1578 ////////////////////////////////////////////////////////////////////////////////
1579 /// @brief \b Function \b Name: HAL_MIU_MaskReq()
1580 /// @brief \b Function \b Description: Mask MIU request
1581 /// @param u8Miu IN \b : miu0 or miu1
1582 /// @param eClientID IN \b : client ID
1583 /// @param None OUT \b :
1584 /// @param None RET \b :
1585 /// @param None GLOBAL \b :
1586 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_MaskReq(MS_U8 u8Miu,eMIUClientID eClientID)1587 void HAL_MIU_MaskReq(MS_U8 u8Miu, eMIUClientID eClientID)
1588 {
1589 MS_S16 sVal = -1;
1590 MS_U32 u32Reg = 0;
1591 MS_U32 u32RegBase = 0;
1592 MS_U32 u32Grp = 0;
1593
1594 sVal = HAL_MIU_GetClientInfo(u8Miu, eClientID);
1595 if (sVal < 0)
1596 {
1597 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1598 return;
1599 }
1600
1601 u32Grp = MIU_GET_CLIENT_GROUP(sVal);
1602
1603 switch (u32Grp)
1604 {
1605 case 0:
1606 case 1:
1607 case 2:
1608 case 3:
1609 u32Reg = REG_MIU_RQX_MASK (u32Grp);
1610 u32RegBase = (u8Miu == E_MIU_0 ? MIU_REG_BASE : (u8Miu == E_MIU_1 ? MIU1_REG_BASE : MIU2_REG_BASE));
1611 break;
1612 case 4:
1613 case 5:
1614 u32Reg = REG_MIU_ARB_RQX_MASK (u32Grp);
1615 u32RegBase = (u8Miu == E_MIU_0 ? MIU_ARB_REG_BASE : (u8Miu == E_MIU_1 ? MIU1_ARB_REG_BASE : MIU2_ARB_REG_BASE));
1616 break;
1617 case 6:
1618 case 7:
1619 u32Reg = REG_MIU_ARBB_RQX_MASK (u32Grp);
1620 u32RegBase = (u8Miu == E_MIU_0 ? MIU_ARBB_REG_BASE : (u8Miu == E_MIU_1 ? MIU1_ARBB_REG_BASE : MIU2_ARBB_REG_BASE));
1621 break;
1622 default:
1623 return;
1624 }
1625 u32Reg += u32RegBase;
1626
1627 HAL_MIU_Write2BytesBit(u32Reg, TRUE, BIT(MIU_GET_CLIENT_POS(sVal)));
1628 }
1629
1630 ////////////////////////////////////////////////////////////////////////////////
1631 /// @brief \b Function \b Name: HAL_MIU_UnMaskReq()
1632 /// @brief \b Function \b Description: Mask MIU request
1633 /// @param u8Miu IN \b : miu0 or miu1
1634 /// @param eClientID IN \b : client ID
1635 /// @param None OUT \b :
1636 /// @param None RET \b :
1637 /// @param None GLOBAL \b :
1638 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_UnMaskReq(MS_U8 u8Miu,eMIUClientID eClientID)1639 void HAL_MIU_UnMaskReq(MS_U8 u8Miu, eMIUClientID eClientID)
1640 {
1641 MS_S16 sVal = -1;
1642 MS_U32 u32Reg = 0;
1643 MS_U32 u32RegBase = 0;
1644 MS_U32 u32Grp = 0;
1645
1646 sVal = HAL_MIU_GetClientInfo(u8Miu, eClientID);
1647 if (sVal < 0)
1648 {
1649 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1650 return;
1651 }
1652
1653 u32Grp = MIU_GET_CLIENT_GROUP(sVal);
1654
1655 switch (u32Grp)
1656 {
1657 case 0:
1658 case 1:
1659 case 2:
1660 case 3:
1661 u32Reg = REG_MIU_RQX_MASK (u32Grp);
1662 u32RegBase = (u8Miu == E_MIU_0 ? MIU_REG_BASE : (u8Miu == E_MIU_1 ? MIU1_REG_BASE : MIU2_REG_BASE));
1663 break;
1664 case 4:
1665 case 5:
1666 u32Reg = REG_MIU_ARB_RQX_MASK (u32Grp);
1667 u32RegBase = (u8Miu == E_MIU_0 ? MIU_ARB_REG_BASE : (u8Miu == E_MIU_1 ? MIU1_ARB_REG_BASE : MIU2_ARB_REG_BASE));
1668 break;
1669 case 6:
1670 case 7:
1671 u32Reg = REG_MIU_ARBB_RQX_MASK (u32Grp);
1672 u32RegBase = (u8Miu == E_MIU_0 ? MIU_ARBB_REG_BASE : (u8Miu == E_MIU_1 ? MIU1_ARBB_REG_BASE : MIU2_ARBB_REG_BASE));
1673 break;
1674 default:
1675 return;
1676 }
1677 u32Reg += u32RegBase;
1678
1679 HAL_MIU_Write2BytesBit(u32Reg, FALSE, BIT(MIU_GET_CLIENT_POS(sVal)));
1680
1681 }
1682
1683 ////////////////////////////////////////////////////////////////////////////////
1684 /// @brief \b Function \b Name: HAL_MIU_SelMIU()
1685 /// @brief \b Function \b Description: MIU selection
1686 /// @param u8MiuDev IN \b : miu device
1687 /// @param u16ClientID IN \b : client ID
1688 /// @param None OUT \b :
1689 /// @param None RET \b :
1690 /// @param None GLOBAL \b :
1691 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SelMIU(eMIU_SelType eType,eMIUClientID eClientID)1692 MS_BOOL HAL_MIU_SelMIU(eMIU_SelType eType, eMIUClientID eClientID)
1693 {
1694 MS_S16 sVal = -1;
1695 MS_U32 u32IdGroup = 0;
1696 MS_U32 u32Reg0 = 0;
1697 MS_U32 u32Reg1 = 0;
1698 MS_U32 u32Reg2 = 0;
1699
1700 //
1701 // 1. Get ID Position in Client Table
1702 //
1703 switch (eType)
1704 {
1705 case MIU_SELTYPE_MIU0:
1706 case MIU_SELTYPE_MIU_ALL:
1707 sVal = HAL_MIU_GetClientInfo(0, eClientID);
1708 break;
1709 case MIU_SELTYPE_MIU1:
1710 sVal = HAL_MIU_GetClientInfo(1, eClientID);
1711 break;
1712 case MIU_SELTYPE_MIU2:
1713 sVal = HAL_MIU_GetClientInfo(2, eClientID);
1714 break;
1715 default:
1716 printf("%s Error Type: 0x%x!\n", __FUNCTION__, eType);
1717 break;
1718 }
1719
1720 if (sVal < 0)
1721 {
1722 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
1723 return FALSE;
1724 }
1725
1726 //
1727 // 2. Set the base address of MIU Select
1728 //
1729 u32IdGroup = MIU_GET_CLIENT_GROUP(sVal);
1730 switch (u32IdGroup)
1731 {
1732 case 0:
1733 case 1:
1734 case 2:
1735 case 3:
1736 case 4:
1737 case 5:
1738 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(u32IdGroup);
1739 u32Reg1 = MIU1_REG_BASE + REG_MIU_SELX(u32IdGroup);
1740 u32Reg2 = MIU2_REG_BASE + REG_MIU_SELX(u32IdGroup);
1741 break;
1742 case 6:
1743 u32Reg0 = MIU_ARBB_REG_BASE + REG_MIU_SELX(0);
1744 u32Reg1 = MIU1_ARBB_REG_BASE + REG_MIU_SELX(0);
1745 u32Reg2 = MIU2_ARBB_REG_BASE + REG_MIU_SELX(0);
1746 break;
1747 default:
1748 break;
1749 }
1750
1751 //
1752 // 3. Set MIU Selection
1753 //
1754 switch (eType)
1755 {
1756 case MIU_SELTYPE_MIU0:
1757 HAL_MIU_Write2BytesBit(u32Reg0, 0, BIT(MIU_GET_CLIENT_POS(sVal)));
1758 HAL_MIU_Write2BytesBit(u32Reg1, 0, BIT(MIU_GET_CLIENT_POS(sVal)));
1759 HAL_MIU_Write2BytesBit(u32Reg2, 0, BIT(MIU_GET_CLIENT_POS(sVal)));
1760 break;
1761 case MIU_SELTYPE_MIU1:
1762 HAL_MIU_Write2BytesBit(u32Reg0, 1, BIT(MIU_GET_CLIENT_POS(sVal)));
1763 HAL_MIU_Write2BytesBit(u32Reg1, 0, BIT(MIU_GET_CLIENT_POS(sVal)));
1764 HAL_MIU_Write2BytesBit(u32Reg2, 0, BIT(MIU_GET_CLIENT_POS(sVal)));
1765 break;
1766 case MIU_SELTYPE_MIU2:
1767 HAL_MIU_Write2BytesBit(u32Reg0, 0, BIT(MIU_GET_CLIENT_POS(sVal)));
1768 HAL_MIU_Write2BytesBit(u32Reg1, 0, BIT(MIU_GET_CLIENT_POS(sVal)));
1769 HAL_MIU_Write2BytesBit(u32Reg2, 1, BIT(MIU_GET_CLIENT_POS(sVal)));
1770 break;
1771 case MIU_SELTYPE_MIU_ALL:
1772 HAL_MIU_Write2BytesBit(u32Reg0, 0, BIT(MIU_GET_CLIENT_POS(sVal)));
1773 HAL_MIU_Write2BytesBit(u32Reg1, 1, BIT(MIU_GET_CLIENT_POS(sVal)));
1774 HAL_MIU_Write2BytesBit(u32Reg2, 0, BIT(MIU_GET_CLIENT_POS(sVal)));
1775 break;
1776 default:
1777 break;
1778 }
1779
1780 return TRUE;
1781 }
1782
1783 ////////////////////////////////////////////////////////////////////////////////
1784 /// @brief \b Function \b Name: MDrv_MIU_Mask_Req_OPM_R()
1785 /// @brief \b Function \b Description: Set OPM MIU mask
1786 /// @param u8Mask IN \b : miu mask
1787 /// @param u8Miu IN \b : miu0 or miu1
1788 /// @param None OUT \b :
1789 /// @param None RET \b :
1790 /// @param None GLOBAL \b :
1791 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_OPM_R(MS_U8 u8Mask,MS_U8 u8Miu)1792 void HAL_MIU_Mask_Req_OPM_R(MS_U8 u8Mask, MS_U8 u8Miu)
1793 {
1794 _FUNC_NOT_USED();
1795 }
1796
1797
1798 ////////////////////////////////////////////////////////////////////////////////
1799 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_DNRB_R()
1800 /// @brief \b Function \b Description: Set OPM MIU mask
1801 /// @param u8Mask IN \b : miu mask
1802 /// @param u8Miu IN \b : miu0 or miu1
1803 /// @param None OUT \b :
1804 /// @param None RET \b :
1805 /// @param None GLOBAL \b :
1806 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_DNRB_R(MS_U8 u8Mask,MS_U8 u8Miu)1807 void HAL_MIU_Mask_Req_DNRB_R(MS_U8 u8Mask, MS_U8 u8Miu)
1808 {
1809 _FUNC_NOT_USED();
1810 }
1811
1812
1813 ////////////////////////////////////////////////////////////////////////////////
1814 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_DNRB_W()
1815 /// @brief \b Function \b Description: Set OPM MIU mask
1816 /// @param u8Mask IN \b : miu mask
1817 /// @param u8Miu IN \b : miu0 or miu1
1818 /// @param None OUT \b :
1819 /// @param None RET \b :
1820 /// @param None GLOBAL \b :
1821 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_DNRB_W(MS_U8 u8Mask,MS_U8 u8Miu)1822 void HAL_MIU_Mask_Req_DNRB_W(MS_U8 u8Mask, MS_U8 u8Miu)
1823 {
1824 _FUNC_NOT_USED();
1825 }
1826
1827
1828 ////////////////////////////////////////////////////////////////////////////////
1829 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_DNRB_RW()
1830 /// @brief \b Function \b Description: Set OPM MIU mask
1831 /// @param u8Mask IN \b : miu mask
1832 /// @param u8Miu IN \b : miu0 or miu1
1833 /// @param None OUT \b :
1834 /// @param None RET \b :
1835 /// @param None GLOBAL \b :
1836 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_DNRB_RW(MS_U8 u8Mask,MS_U8 u8Miu)1837 void HAL_MIU_Mask_Req_DNRB_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1838 {
1839 _FUNC_NOT_USED();
1840 }
1841
1842
1843 ////////////////////////////////////////////////////////////////////////////////
1844 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_SC_RW()
1845 /// @brief \b Function \b Description: Set OPM MIU mask
1846 /// @param u8Mask IN \b : miu mask
1847 /// @param u8Miu IN \b : miu0 or miu1
1848 /// @param None OUT \b :
1849 /// @param None RET \b :
1850 /// @param None GLOBAL \b :
1851 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_SC_RW(MS_U8 u8Mask,MS_U8 u8Miu)1852 void HAL_MIU_Mask_Req_SC_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1853 {
1854 _FUNC_NOT_USED();
1855 }
1856
1857
1858 ////////////////////////////////////////////////////////////////////////////////
1859 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVOP_R()
1860 /// @brief \b Function \b Description: Set OPM MIU mask
1861 /// @param u8Mask IN \b : miu mask
1862 /// @param u8Miu IN \b : miu0 or miu1
1863 /// @param None OUT \b :
1864 /// @param None RET \b :
1865 /// @param None GLOBAL \b :
1866 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVOP_R(MS_U8 u8Mask,MS_U8 u8Miu)1867 void HAL_MIU_Mask_Req_MVOP_R(MS_U8 u8Mask, MS_U8 u8Miu)
1868 {
1869 _FUNC_NOT_USED();
1870 }
1871
1872 ////////////////////////////////////////////////////////////////////////////////
1873 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVD_R()
1874 /// @brief \b Function \b Description: Set OPM MIU mask
1875 /// @param u8Mask IN \b : miu mask
1876 /// @param u8Miu IN \b : miu0 or miu1
1877 /// @param None OUT \b :
1878 /// @param None RET \b :
1879 /// @param None GLOBAL \b :
1880 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVD_R(MS_U8 u8Mask,MS_U8 u8Miu)1881 void HAL_MIU_Mask_Req_MVD_R(MS_U8 u8Mask, MS_U8 u8Miu)
1882 {
1883 _FUNC_NOT_USED();
1884 }
1885
1886 ////////////////////////////////////////////////////////////////////////////////
1887 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVD_W()
1888 /// @brief \b Function \b Description: Set OPM MIU mask
1889 /// @param u8Mask IN \b : miu mask
1890 /// @param u8Miu IN \b : miu0 or miu1
1891 /// @param None OUT \b :
1892 /// @param None RET \b :
1893 /// @param None GLOBAL \b :
1894 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVD_W(MS_U8 u8Mask,MS_U8 u8Miu)1895 void HAL_MIU_Mask_Req_MVD_W(MS_U8 u8Mask, MS_U8 u8Miu)
1896 {
1897 _FUNC_NOT_USED();
1898 }
1899
1900
1901 ////////////////////////////////////////////////////////////////////////////////
1902 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_MVD_RW()
1903 /// @brief \b Function \b Description: Set OPM MIU mask
1904 /// @param u8Mask IN \b : miu mask
1905 /// @param u8Miu IN \b : miu0 or miu1
1906 /// @param None OUT \b :
1907 /// @param None RET \b :
1908 /// @param None GLOBAL \b :
1909 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_MVD_RW(MS_U8 u8Mask,MS_U8 u8Miu)1910 void HAL_MIU_Mask_Req_MVD_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1911 {
1912 _FUNC_NOT_USED();
1913 }
1914
1915
1916 ////////////////////////////////////////////////////////////////////////////////
1917 /// @brief \b Function \b Name: HAL_MIU_Mask_Req_AUDIO_RW()
1918 /// @brief \b Function \b Description: Set OPM MIU mask
1919 /// @param u8Mask IN \b : miu mask
1920 /// @param u8Miu IN \b : miu0 or miu1
1921 /// @param None OUT \b :
1922 /// @param None RET \b :
1923 /// @param None GLOBAL \b :
1924 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_Mask_Req_AUDIO_RW(MS_U8 u8Mask,MS_U8 u8Miu)1925 void HAL_MIU_Mask_Req_AUDIO_RW(MS_U8 u8Mask, MS_U8 u8Miu)
1926 {
1927 _FUNC_NOT_USED();
1928 }
1929
1930 ////////////////////////////////////////////////////////////////////////////////
1931 /// @brief \b Function \b Name: HAL_MIU_GET_MUX()
1932 /// @brief \b Function \b Description:
1933 /// @param None IN \b :
1934 /// @param None IN \b :
1935 /// @param None OUT \b :
1936 /// @param None RET \b :
1937 /// @param None GLOBAL \b :
1938 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GET_MUX(void)1939 MS_U16 HAL_MIU_GET_MUX(void)
1940 {
1941 return 0x0000;
1942 }
1943
1944 ////////////////////////////////////////////////////////////////////////////////
1945 /// @brief \b Function \b Name: HAL_MIU_SwitchMIU()
1946 /// @brief \b Function \b Description:
1947 /// @param u8MiuID \b IN : select MIU0 or MIU1
1948 /// @param None \b RET:
1949 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_VOP_SwitchMIU(MS_U8 u8MiuID)1950 void HAL_MIU_VOP_SwitchMIU(MS_U8 u8MiuID)
1951 {
1952 _FUNC_NOT_USED();
1953 }
1954
1955 ////////////////////////////////////////////////////////////////////////////////
1956 /// @brief \b Function \b Name: HAL_MIU_IsI64Mode()
1957 /// @brief \b Function \b Description:
1958 /// @param None \b RET: 0: not support, 64 or 128 bits
1959 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_IsI64Mode(void)1960 MS_U16 HAL_MIU_IsI64Mode(void)
1961 {
1962 _FUNC_NOT_USED();
1963 return 0x0000;
1964 }
1965
1966 ////////////////////////////////////////////////////////////////////////////////
1967 /// @brief \b Function \b Name: HAL_MIU_IsInitMiu1()
1968 /// @brief \b Function \b Description:
1969 /// @param None \b RET:
1970 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_IsInitMiu1(void)1971 MS_BOOL HAL_MIU_IsInitMiu1(void)
1972 {
1973 return TRUE;
1974 }
1975
1976 ////////////////////////////////////////////////////////////////////////////////
1977 /// @brief \b Function \b Name: HAL_MIU_SetGroupPriority()
1978 /// @brief \b Function \b Description: This function for set each group priority
1979 /// @param u8MiuDev \b IN : select MIU0 or MIU1
1980 /// @param sPriority \b IN : gropu priority
1981 /// @param None \b RET: 0: Fail 1: Ok
1982 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetGroupPriority(MS_U8 u8MiuDev,MIU_GroupPriority sPriority)1983 MS_BOOL HAL_MIU_SetGroupPriority(MS_U8 u8MiuDev, MIU_GroupPriority sPriority)
1984 {
1985 MS_U8 u8Val = 0;
1986 MS_U32 u32RegAddr = REG_MIU_GROUP_PRIORITY;
1987
1988 u8Val = (sPriority.u84th << 6 | sPriority.u83rd << 4 | sPriority.u82nd << 2 | sPriority.u81st);
1989 printf("Change miu%u group priority:%x\n", u8MiuDev, u8Val);
1990
1991 if(u8MiuDev == E_MIU_0)
1992 {
1993 u32RegAddr += MIU_REG_BASE;
1994 }
1995 else if(u8MiuDev == E_MIU_1)
1996 {
1997 u32RegAddr += MIU1_REG_BASE;
1998 }
1999 else if(u8MiuDev == E_MIU_2)
2000 {
2001 u32RegAddr += MIU2_REG_BASE;
2002 }
2003 else
2004 {
2005 printf("%s not support MIU%u!\n", __FUNCTION__, u8MiuDev );
2006 }
2007
2008 HAL_MIU_Write2BytesBit(u32RegAddr,DISABLE, BIT8);
2009 HAL_MIU_WriteByte(u32RegAddr, u8Val);
2010 HAL_MIU_Write2BytesBit(u32RegAddr,ENABLE, BIT8);
2011 return TRUE;
2012 }
2013
2014 ////////////////////////////////////////////////////////////////////////////////
2015 /// @brief \b Function \b Name: HAL_MIU_SetGroupPriority()
2016 /// @brief \b Function \b Description: This function for set each group priority
2017 /// @param u8MiuDev \b IN : select MIU0 or MIU1
2018 /// @param eClientID \b IN : client ID
2019 /// @param bMask \b IN : TRUE: Mask high priority FALSE: Unmask hih priority
2020 /// @param None \b RET: 0: Fail 1: Ok
2021 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetHPriorityMask(MS_U8 u8MiuDev,eMIUClientID eClientID,MS_BOOL bMask)2022 MS_BOOL HAL_MIU_SetHPriorityMask(MS_U8 u8MiuDev, eMIUClientID eClientID, MS_BOOL bMask)
2023 {
2024 MS_S16 sVal;
2025
2026 sVal = HAL_MIU_GetClientInfo(u8MiuDev, eClientID);
2027 if (sVal < 0)
2028 {
2029 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
2030 return FALSE;
2031 }
2032 else
2033 {
2034 MS_U32 u32Reg = REG_MIU_RQX_HPMASK(MIU_GET_CLIENT_GROUP(sVal));
2035
2036 if(u8MiuDev == E_MIU_0)
2037 {
2038 u32Reg += MIU_REG_BASE;
2039 }
2040 else if(u8MiuDev == E_MIU_1)
2041 {
2042 u32Reg += MIU1_REG_BASE;
2043 }
2044 else if(u8MiuDev == E_MIU_2)
2045 {
2046 u32Reg += MIU2_REG_BASE;
2047 }
2048 else
2049 {
2050 printf("%s not support MIU%u!\n", __FUNCTION__, u8MiuDev );
2051 return FALSE;
2052 }
2053
2054 HAL_MIU_Write2BytesBit(u32Reg, bMask, BIT(MIU_GET_CLIENT_POS(sVal)));
2055 }
2056 return TRUE;
2057 }
2058
HAL_MIU_GetAutoPhaseResult(MS_U32 * miu0,MS_U32 * miu1)2059 MS_BOOL HAL_MIU_GetAutoPhaseResult(MS_U32 *miu0, MS_U32 *miu1)
2060 {
2061 static MS_U32 u32Miu0 = 0, u32Miu1 = 0;
2062
2063 *miu0 = u32Miu0;
2064 *miu1 = u32Miu1;
2065
2066 return FALSE;
2067 }
2068
HAL_MIU_EnableScramble(MS_BOOL bEnable)2069 MS_BOOL HAL_MIU_EnableScramble(MS_BOOL bEnable)
2070 {
2071 return FALSE; // not implemented yet
2072 }
2073
HAL_MIU_IsScrambleEnabled(void)2074 MS_BOOL HAL_MIU_IsScrambleEnabled(void)
2075 {
2076 return FALSE; // not implemented yet
2077 }
2078
2079 ////////////////////////////////////////////////////////////////////////////////
2080 /// @brief \b Function \b Name: HAL_MIU_SetLoadingRequest
2081 /// @brief \b Function \b Description: Set loading request
2082 /// @param u8MiuDev \b IN : select MIU0 or MIU1
2083 /// @return \b 0: Fail 1: OK
2084 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_SetLoadingRequest(MS_U8 u8MiuDev)2085 MS_BOOL HAL_MIU_SetLoadingRequest(MS_U8 u8MiuDev)
2086 {
2087 MS_U32 u32RegAddr;
2088
2089 if (u8MiuDev == 1)
2090 {
2091 u32RegAddr = MIU1_BW_REQUEST;
2092 }
2093 else
2094 {
2095 u32RegAddr = MIU_BW_REQUEST;
2096 }
2097
2098 HAL_MIU_Write2Byte(u32RegAddr, 0x0050);
2099 HAL_MIU_Write2Byte(u32RegAddr, 0x0051);
2100
2101 return TRUE;
2102 }
2103 ////////////////////////////////////////////////////////////////////////////////
2104 /// @brief \b Function \b Name: HAL_MIU_GetLoadingRequest
2105 /// @brief \b Function \b Description: Get loading request
2106 /// @param u8MiuDev \b IN : select MIU0 or MIU1
2107 /// @param *u32Loading \b IN : percentage of MIU loading
2108 /// @return \b 0: Fail 1: OK
2109 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GetLoadingRequest(MS_U8 u8MiuDev,MS_U32 * u32Loading)2110 MS_BOOL HAL_MIU_GetLoadingRequest(MS_U8 u8MiuDev, MS_U32 *u32Loading)
2111 {
2112 return FALSE;
2113 }
2114
2115 ////////////////////////////////////////////////////////////////////////////////
2116 /// @brief \b Function \b Name: HAL_MIU_ParseOccupiedResource
2117 /// @brief \b Function \b Description: Parse occupied resource to software structure
2118 /// @return \b 0: Fail 1: OK
2119 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_ParseOccupiedResource(void)2120 MS_BOOL HAL_MIU_ParseOccupiedResource(void)
2121 {
2122 MS_U8 u8MiuSel;
2123 MS_U8 u8Blockx;
2124 MS_U8 u8ClientID;
2125 MS_U16 u16idenable;
2126 MS_U32 u32index;
2127 MS_U32 u32RegAddr;
2128 MS_U32 u32RegAddrIDenable;
2129
2130 for(u8MiuSel = E_MIU_0; u8MiuSel < MIU_MAX_DEVICE; u8MiuSel++)
2131 {
2132 for(u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++)
2133 {
2134 if(u8MiuSel == E_MIU_0)
2135 {
2136 u32RegAddr = MIU_PROTECT0_ID0;
2137
2138 switch (u8Blockx)
2139 {
2140 case E_MIU_BLOCK_0:
2141 u32RegAddrIDenable = MIU_PROTECT0_ID_ENABLE;
2142 break;
2143 case E_MIU_BLOCK_1:
2144 u32RegAddrIDenable = MIU_PROTECT1_ID_ENABLE;
2145 break;
2146 case E_MIU_BLOCK_2:
2147 u32RegAddrIDenable = MIU_PROTECT2_ID_ENABLE;
2148 break;
2149 case E_MIU_BLOCK_3:
2150 u32RegAddrIDenable = MIU_PROTECT3_ID_ENABLE;
2151 break;
2152 default:
2153 return false;
2154 }
2155 }
2156 else if(u8MiuSel == E_MIU_1)
2157 {
2158 u32RegAddr = MIU1_PROTECT0_ID0;
2159
2160 switch (u8Blockx)
2161 {
2162 case E_MIU_BLOCK_0:
2163 u32RegAddrIDenable = MIU1_PROTECT0_ID_ENABLE;
2164 break;
2165 case E_MIU_BLOCK_1:
2166 u32RegAddrIDenable = MIU1_PROTECT1_ID_ENABLE;
2167 break;
2168 case E_MIU_BLOCK_2:
2169 u32RegAddrIDenable = MIU1_PROTECT2_ID_ENABLE;
2170 break;
2171 case E_MIU_BLOCK_3:
2172 u32RegAddrIDenable = MIU1_PROTECT3_ID_ENABLE;
2173 break;
2174 default:
2175 return false;
2176 }
2177 }
2178 else if(u8MiuSel == E_MIU_2)
2179 {
2180 u32RegAddr = MIU2_PROTECT0_ID0;
2181
2182 switch (u8Blockx)
2183 {
2184 case E_MIU_BLOCK_0:
2185 u32RegAddrIDenable = MIU2_PROTECT0_ID_ENABLE;
2186 break;
2187 case E_MIU_BLOCK_1:
2188 u32RegAddrIDenable = MIU2_PROTECT1_ID_ENABLE;
2189 break;
2190 case E_MIU_BLOCK_2:
2191 u32RegAddrIDenable = MIU2_PROTECT2_ID_ENABLE;
2192 break;
2193 case E_MIU_BLOCK_3:
2194 u32RegAddrIDenable = MIU2_PROTECT3_ID_ENABLE;
2195 break;
2196 default:
2197 return false;
2198 }
2199 }
2200 else
2201 {
2202 printf("%s not support MIU%u!\n", __FUNCTION__, u8MiuSel );
2203 return FALSE;
2204 }
2205
2206 u16idenable = HAL_MIU_Read2Byte(u32RegAddrIDenable);
2207 for(u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++)
2208 {
2209 IDEnables[u8MiuSel][u8Blockx][u32index] = ((u16idenable >> u32index) & 0x1)? 1: 0;
2210 }
2211 }//for(u8Blockx = E_MIU_BLOCK_0; u8Blockx < E_MIU_BLOCK_NUM; u8Blockx++)
2212
2213 for(u32index = 0; u32index < MIU_MAX_PROTECT_ID; u32index++)
2214 {
2215 u8ClientID = HAL_MIU_ReadByte(u32RegAddr + u32index);
2216 IDs[u8MiuSel][u32index] = clientTbl[u8MiuSel][u8ClientID];
2217 }
2218 }//for(u8MiuSel = E_MIU_0; u8MiuSel < E_MIU_NUM; u8MiuSel++)
2219
2220 return TRUE;
2221 }
2222
2223
HAL_MIU_PrintMIUProtectArea(MS_U8 u8Blockx,MS_U8 miu_dev)2224 void HAL_MIU_PrintMIUProtectArea(MS_U8 u8Blockx,MS_U8 miu_dev)
2225 {
2226
2227 MS_U16 val_16,val1_16,val2_16;
2228 MS_U32 val_32;
2229 MS_U32 u32RegAddrMSB;
2230 MS_U32 u32RegAddrStar;
2231
2232
2233 if( miu_dev == E_MIU_0 )
2234 {
2235 u32RegAddrMSB = MIU_PROTECT0_MSB;
2236 switch (u8Blockx)
2237 {
2238 case 0:
2239 u32RegAddrStar = MIU_PROTECT0_START;
2240 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2241 val1_16 = ( val1_16 & 0x1 );
2242 val2_16 = ( val1_16 & 0xC );
2243 break;
2244
2245 case 1:
2246 u32RegAddrStar = MIU_PROTECT1_START;
2247 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2248 val1_16 = ( val1_16 & 0x10 );
2249 val2_16 = ( val1_16 & 0xC0 );
2250 break;
2251
2252 case 2:
2253 u32RegAddrStar = MIU_PROTECT2_START;
2254 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2255 val1_16 = ( val1_16 & 0x100 );
2256 val2_16 = ( val1_16 & 0xC00 );
2257 break;
2258
2259 case 3:
2260 u32RegAddrStar = MIU_PROTECT3_START;
2261 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2262 val1_16 = ( val1_16 & 0x1000 );
2263 val2_16 = ( val1_16 & 0xC000 );
2264 break;
2265
2266 default:
2267 printf("error miu protect block number\n");
2268 return ;
2269 }
2270 }
2271 else if( miu_dev == E_MIU_1 )
2272 {
2273 u32RegAddrMSB = MIU1_PROTECT0_MSB;
2274 switch (u8Blockx)
2275 {
2276 case 0:
2277 u32RegAddrStar = MIU1_PROTECT0_START;
2278 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2279 val1_16 = ( val1_16 & 0x1 );
2280 val2_16 = ( val1_16 & 0xC );
2281 break;
2282
2283 case 1:
2284 u32RegAddrStar = MIU1_PROTECT1_START;
2285 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2286 val1_16 = ( val1_16 & 0x10 );
2287 val2_16 = ( val1_16 & 0xC0 );
2288 break;
2289
2290 case 2:
2291 u32RegAddrStar = MIU1_PROTECT2_START;
2292 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2293 val1_16 = ( val1_16 & 0x100 );
2294 val2_16 = ( val1_16 & 0xC00 );
2295 break;
2296
2297 case 3:
2298 u32RegAddrStar = MIU1_PROTECT3_START;
2299 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2300 val1_16 = ( val1_16 & 0x1000 );
2301 val2_16 = ( val1_16 & 0xC000 );
2302 break;
2303
2304 default:
2305 printf("error miu protect block number\n");
2306 return ;
2307 }
2308
2309 }
2310 else if( miu_dev == E_MIU_2 )
2311 {
2312 u32RegAddrMSB = MIU2_PROTECT0_MSB;
2313 switch (u8Blockx)
2314 {
2315 case 0:
2316 u32RegAddrStar = MIU2_PROTECT0_START;
2317 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2318 val1_16 = ( val1_16 & 0x1 );
2319 val2_16 = ( val1_16 & 0xC );
2320 break;
2321
2322 case 1:
2323 u32RegAddrStar = MIU2_PROTECT1_START;
2324 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2325 val1_16 = ( val1_16 & 0x10 );
2326 val2_16 = ( val1_16 & 0xC0 );
2327 break;
2328
2329 case 2:
2330 u32RegAddrStar = MIU2_PROTECT2_START;
2331 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2332 val1_16 = ( val1_16 & 0x100 );
2333 val2_16 = ( val1_16 & 0xC00 );
2334 break;
2335
2336 case 3:
2337 u32RegAddrStar = MIU2_PROTECT3_START;
2338 val1_16 = HAL_MIU_Read2Byte(u32RegAddrMSB);
2339 val1_16 = ( val1_16 & 0x1000 );
2340 val2_16 = ( val1_16 & 0xC000 );
2341 break;
2342
2343 default:
2344 printf("error miu protect block number\n");
2345 return ;
2346 }
2347
2348 }
2349 else
2350 {
2351 printf("%s not support MIU%u!\n", __FUNCTION__, miu_dev );
2352 return;
2353 }
2354
2355 //protect start address
2356 val_16 = HAL_MIU_Read2Byte(u32RegAddrStar);
2357 val_32 = (( val_16 ) | (( val1_16 ) << 4 )) << MIU_PAGE_SHIFT;
2358 printf("miu%d protect%d startaddr is 0x%tX\n", miu_dev, u8Blockx, (ptrdiff_t)val_32);
2359
2360 //protect end address
2361 val_16 = HAL_MIU_Read2Byte(u32RegAddrStar+0x2);
2362 val_32 = ((( val_16 + 1 ) | (( val1_16 ) << 4 ) ) << MIU_PAGE_SHIFT ) - 1;
2363
2364 printf("miu%d protect%d endaddr is 0x%tX\n", miu_dev, u8Blockx, (ptrdiff_t)val_32);
2365 }
2366
HAL_MIU_PrintMIUProtectInfo(void)2367 void HAL_MIU_PrintMIUProtectInfo(void)
2368 {
2369 MS_U32 u32MiuProtectEn;
2370 MS_U32 u32MiuProtectIdEn;
2371
2372 MS_U8 val_8;
2373 MS_U16 val_16;
2374
2375 u32MiuProtectEn = MIU_PROTECT_EN;
2376
2377 u32MiuProtectIdEn= MIU_PROTECT0_ID_ENABLE;
2378 val_8 = HAL_MIU_ReadByte(u32MiuProtectEn);
2379
2380 //printf("val=%d\n",val);
2381
2382 if ( (val_8 & 0xf) != 0 )
2383 {
2384 printf("miu0 protect is enabled\n");
2385
2386 //protect_ID_enable information
2387 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2388 if ( val_16 != 0 )
2389 {
2390 printf("miu0 protect0_ID_enable is 0x%x\n",val_16);
2391 HAL_MIU_PrintMIUProtectArea(0,0);
2392 }
2393
2394 u32MiuProtectIdEn= MIU_PROTECT1_ID_ENABLE;
2395 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2396 if ( val_16 != 0 )
2397 {
2398 printf("miu0 protect1_ID_enable is 0x%x\n",val_16);
2399 HAL_MIU_PrintMIUProtectArea(1,0);
2400 }
2401
2402 u32MiuProtectIdEn= MIU_PROTECT2_ID_ENABLE;
2403 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2404 if ( val_16 != 0 )
2405 {
2406 printf("miu0 protect2_ID_enable is 0x%x\n",val_16);
2407 HAL_MIU_PrintMIUProtectArea(2,0);
2408 }
2409
2410 u32MiuProtectIdEn= MIU_PROTECT3_ID_ENABLE;
2411 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2412 if ( val_16 != 0 )
2413 {
2414 printf("miu0 protect3_ID_enable is 0x%x\n",val_16);
2415 HAL_MIU_PrintMIUProtectArea(3,0);
2416 }
2417
2418 }
2419 else
2420 {
2421 printf("miu0 protect is not enabled\n");
2422 }
2423
2424 u32MiuProtectEn=MIU1_PROTECT_EN;
2425 val_8 = HAL_MIU_ReadByte(u32MiuProtectEn);
2426
2427 //printf("val=%d\n",val);
2428
2429 if ( (val_8 & 0xf) != 0x0 )
2430 {
2431 printf("miu1 protect is enabled\n");
2432
2433 //protect_ID_enable information
2434 u32MiuProtectIdEn= MIU1_PROTECT0_ID_ENABLE;
2435 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2436 if ( val_16 != 0 )
2437 {
2438 printf("miu1 protect0_ID_enable is 0x%x\n",val_16);
2439 HAL_MIU_PrintMIUProtectArea(0,1);
2440 }
2441
2442 u32MiuProtectIdEn= MIU1_PROTECT1_ID_ENABLE;
2443 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2444 if ( val_16 != 0 )
2445 {
2446 printf("miu1 protect1_ID_enable is 0x%x\n",val_16);
2447 HAL_MIU_PrintMIUProtectArea(1,1);
2448 }
2449
2450 u32MiuProtectIdEn= MIU1_PROTECT2_ID_ENABLE;
2451 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2452 if ( val_16 != 0 )
2453 {
2454 printf("miu1 protect2_ID_enable is 0x%x\n",val_16);
2455 HAL_MIU_PrintMIUProtectArea(2,1);
2456 }
2457
2458 u32MiuProtectIdEn= MIU1_PROTECT3_ID_ENABLE;
2459 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2460 if ( val_16 != 0 )
2461 {
2462 printf("miu1 protect3_ID_enable is 0x%x\n",val_16);
2463 HAL_MIU_PrintMIUProtectArea(3,1);
2464 }
2465
2466
2467 }
2468 else
2469 {
2470 printf("miu1 protect is not enabled\n");
2471
2472 }
2473
2474 u32MiuProtectEn=MIU2_PROTECT_EN;
2475 val_8 = HAL_MIU_ReadByte(u32MiuProtectEn);
2476
2477 //printf("val=%d\n",val);
2478
2479 if ( (val_8 & 0xf) != 0x0 )
2480 {
2481 printf("miu2 protect is enabled\n");
2482
2483 //protect_ID_enable information
2484 u32MiuProtectIdEn= MIU2_PROTECT0_ID_ENABLE;
2485 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2486 if ( val_16 != 0 )
2487 {
2488 printf("miu2 protect0_ID_enable is 0x%x\n",val_16);
2489 HAL_MIU_PrintMIUProtectArea(0,2);
2490 }
2491
2492 u32MiuProtectIdEn= MIU2_PROTECT1_ID_ENABLE;
2493 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2494 if ( val_16 != 0 )
2495 {
2496 printf("miu2 protect1_ID_enable is 0x%x\n",val_16);
2497 HAL_MIU_PrintMIUProtectArea(1,2);
2498 }
2499
2500 u32MiuProtectIdEn= MIU2_PROTECT2_ID_ENABLE;
2501 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2502 if ( val_16 != 0 )
2503 {
2504 printf("miu2 protect2_ID_enable is 0x%x\n",val_16);
2505 HAL_MIU_PrintMIUProtectArea(2,2);
2506 }
2507
2508 u32MiuProtectIdEn= MIU2_PROTECT3_ID_ENABLE;
2509 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2510 if ( val_16 != 0 )
2511 {
2512 printf("miu2 protect3_ID_enable is 0x%x\n",val_16);
2513 HAL_MIU_PrintMIUProtectArea(3,2);
2514 }
2515
2516
2517 }
2518 else
2519 {
2520 printf("miu2 protect is not enabled\n");
2521
2522 }
2523
2524 u32MiuProtectEn=MIU3_PROTECT_EN;
2525 val_8 = HAL_MIU_ReadByte(u32MiuProtectEn);
2526
2527 //printf("val=%d\n",val);
2528
2529 if ( (val_8 & 0xf) != 0x0 )
2530 {
2531 printf("miu3 protect is enabled\n");
2532
2533 //protect_ID_enable information
2534 u32MiuProtectIdEn= MIU3_PROTECT0_ID_ENABLE;
2535 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2536 if ( val_16 != 0 )
2537 {
2538 printf("miu3 protect0_ID_enable is 0x%x\n",val_16);
2539 HAL_MIU_PrintMIUProtectArea(0,3);
2540 }
2541
2542 u32MiuProtectIdEn= MIU3_PROTECT1_ID_ENABLE;
2543 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2544 if ( val_16 != 0 )
2545 {
2546 printf("miu3 protect1_ID_enable is 0x%x\n",val_16);
2547 HAL_MIU_PrintMIUProtectArea(1,3);
2548 }
2549
2550 u32MiuProtectIdEn= MIU3_PROTECT2_ID_ENABLE;
2551 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2552 if ( val_16 != 0 )
2553 {
2554 printf("miu3 protect2_ID_enable is 0x%x\n",val_16);
2555 HAL_MIU_PrintMIUProtectArea(2,3);
2556 }
2557
2558 u32MiuProtectIdEn= MIU3_PROTECT3_ID_ENABLE;
2559 val_16 =HAL_MIU_Read2Byte(u32MiuProtectIdEn);
2560 if ( val_16 != 0 )
2561 {
2562 printf("miu3 protect3_ID_enable is 0x%x\n",val_16);
2563 HAL_MIU_PrintMIUProtectArea(3,3);
2564 }
2565
2566
2567 }
2568 else
2569 {
2570 printf("miu3 protect is not enabled\n");
2571
2572 }
2573 }
2574
2575 ////////////////////////////////////////////////////////////////////////////////
2576 /// @brief \b Function \b Name: HAL_MIU_GetClientWidth
2577 /// @brief \b Function \b Description: Get MIU client bus width
2578 /// @param u8MiuDev \b IN : select MIU0 or MIU1
2579 /// @param eClientID \b IN : client ID
2580 /// @param pClientWidth \b IN : client bus width
2581 /// @return \b 0 : Fail 1: OK
2582 ////////////////////////////////////////////////////////////////////////////////
HAL_MIU_GetClientWidth(MS_U8 u8MiuDevi,eMIUClientID eClientID,eMIU_ClientWidth * pClientWidth)2583 MS_BOOL HAL_MIU_GetClientWidth(MS_U8 u8MiuDevi, eMIUClientID eClientID, eMIU_ClientWidth *pClientWidth)
2584 {
2585 MS_U32 u32Reg;
2586 MS_S16 sVal;
2587 MS_U16 u16Group;
2588 MS_U16 u16Client;
2589 MS_U16 u16RegVal;
2590
2591 sVal = HAL_MIU_GetClientInfo(u8MiuDevi, eClientID);
2592
2593 if (sVal < 0)
2594 {
2595 printf("%s not support client ID:%u!\n", __FUNCTION__, eClientID);
2596 return FALSE;
2597 }
2598 else
2599 {
2600 u16Group = MIU_GET_CLIENT_GROUP(sVal);
2601 u16Client = MIU_GET_CLIENT_POS(sVal);
2602
2603 if(u16Group >= 4)
2604 {
2605 *pClientWidth = E_MIU_CLIENT_256BIT;
2606 return TRUE;
2607 }
2608
2609 u32Reg = REG_MI64_FORCE + (MIU_GET_CLIENT_GROUP(sVal) << 1);
2610 u16RegVal = HAL_MIU_Read2Byte(u32Reg);
2611
2612 if(u16RegVal & (1 << u16Client))
2613 *pClientWidth = E_MIU_CLIENT_64BIT;
2614 else
2615 *pClientWidth = E_MIU_CLIENT_128BIT;
2616
2617 return TRUE;
2618 }
2619 }
2620
2621
HAL_MIU_GetDramType(MS_U32 eMiu,MIU_DDR_TYPE * pType)2622 MS_BOOL HAL_MIU_GetDramType(MS_U32 eMiu, MIU_DDR_TYPE* pType)
2623 {
2624 MS_U32 u32Reg;
2625
2626 if (eMiu >= MIU_MAX_DEVICE)
2627 return FALSE;
2628
2629 switch (eMiu)
2630 {
2631 case 0:
2632 u32Reg = REG_MIU_DDR_STATUS;
2633 break;
2634 case 1:
2635 u32Reg = REG_MIU1_DDR_STATUS;
2636 break;
2637 case 2:
2638 u32Reg = REG_MIU2_DDR_STATUS;
2639 break;
2640 default:
2641 return FALSE;
2642 }
2643
2644 if (HAL_MIU_Read2Byte(u32Reg)& REG_MIU_DDR4)
2645 {
2646 *pType = E_MIU_DDR4;
2647 }
2648 else
2649 {
2650 *pType = E_MIU_DDR3;
2651 }
2652
2653 return TRUE;
2654 }
2655