1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108 #define HAL_GOP_DEBUGINFO(x) //x
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_BANK_MASK 0x1FUL
117 #define GOP_DST_MASK 0xFUL
118
119 //------------------------------------------------------------------------------
120 // Local Var
121 //------------------------------------------------------------------------------
122 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
123 {
124 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
125 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
126 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
127 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
128 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
129 };
130 #ifdef GOP_CMDQ_ENABLE
131 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
132 extern MS_BOOL bMIUSelect[MAX_GOP_SUPPORT];
133
134 extern MS_U16 u16AFBCMIUSelect[MAX_GOP_SUPPORT];
135 extern MS_BOOL bAFBCMIUSelect[MAX_GOP_SUPPORT];
136 #endif
137 GOP_CHIP_PROPERTY g_GopChipPro =
138 {
139 .bSetHSyncInverse = TRUE,
140 .bGop1GPalette = TRUE,
141 .bSetHPipeOfst = FALSE,
142 .bNeedCheckMVOP = FALSE,
143 .bNeedSetMUX1ToIP0 = FALSE,
144 .bNeedSetMUX3ToIP0 = FALSE,
145 .bNewMux = TRUE,
146 .bNewPalette = TRUE,
147 .bNewBwReg = TRUE,
148 .bGop2VStretch = TRUE,
149 .bIgnoreIPHPD = TRUE, //Uranus4 has handshack with XC, should not set HPD
150 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
151 .bhastilemode = TRUE,
152 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
153 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
154 .bGOPWithVscale = {TRUE, TRUE, TRUE, FALSE, FALSE}, //setting GOP with/without Vscale
155
156 .bDWINSupport = FALSE,
157 .DwinVer = 0x1,
158 .bTstPatternAlpha = TRUE,
159 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
160 .bFRCSupport = FALSE, /*OC path*/
161 .bGOPMixerToVE= TRUE, /*Mixer to VE path*/
162 .bBnkForceWrite = TRUE, /*Direct Bank Force Write*/
163 .bPixelModeSupport = TRUE, /*Pixel Mode Support*/
164 .bScalingDownSupport= FALSE,
165 .b2Pto1PSupport= TRUE,
166 .bTLBSupport= {TRUE, FALSE, TRUE, TRUE, FALSE, FALSE},
167 .GOP_TestPattern_Vaild= E_GOP0,
168 .bInternalMIUSelect= {TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
169 .bAFBC_Support= {TRUE, FALSE, TRUE, FALSE, FALSE, FALSE},
170
171 #ifdef ENABLE_GOP_T3DPATCH
172 .GOP_PD = 0x30,
173 #else
174 .GOP_PD = 0x179,
175 #endif
176 .GOP_UHD_PD_Offset = 0x0,
177 .GOP_IP_PD = 0x00,
178 .GOP_MVOP_PD = 0x69,
179 .GOP_VE_PD = 0x89,
180 .GOP_MIXER_PD = 0x0,
181 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
182 .GOP_VE_V_Offset = 0x0,
183 .GOP_OP1_PD = 0x1A0,
184
185 .GOP_MUX_Delta = 0x4,
186 .GOP_Mux_Offset = {0x0, 0x1, 0x2, 0x3, 0x3},
187 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX1, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX4},
188 .GOP_Mux_FRC_offset= 0x13,
189
190 .WordUnit = GOP_WordUnit,
191 .TotalGwinNum = GOP_TotalGwinNum,
192 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
193 .enGOP3DType = E_DRV_3D_DUP_FULL,
194 .bAFBC_Merge_GOP_Trig = TRUE,
195 .bGOPVscalePipeDelay = {FALSE, FALSE, FALSE, FALSE, TRUE, FALSE},
196 .bGOPAutoClkGating = TRUE,
197 };
198
199
200 //------------------------------------------------------------------------------
201 // Global Functions
202 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)203 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
204 {
205 GOP_TYPE->GOP0 = E_GOP0;
206 GOP_TYPE->GOP1 = E_GOP1;
207 GOP_TYPE->GOP2 = E_GOP2;
208 GOP_TYPE->GOP3 = E_GOP3;
209 GOP_TYPE->GOP4 = E_GOP4;
210 GOP_TYPE->GOP5 = E_GOP5;
211 GOP_TYPE->DWIN = E_GOP_Dwin;
212 GOP_TYPE->MIXER = E_GOP_MIXER;
213 }
214
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)215 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
216 {
217 MS_U32 u32BankOffSet = 0;
218
219 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
220
221 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
222 {
223 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, 0x01f0);
224 }
225 else
226 {
227 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, 0x01f0);
228 }
229
230 return GOP_SUCCESS;
231 }
232
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)233 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
234 {
235 MS_U32 u32BankOffSet =0;
236 MS_U32 u32BitMask,Regval;
237
238 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
239
240 switch(pinpon_mode)
241 {
242 default:
243 case E_DRV_GOP_PINPON_G3D:
244 Regval = bEn << 5;
245 u32BitMask = GOP_BIT5;
246 break;
247 case E_DRV_GOP_PINPON_DWIN:
248 Regval = bEn << 6;
249 u32BitMask = GOP_BIT6;
250 break;
251 case E_DRV_GOP_PINPON_DIP:
252 Regval = bEn << 7;
253 u32BitMask = GOP_BIT7;
254 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT9,(GOP_BIT8|GOP_BIT9));
255 break;
256 case E_DRV_GOP_PINPON_DWIN0:
257 Regval = bEn << 7;
258 u32BitMask = GOP_BIT7;
259 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, 0x0,(GOP_BIT8|GOP_BIT9));
260 break;
261 case E_DRV_GOP_PINPON_DWIN1:
262 Regval = bEn << 7;
263 u32BitMask = GOP_BIT7;
264 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT8,(GOP_BIT8|GOP_BIT9));
265 break;
266 break;
267 }
268
269 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
270 return GOP_SUCCESS;
271 }
272
273
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)274 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
275 {
276 if(gop >= MAX_GOP_SUPPORT)
277 {
278 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
279 return FALSE;
280 }
281
282 if (gop==E_GOP0)
283 *pBnkOfst = GOP_4G_OFST<<16;
284 else if (gop==E_GOP1)
285 *pBnkOfst = GOP_2G_OFST<<16;
286 else if (gop==E_GOP2)
287 *pBnkOfst = GOP_1G_OFST<<16;
288 else if (gop==E_GOP3)
289 *pBnkOfst = GOP_1GX_OFST<<16;
290 else if (gop==E_GOP5)
291 *pBnkOfst = GOP_1GS1_OFST<<16;
292 else
293 return FALSE;
294
295 return TRUE;
296 }
297
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)298 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
299 {
300 MS_U16 u16Mask0 = 0;
301 MS_U16 u16Mask1 = 0;
302 if (u16GopMask&GOP_BIT0)
303 {
304 u16Mask0 |= GOP_BIT12;
305 }
306 if (u16GopMask&GOP_BIT1)
307 {
308 u16Mask0 |= GOP_BIT13;
309 }
310 if (u16GopMask&GOP_BIT2)
311 {
312 u16Mask0 |= GOP_BIT14;
313 }
314 if (u16GopMask&GOP_BIT3)
315 {
316 u16Mask0 |= GOP_BIT15;
317 }
318 if (u16GopMask&GOP_BIT4)
319 {
320 u16Mask1 |= GOP_BIT4;
321 }
322 if (u16Mask0 != 0)
323 {
324 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
325 }
326 if (u16Mask1 != 0)
327 {
328 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, 0xFFFF , u16Mask1);
329 }
330
331 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
332 {
333 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
334 }
335 return GOP_SUCCESS;
336 }
337
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)338 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
339 {
340 if(gop >= MAX_GOP_SUPPORT)
341 {
342 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
343 return GOP_FAIL;
344 }
345
346 switch(gop)
347 {
348 case E_GOP0:
349 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
350 break;
351 case E_GOP1:
352 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
353 break;
354 case E_GOP2:
355 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
356 break;
357 case E_GOP3:
358 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
359 break;
360 #if (MAX_GOP_SUPPORT>4)
361 case E_GOP4:
362 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
363 break;
364 #endif
365 default:
366 break;
367 }
368 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
369 {
370 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0);
371 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
372 }
373 return GOP_SUCCESS;
374 }
375
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)376 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
377 {
378 MS_U16 u16GopAck = 0,reg_val =0;
379
380 if(gop >= MAX_GOP_SUPPORT)
381 {
382 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
383 return FALSE;
384 }
385
386 switch(gop)
387 {
388 case E_GOP0:
389 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
390 if(reg_val&GOP_BIT12)
391 u16GopAck = FALSE;
392 else
393 u16GopAck = TRUE;
394 break;
395 case E_GOP1:
396 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
397 if(reg_val&GOP_BIT13)
398 u16GopAck = FALSE;
399 else
400 u16GopAck = TRUE;
401 break;
402 case E_GOP2:
403 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
404 if(reg_val&GOP_BIT14)
405 u16GopAck = FALSE;
406 else
407 u16GopAck = TRUE;
408 break;
409 case E_GOP3:
410 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
411 if(reg_val&GOP_BIT15)
412 u16GopAck = FALSE;
413 else
414 u16GopAck = TRUE;
415 break;
416 #if (MAX_GOP_SUPPORT>4)
417 case E_GOP4:
418 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
419 if(reg_val&GOP_BIT4)
420 u16GopAck = FALSE;
421 else
422 u16GopAck = TRUE;
423 break;
424 #endif
425 default:
426 break;
427 }
428 return u16GopAck;
429 }
430
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)431 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
432 {
433 return GOP_FUN_NOT_SUPPORTED;
434 }
435
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)436 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
437 {
438 MS_U32 u32bankoff = 0;
439 MS_U16 mask_shift=0xFF;
440 MS_U16 u16RegVal=0xFF;
441 MS_U8 u8MIUSel=0xF;
442 MS_U8 u8Core=0;
443
444 if(u8GOPNum >= MAX_GOP_SUPPORT)
445 {
446 return;
447 }
448
449 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
450 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
451
452 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, 0xDCF0, GOP_REG_WORD_MASK); //set GOP DMA Burst length to "32"
453
454 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
455 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
456 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT8|GOP_BIT9, GOP_BIT8|GOP_BIT9);
457
458 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
459
460 // H121 filter
461 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0, GOP_BIT0); // HD alpha Enable
462 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0, GOP_BIT1); // HD data Enable
463 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT2, GOP_BIT2); // SD data Enable
464 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT3, GOP_BIT3); // SD data Enable
465 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0x2000, 0x3F00); // Ratio between [H121] and [Bypass mode]
466
467 if((u8GOPNum == 0)||(u8GOPNum == 1)||(u8GOPNum == 2))
468 {
469 if(u8GOPNum == 0)
470 {
471 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT13|GOP_BIT14);
472 }
473 else
474 {
475 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT14);
476 }
477 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_TWO_LINEBUFFER, GOP_BIT12, GOP_BIT12);
478 }
479
480 /* enable GOP clock */
481 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM1_DISABLE_CLK|CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
482 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, BMASK(7:0)); /* GOP Line buffer sram clock */
483
484 switch(u8GOPNum)
485 {
486 case E_GOP0:
487 mask_shift = GOP_MIU_CLIENT_GOP0;
488 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
489 break;
490 case E_GOP1:
491 mask_shift = GOP_MIU_CLIENT_GOP1;
492 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
493 break;
494 case E_GOP2:
495 mask_shift = GOP_MIU_CLIENT_GOP2;
496 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
497 break;
498 case E_GOP3:
499 mask_shift = GOP_MIU_CLIENT_GOP3;
500 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK); /* GOP 3 */
501 break;
502 case E_GOP5:
503 mask_shift = GOP_MIU_CLIENT_GOP5;
504 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, 0, CKG_GOPG5_DISABLE_CLK_MASK); /* GOP 5 */
505 break;
506 default:
507 mask_shift = 0xFF;
508 break;
509 }
510 if(g_GopChipPro.bAFBC_Support[u8GOPNum] ==TRUE)
511 {
512 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, 0, CKG_AFBCCLK_DISABLE_CLK_MASK);
513 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(0), GOP_BIT5 , GOP_BIT5); //Half block
514 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(1), GOP_BIT5 , GOP_BIT5); //Half block
515 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk(Without resoluton)
516 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0); //Double buffer
517 }
518
519
520 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
521 {
522 if(u8GOPNum ==E_GOP5)
523 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal);
524 else
525 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
526 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
527 #ifdef GOP_MIU_GROUP2
528 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal);
529 u8MIUSel = u8MIUSel|(((u16RegVal>>mask_shift)&0x0000001UL)<<1);
530 #endif
531 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
532 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
533 if(g_GopChipPro.bAFBC_Support[u8GOPNum]==TRUE)
534 {
535 HAL_GOP_AFBC_GetCore(pGOPHalLocal, u8GOPNum, &u8Core);
536 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_MIU, u8MIUSel<<4 , GOP_BIT4|GOP_BIT5);
537 }
538
539 if(u8GOPNum ==E_GOP5)
540 HAL_GOP_Write16Reg(pGOPHalLocal, GOP5_MIU_GROUP, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
541 else
542 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
543 }
544
545 //OC_RM_alpha
546 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, GOP_BIT0, GOP_BIT0);
547 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
548 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
549
550 // set VIP/VOP timing select, always select VOP should be OK.
551 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_VIP_VOP_TIMING_SEL, GOP_BIT10, GOP_BIT10);
552
553 // Enable OP Mux double buff
554 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_OP_MUX_DBF, GOP_BIT15 , GOP_BIT15);
555
556 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15);//Per Pixel New alpha mode
557 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15);//Per Pixel New alpha mode
558 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP,GOP_IP_SUB_MUX_MASK, GOP_IP_SUB_MUX_MASK); //default mask sub IP
559 }
560
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)561 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
562 {
563 *pGOPHalLocal->pGopChipPro = g_GopChipPro;
564 }
565
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)566 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
567 {
568 switch(u8GopNum)
569 {
570 case E_GOP0:
571 return (MS_U8)MAX_GOP0_GWIN;
572 break;
573 case E_GOP1:
574 return (MS_U8)MAX_GOP1_GWIN;
575 break;
576 case E_GOP2:
577 return (MS_U8)MAX_GOP2_GWIN;
578 break;
579 case E_GOP3:
580 return (MS_U8)MAX_GOP3_GWIN;
581 break;
582 case E_GOP4:
583 return (MS_U8)MAX_GOP4_GWIN;
584 break;
585 default:
586 MS_ASSERT(0);
587 return 0xFF;
588 break;
589 }
590 }
591
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)592 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
593 {
594 MS_U8 u8GWinId = 0;
595
596 //Adjust GWIN ID by different Chip
597 if(u8Gop >= MAX_GOP_SUPPORT)
598 {
599 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8Gop);
600 MS_ASSERT(0);
601 return 0xFF;
602 }
603
604 switch(u8Gop)
605 {
606 case E_GOP0:
607 u8GWinId = GOP0_GwinIdBase + u8Idx;
608 break;
609 case E_GOP1:
610 u8GWinId = GOP1_GwinIdBase + u8Idx;
611 break;
612 case E_GOP2:
613 u8GWinId = GOP2_GwinIdBase + u8Idx;
614 break;
615 case E_GOP3:
616 u8GWinId = GOP3_GwinIdBase + u8Idx;
617 break;
618 #if (MAX_GOP_SUPPORT>4)
619 case E_GOP4:
620 u8GWinId = GOP4_GwinIdBase + u8Idx;
621 break;
622 #endif
623 default:
624 break;
625 }
626 return u8GWinId;
627
628 }
629
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)630 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
631 {
632 if(u8GOPNum >= MAX_GOP_SUPPORT)
633 {
634 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOPNum);
635 MS_ASSERT(0);
636 return 0xFF;
637 }
638
639 switch(u8GOPNum)
640 {
641 case E_GOP0: // GOP4G
642 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
643 return GOP_SUCCESS;
644 case E_GOP1: // GOP2G
645 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
646 return GOP_SUCCESS;
647 case E_GOP2: // GOP1G
648 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
649 return GOP_SUCCESS;
650 case E_GOP3: // GOP1GX
651 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
652 return GOP_SUCCESS;
653 #if (MAX_GOP_SUPPORT>4)
654 case E_GOP4: // GOP1GS
655 pGOPHalLocal->bank_offset = GOP_1GS0_OFST<<16;
656 return GOP_SUCCESS;
657 #endif
658 default:
659 MS_ASSERT(0);
660 return GOP_FAIL;
661 }
662 }
663
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)664 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
665 {
666 MS_U16 u16Bank;
667 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
668 u16Bank &= ~BMASK(3:0);
669 u16Bank |= (u8bank&BMASK(3:0));
670 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
671 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL_EX);
672 u16Bank &= ~GOP_BIT4;
673 u16Bank |= ((u8bank&GOP_BIT4)<<GOP_BIT4);
674 GOP_WRITE2BYTE(GOP_BAK_SEL_EX, u16Bank);
675 }
676
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)677 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
678 {
679 MS_U16 u16GetBank=0;
680 #if (MAX_GOP_SUPPORT>4)
681 MS_U16 u16BankMask=0;
682
683 if(MAX_GOP_SUPPORT ==5)
684 {
685 u16BankMask = GOP_BANK_MASK | GOP_BIT4;
686 u16GetBank = ((GOP_READ2BYTE(GOP_BAK_SEL_EX)& GOP_BIT8)>> GOP_BIT4)| (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
687 return (u16GetBank&u16BankMask);
688 }
689 else
690 #endif
691 {
692 u16GetBank = (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
693 return (u16GetBank&GOP_BANK_MASK);
694 }
695 }
696
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)697 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
698 {
699 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
700 MS_U32 bank;
701 MS_U32 direct_addr;
702
703 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Read16Reg[%x]\n", u32addr));
704
705 //* Gop driver should access another HW IP register
706 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
707 switch (u32addr & 0xFF00)
708 {
709 case GOP_REG_BASE:
710 {
711 bank = (u32addr & 0xFF0000) >> 8;
712 #if 0 //for GOP4
713 if(bank==0xE00)//GOP4: 0x121B00
714 {
715 bank=GOP_REG_GOP4_BK_OFFSET;
716 }
717 else if(bank==0xF00)//GWIN4: 0x121E00
718 {
719 bank=GOP_REG_GOP4_GW_OFFSET;
720 }
721 else if(bank==0x1000)//GOP4_ST
722 {
723 bank=GOP_REG_GOP4_ST_OFFSET;
724 }
725 #endif
726 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
727 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
728 break;
729 }
730 case SC1_REG_BASE:
731 {
732 if(g_GopChipPro.bXCDirrectBankSupport)
733 {
734 u16xcSubbank = (u32addr & 0xFF0000)>>8;
735 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
736 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
737 }
738 else
739 {
740 u16xcSubbank = (u32addr & 0xFF0000)>>16;
741 u16BankAddr = GOP_SC_BANKSEL+0;
742 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
743
744 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
745 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
746 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
747 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
748 }
749 break;
750 }
751 case GE_REG_BASE:
752 case CKG_REG_BASE:
753 case MIU0_REG_BASE:
754 case MIU_REG_BASE:
755 case MVOP_REG_BASE:
756 case VE_REG_BASE:
757 {
758 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
759 break;
760 }
761 #ifdef GOP_MIU_GROUP2
762 case (MIU2_REG_BASE & 0xFF00):
763 {
764 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
765 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
766
767 break;
768 }
769 #endif
770 default:
771 {
772 //Gop lib current do not support this HW ip base
773 MS_ASSERT(0);
774 *pu16ret =0;
775 break;
776 }
777 }
778 }
779
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)780 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
781 {
782 MS_U16 u16tmp=0;
783 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
784 MS_U32 bank;
785 MS_U32 direct_addr;
786
787 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write16Reg[%04x] = %04x\n", u32addr, u16val));
788
789 if(mask!=0xffff)
790 {
791 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
792 u16tmp &= ~mask;
793 u16val &= mask;
794 u16val |= u16tmp;
795 }
796
797 //* Gop driver should access another HW IP register
798 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
799 switch (u32addr & 0xFF00)
800 {
801 case GOP_REG_BASE:
802 {
803 bank = (u32addr & 0xFF0000) >> 8;
804 #if 0 //for GOP4
805 if(bank==0xE00)//GOP4: 0x121B00
806 {
807 bank=GOP_REG_GOP4_BK_OFFSET;
808 }
809 else if(bank==0xF00)//GWIN4: 0x121E00
810 {
811 bank=GOP_REG_GOP4_GW_OFFSET;
812 }
813 else if(bank==0x1000) //GOP4_ST
814 {
815 bank=GOP_REG_GOP4_ST_OFFSET;
816 }
817 #endif
818 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
819 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
820 break;
821 }
822 case SC1_REG_BASE:
823 if(g_GopChipPro.bXCDirrectBankSupport)
824 { /*Derrick Bank*/
825 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
826 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
827 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
828 }
829 else
830 { /*Sub Bank*/
831 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
832 u16BankAddr = GOP_SC_BANKSEL+0;
833 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
834
835 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
836 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
837 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
838 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
839 }
840 break;
841 case GE_REG_BASE:
842 case CKG_REG_BASE:
843 case MIU0_REG_BASE:
844 case MIU_REG_BASE:
845 case VE_REG_BASE:
846 {
847 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
848 break;
849 }
850 #ifdef GOP_MIU_GROUP2
851 case (MIU2_REG_BASE & 0xFF00):
852 {
853 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
854 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
855 break;
856 }
857 #endif
858 default:
859 {
860 //Gop lib current do not support this HW ip base
861 MS_ASSERT(0);
862 break;
863 }
864
865 }
866 }
867
868
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)869 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
870 {
871 MS_U32 bank;
872 MS_U32 direct_addr;
873
874 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write32Reg[%bx] = %lx\n", u32addr, u32val));
875
876 //* Gop driver should access another HW IP register
877 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
878 switch (u32addr & 0xFF00)
879 {
880 case GOP_REG_BASE:
881 {
882 bank = (u32addr & 0xFF0000) >> 8;
883 #if 0 //for GOP4
884 if(bank==0xE00)//GOP4: 0x121B00
885 {
886 bank=GOP_REG_GOP4_BK_OFFSET;
887 }
888 else if(bank==0xF00)//GWIN4: 0x121E00
889 {
890 bank=GOP_REG_GOP4_GW_OFFSET;
891 }
892 else if(bank==0x1000) //GOP4_ST
893 {
894 bank=GOP_REG_GOP4_ST_OFFSET;
895 }
896 #endif
897 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
898 GOP_WRITE2BYTE((direct_addr&0xFFFFF), (u32val&0xFFFF));
899 GOP_WRITE2BYTE((direct_addr&0xFFFFF)+2, (u32val&0xFFFF0000)>>16);
900 break;
901 }
902
903 case GE_REG_BASE:
904 case SC1_REG_BASE:
905 case CKG_REG_BASE:
906 {
907 GOP_WRITE2BYTE((u32addr&0xFFFF), (u32val&0xFFFF));
908 GOP_WRITE2BYTE((u32addr&0xFFFF)+2, (u32val&0xFFFF0000)>>16);
909 break;
910 }
911
912 default:
913 {
914 //Gop lib current do not support this HW ip base
915 MS_ASSERT(0);
916 break;
917 }
918
919 }
920 }
921
922 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
923
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)924 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
925 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
926 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
927 {
928 MS_U8 i=0;
929 HAL_GOP_DEBUGINFO(printf("GOP_Write32Pal : i= %02bx, ARGB = %02bx,%02bx,%02bx,%02bx\n",u8Index, u8A, u8R, u8G, u8B));
930
931 /* Don't care high byte */
932 MS_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
933
934 for(i =(GOP_WordUnit-1);i>4;i--)
935 {
936 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
937 }
938 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
939 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
940 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
941 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
942 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
943 *pREGMAP_Offset += GOP_WordUnit;
944
945 MsOS_FlushMemory(); //make sure cpu write data to dram
946
947 }
948
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)949 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
950 {
951 MS_U16 bpp=0;
952
953 switch ( fbFmt )
954 {
955 case E_DRV_GOP_COLOR_RGB555_BLINK :
956 case E_DRV_GOP_COLOR_RGB565 :
957 case E_DRV_GOP_COLOR_ARGB1555:
958 case E_DRV_GOP_COLOR_RGBA5551:
959 case E_DRV_GOP_COLOR_ARGB4444 :
960 case E_DRV_GOP_COLOR_RGBA4444 :
961 case E_DRV_GOP_COLOR_RGB555YUV422:
962 case E_DRV_GOP_COLOR_YUV422:
963 case E_DRV_GOP_COLOR_2266:
964 bpp = 16;
965 break;
966 case E_DRV_GOP_COLOR_ARGB8888 :
967 case E_DRV_GOP_COLOR_ABGR8888 :
968 bpp = 32;
969 break;
970
971 case E_DRV_GOP_COLOR_I8 :
972 bpp = 8;
973 break;
974
975 default :
976 //print err
977 MS_ASSERT(0);
978 bpp = 0xFFFF;
979 break;
980 }
981 return bpp;
982
983 }
984
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)985 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
986 {
987 MS_U16 regval;
988 /*For compatibility
989 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
990 MS_U8 u8coef_cpt = u8coef;
991
992 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
993 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
994 {
995 switch(u8coef)
996 {
997 case 0x0 :
998 u8coef_cpt = u8coef<<2;
999 break;
1000 case 0x3f :
1001 u8coef_cpt = ((u8coef<<2)|0x3);
1002 break;
1003 default:
1004 u8coef_cpt = ((u8coef<<2)|0x1);
1005 break;
1006 }
1007 }
1008
1009 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
1010 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1011 {
1012 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef&0x3F)<<8);
1013 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
1014 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
1015 }
1016 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
1017 else
1018 {
1019 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1020 {
1021 regval = (MS_U16)(bEnable?(1<<14):0);
1022 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
1023 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
1024 }
1025 else if ((u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)))
1026 {
1027 regval = (MS_U16)(bEnable?(1<<14):0);
1028 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
1029 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
1030 }
1031 else
1032 {
1033 regval = (MS_U16)(bEnable?(1<<14):0);
1034 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN0_CTRL, regval, 0x4000);
1035 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u8coef, 0xFF);
1036 }
1037 }
1038 }
1039
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1040 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1041 {
1042 pGOPHalLocal->va_mmio_base = addr;
1043 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1044 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1045 {
1046 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1047 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1048 {
1049 }
1050
1051
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)1052 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
1053 {
1054 /*A5 GOP dst type:
1055 1: IP (Main)
1056 0: IP (Sub)
1057 2: OP
1058 3: MVOP
1059 4: MVOP (Sub)
1060 6: FRC
1061 11: InsideFRC
1062 */
1063 MS_U16 u16RegVal;
1064 MS_U32 u32BankOffSet;
1065 MS_BOOL bEnable=FALSE;
1066 MS_U16 u16HSyncMask=GOP_BIT14;
1067
1068 if( GopNum >= MAX_GOP_SUPPORT)
1069 {
1070 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,GopNum);
1071 return GOP_INVALID_PARAMETERS;
1072 }
1073
1074 switch (eDstType)
1075 {
1076 case E_DRV_GOP_DST_IP0:
1077 if( (GopNum == E_GOP0) || (GopNum == E_GOP1) )
1078 {
1079 u16RegVal = 0x0;
1080 bEnable = FALSE;
1081 u16HSyncMask=0;
1082 }else{
1083 return GOP_FUN_NOT_SUPPORTED;
1084 }
1085 break;
1086
1087 case E_DRV_GOP_DST_IP0_SUB:
1088 if( (GopNum == E_GOP0) || (GopNum == E_GOP1) )
1089 {
1090 u16RegVal = 0x1;
1091 bEnable = FALSE;
1092 u16HSyncMask=0;
1093 }else{
1094 return GOP_FUN_NOT_SUPPORTED;
1095 }
1096 break;
1097
1098 case E_DRV_GOP_DST_OP0:
1099 u16RegVal = 0x2;
1100 bEnable = FALSE;
1101 u16HSyncMask=GOP_BIT14;
1102 break;
1103
1104 case E_DRV_GOP_DST_IP1:
1105 u16RegVal = 0x5;
1106 bEnable = TRUE;
1107 break;
1108
1109 case E_DRV_GOP_DST_OP1:
1110 u16RegVal = 0x6;
1111 bEnable = TRUE;
1112 u16HSyncMask=GOP_BIT14;
1113 break;
1114
1115 case E_DRV_GOP_DST_DIP:
1116 u16RegVal = 0x8;
1117 bEnable = TRUE;
1118 u16HSyncMask=GOP_BIT14;
1119 break;
1120
1121 default:
1122 return GOP_FUN_NOT_SUPPORTED;
1123 }
1124
1125 if(bOnlyCheck == FALSE)
1126 {
1127 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1128 HAL_GOP_SetGOP2Pto1P(pGOPHalLocal, GopNum, bEnable);
1129 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(3:0));
1130
1131 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
1132 }
1133 return GOP_SUCCESS;
1134 }
1135
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)1136 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
1137 {
1138 /*U4 Mixer dst type:
1139 2: OP
1140 3: VE
1141 */
1142 MS_U16 u16Regval = 0;
1143 DRV_MixerDstType eType=E_DRV_MIXER_DST_VE;
1144
1145 switch(eDstType)
1146 {
1147 case E_DRV_GOP_DST_MIXER2VE:
1148 eType = E_DRV_MIXER_DST_VE;
1149 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //Enable pseudo hsync
1150 break;
1151 case E_DRV_GOP_DST_MIXER2OP:
1152 eType = E_DRV_MIXER_DST_OP;
1153 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT7); //Disable pseudo hsync
1154 break;
1155 default:
1156 break;
1157 }
1158
1159 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, &u16Regval);
1160
1161 u16Regval &= (~(GOP_BIT3|GOP_BIT4));
1162 u16Regval |= (eType<<0x3);
1163
1164 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16Regval, (GOP_BIT3|GOP_BIT4));
1165 return GOP_SUCCESS;
1166 }
1167
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)1168 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
1169 {
1170 MS_U16 u16Regval = 0;
1171
1172 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, &u16Regval);
1173
1174 if(((u16Regval&0x18)>>3) == 0x2)
1175 *pGopDst = E_DRV_GOP_DST_MIXER2OP;
1176 else
1177 *pGopDst = E_DRV_GOP_DST_MIXER2VE;
1178
1179 return GOP_SUCCESS;
1180 }
1181
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1182 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1183 {
1184 /*T8
1185 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
1186 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1187 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
1188 */
1189 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3, gop1gs=4;
1190 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gs<<(GOP_MUX_SHIFT*4))|(gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
1191 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT15 , GOP_BIT15); // trigger
1192
1193 /*Disable VE OSD enable*/
1194 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal, FALSE, EN_OSD_0, 0x4);
1195 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal, FALSE, EN_OSD_1, 0x4);
1196
1197 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_VOPNBL, 1<<7, GOP_BIT7);
1198 return GOP_SUCCESS;
1199 }
1200
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1201 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1202 {
1203 MS_U16 u16GopMux=0;
1204 switch(eGopMux)
1205 {
1206 case E_GOP_MUX0:
1207 case E_GOP_MUX1:
1208 case E_GOP_MUX2:
1209 case E_GOP_MUX3:
1210 case E_GOP_MUX4:
1211 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1212 *u8GOPNum = (u16GopMux >> (eGopMux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1213 break;
1214 case E_GOP_IP0_MUX:
1215 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1216 *u8GOPNum = (u16GopMux&GOP_IP_MAIN_MUX_MASK)>>GOP_IP_MAIN_MUX_SHIFT;
1217 break;
1218 case E_GOP_IP0_SUB_MUX:
1219 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1220 *u8GOPNum = (u16GopMux&GOP_IP_SUB_MUX_MASK)>>GOP_IP_SUB_MUX_SHIFT;
1221 break;
1222 case E_GOP_VOP0_MUX:
1223 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1224 *u8GOPNum = (u16GopMux&GOP_IP_VOP0_MUX_MASK)>>GOP_IP_VOP0_MUX_SHIFT;
1225 break;
1226 case E_GOP_VOP0_SUB_MUX:
1227 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1228 *u8GOPNum = (u16GopMux&GOP_IP_VOP1_MUX_MASK)>>GOP_IP_VOP1_MUX_SHIFT;
1229 break;
1230 case E_GOP_Mix_MUX0:
1231 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1232 *u8GOPNum = (u16GopMux&GOP_Mix_MUX0_MASK)>>GOP_Mix_MUX0_SHIFT;
1233 break;
1234 case E_GOP_Mix_MUX1:
1235 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1236 *u8GOPNum = (u16GopMux&GOP_Mix_MUX1_MASK)>>GOP_Mix_MUX1_SHIFT;
1237 break;
1238 case E_GOP_VE0_MUX:
1239 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1240 *u8GOPNum = (u16GopMux&GOP_VE0_MUX_MASK)>>GOP_VE0_MUX_SHIFT;
1241 break;
1242 case E_GOP_VE1_MUX:
1243 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1244 *u8GOPNum = (u16GopMux&GOP_VE1_MUX_MASK)>>GOP_VE1_MUX_SHIFT;
1245 break;
1246 case E_GOP_DIP_MUX:
1247 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1248 *u8GOPNum = (u16GopMux&GOP_DIP_MUX_MASK)>>GOP_DIP_MUX_SHIFT;
1249 break;
1250 case E_GOP_FRC_MUX0:
1251 case E_GOP_FRC_MUX1:
1252 case E_GOP_FRC_MUX2:
1253 case E_GOP_FRC_MUX3:
1254 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1255 *u8GOPNum = (u16GopMux >> ((eGopMux%E_GOP_FRC_MUX0)*GOP_FRC_MUX_SHIFT))& GOP_FRC_REGMUX_MASK;
1256 break;
1257 case E_GOP_BYPASS_MUX0:
1258 break;
1259 case E_GOP_OP1_MUX:
1260 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_SC1, &u16GopMux);
1261 *u8GOPNum = (u16GopMux& ((BMASK((GOP_MUX_SHIFT-1):0))<<12))>>12;
1262 break;
1263 case E_GOP_IP1_MUX:
1264 case E_GOP_VOP1_MUX:
1265 case E_GOP_GS_MUX:
1266 case E_GOP_DUALRATE_OP_MUX0:
1267 case E_GOP_DUALRATE_OP_MUX1:
1268 case E_GOP_DUALRATE_OP_MUX2:
1269 // to prevent warning log
1270 break;
1271 default:
1272 printf("[%s]ERROR, not support the mux[%d]\n",__FUNCTION__,eGopMux);
1273 break;
1274 }
1275 }
1276
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1277 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1278 {
1279 MS_U16 u16Ret[4]={0};
1280
1281 switch(eGopMux)
1282 {
1283 case E_GOP_MUX0:
1284 case E_GOP_MUX1:
1285 case E_GOP_MUX2:
1286 case E_GOP_MUX3:
1287 case E_GOP_MUX4:
1288 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1289 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT15 , GOP_BIT15); // trigger
1290 break;
1291 case E_GOP_OP1_MUX:
1292 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_SC1, u8GOPNum <<12, GOP_REGMUX_MASK<<12);
1293 break;
1294 case E_GOP_IP0_MUX:
1295 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
1296 break;
1297 case E_GOP_IP1_MUX:
1298 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << 0, BMASK(2:0));
1299 break;
1300 case E_GOP_VOP0_MUX:
1301 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
1302 break;
1303 case E_GOP_VOP1_MUX:
1304 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
1305 break;
1306 case E_GOP_Mix_MUX0:
1307 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX0_SHIFT, GOP_Mix_MUX0_MASK);
1308 break;
1309 case E_GOP_Mix_MUX1:
1310 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX1_SHIFT, GOP_Mix_MUX1_MASK);
1311 break;
1312 case E_GOP_VE0_MUX:
1313 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE0_MUX_SHIFT, GOP_VE0_MUX_MASK);
1314 break;
1315 case E_GOP_VE1_MUX:
1316 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE1_MUX_SHIFT, GOP_VE1_MUX_MASK);
1317 break;
1318 case E_GOP_DIP_MUX:
1319 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1320 break;
1321 case E_GOP_FRC_MUX0:
1322 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1323 break;
1324 case E_GOP_FRC_MUX1:
1325 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1326 break;
1327 case E_GOP_FRC_MUX2:
1328 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1329 break;
1330 case E_GOP_FRC_MUX3:
1331 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1332 break;
1333 case E_GOP_BYPASS_MUX0:
1334 //Check MUX is using? Checking from priority high to low
1335 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, &u16Ret[0]);
1336 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, &u16Ret[1]);
1337 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, &u16Ret[2]);
1338 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, &u16Ret[3]);
1339
1340 //Checking if un-use
1341 if((u16Ret[0] & GOP_BIT0) ==0)
1342 {
1343 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)));
1344 }
1345 else if((u16Ret[1] & GOP_BIT0) ==0)
1346 {
1347 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)));
1348 }
1349 else if((u16Ret[2] & GOP_BIT0) ==0)
1350 {
1351 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)));
1352 }
1353 else if((u16Ret[3] & GOP_BIT0) ==0)
1354 {
1355 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)));
1356 }
1357 else
1358 {
1359 printf("[%s][%d]FRC mux is already full.\n",__FUNCTION__,__LINE__);
1360 }
1361 break;
1362 break;
1363 default:
1364 printf("[%s]ERROR mux setting\n",__FUNCTION__);
1365 break;
1366 }
1367 }
1368
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1369 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1370 {
1371 /* GOP OP Path enable to SC Setting
1372 A5: GOP OP Path blending with SC sequence
1373 mux1-->mux0-->mux2-->mux3
1374 */
1375 MS_BOOL bOSDBEnable=TRUE;
1376 MS_U16 muxValue=0, mux4Value=0, regval=0;
1377
1378 DRV_GOPDstType pGopDst = E_DRV_GOP_DST_INVALID;
1379 MS_U16 u164K2KMuxValue=0;
1380
1381 if(gopNum >= MAX_GOP_SUPPORT)
1382 {
1383 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1384 return GOP_FAIL;
1385 }
1386
1387 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1388 if(bOSDBEnable)
1389 {
1390 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, 0x0, GOP_REG_HW_MASK);
1391
1392 }else
1393 {
1394 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1395 }
1396
1397 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1398 {
1399 if(bOSDBEnable)
1400 {
1401 if(bEnable)
1402 {
1403 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0<<1, GOP_BIT1|GOP_BIT2);
1404 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT3, GOP_BIT3);
1405 }else{
1406 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT3);
1407 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0<<1, GOP_BIT1|GOP_BIT2);
1408 }
1409 }
1410 else
1411 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1412 }
1413
1414 if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1415 {
1416 if(bOSDBEnable)
1417 {
1418 if(bEnable)
1419 {
1420 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 1<<9, GOP_BIT9|GOP_BIT10);
1421 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT11, GOP_BIT11);
1422 }else{
1423 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT11);
1424 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 1<<9, GOP_BIT9|GOP_BIT10);
1425 }
1426 }
1427 else
1428 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12);
1429 }
1430
1431 if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1432 {
1433 if(bOSDBEnable)
1434 {
1435 if(bEnable)
1436 {
1437 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 2<<1, GOP_BIT1|GOP_BIT2);
1438 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT3, GOP_BIT3);
1439 }else{
1440 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT3);
1441 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 2<<1, GOP_BIT1|GOP_BIT2);
1442 }
1443 }
1444 else
1445 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1446 }
1447
1448 if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1449 {
1450 if(bOSDBEnable)
1451 {
1452 if(bEnable)
1453 {
1454 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 3<<9, GOP_BIT9|GOP_BIT10);
1455 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT11, GOP_BIT11);
1456 }else{
1457 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT11);
1458 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 3<<9, GOP_BIT9|GOP_BIT10);
1459 }
1460 }
1461 else
1462 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1463 }
1464
1465
1466 if(MAX_GOP_SUPPORT ==5)
1467 {
1468 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &mux4Value);
1469 if (gopNum== ((mux4Value & GOP_MUX4_MASK)>> GOP_MUX4_SHIFT)) //enable mux4
1470 {
1471 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1472 }
1473 }
1474
1475 /*For FRC mux switch*/
1476 HAL_GOP_GetGOPDst(pGOPHalLocal, gopNum, &pGopDst);
1477 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u164K2KMuxValue);
1478 if (gopNum== (u164K2KMuxValue & GOP_MUX0_MASK))
1479 {
1480 /* Switch FRC blending */
1481 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1482 }
1483
1484 if (gopNum== ((u164K2KMuxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1485 {
1486 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1487 }
1488
1489 if (gopNum== ((u164K2KMuxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1490 {
1491 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1492 }
1493
1494 if (gopNum== ((u164K2KMuxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1495 {
1496 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1497 }
1498
1499 return GOP_SUCCESS;
1500 }
1501
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1502 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1503 {
1504 MS_U32 u32pBankOffSet=0;
1505 MS_U16 u16Regval;
1506
1507 if(g_GopChipPro.b2Pto1PSupport)
1508 {
1509 _GetBnkOfstByGop(gopNum, &u32pBankOffSet);
1510 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, &u16Regval);
1511 HAL_GOP_Write16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, bEnable?(u16Regval |GOP_BIT11):(u16Regval & ~GOP_BIT11), GOP_BIT11);
1512 }
1513 return GOP_SUCCESS;
1514 }
1515
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1516 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1517 {
1518 /* GOP OP Path enable to SC Setting
1519 A5: GOP OP Path blending with SC sequence
1520 mux1-->mux0-->mux2-->mux3
1521 */
1522 MS_U16 muxValue=0, regval=0;
1523
1524 if(gopNum >= MAX_GOP_SUPPORT)
1525 {
1526 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1527 return FALSE;
1528 }
1529
1530 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1531 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1532 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1533 {
1534 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
1535 }
1536 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1537 {
1538 //printf("");
1539 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x1000):(regval & ~0x1000), 0x3000);
1540 }
1541 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1542 {
1543 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
1544 }
1545 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1546 {
1547 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
1548 }
1549 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1550 {
1551 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x4000):(regval & ~0x4000), 0xc000);
1552 }
1553 else
1554 {
1555 return GOP_FAIL;
1556 }
1557 return GOP_SUCCESS;
1558 }
1559
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1560 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1561 {
1562 MS_U16 muxValue=0;
1563 MS_U16 regval37=0;
1564 MS_U16 regval38=0;
1565
1566 if(gopNum >= MAX_GOP_SUPPORT)
1567 {
1568 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1569 return FALSE;
1570 }
1571
1572 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1573 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, ®val37);
1574 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, ®val38);
1575 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1576 {
1577 *pbEnable = (regval37& GOP_BIT5) == GOP_BIT5;
1578 }
1579 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1580 {
1581 *pbEnable = (regval37 & GOP_BIT13) == GOP_BIT13;
1582 }
1583 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1584 {
1585 *pbEnable = (regval38 & GOP_BIT5) == GOP_BIT5;
1586 }
1587 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1588 {
1589 *pbEnable = (regval38 & GOP_BIT13) == GOP_BIT13;
1590 }
1591 else
1592 {
1593 return GOP_FAIL;
1594 }
1595 return GOP_SUCCESS;
1596 }
1597
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1598 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1599 {
1600 /*T8
1601 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1602 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1603 */
1604 MS_U16 Mux3Gop, muxValue=0, i;
1605 MS_U16 MuxShift;
1606
1607 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX3;
1608
1609 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1610 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1611 {
1612 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1613 {
1614 Mux3Gop = (muxValue&GOP_MUX3_MASK)>> MuxShift; //save mux2 gop
1615
1616 muxValue &= ~GOP_MUX3_MASK; //clear mux2 setting
1617 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1618 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1619 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1620 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT15 , GOP_BIT15); // trigger
1621 break;
1622
1623 }
1624
1625 }
1626 return GOP_SUCCESS;
1627 }
1628
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1629 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1630 {
1631 /*T8 GOP dst type:
1632 0: IP (Main)
1633 1: IP (Sub)
1634 2: OP
1635 3: MVOP
1636 */
1637
1638 if(gopNum >= MAX_GOP_SUPPORT)
1639 {
1640 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1641 MS_ASSERT(0);
1642 return GOP_INVALID_PARAMETERS;
1643 }
1644 /* Monaco clkgen setting */
1645 /******************
1646 0: odclk
1647 1: idclk_f2 (ipm)
1648 2: idclk_f1 (ips)
1649 3: ocmixer
1650 4: ve
1651 5 : mvop main
1652 6 : mvop sub
1653 ******************/
1654
1655 switch(eDstType)
1656 {
1657 case E_DRV_GOP_DST_IP0:
1658 if (gopNum==E_GOP0)
1659 {
1660 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 6<<2, CKG_GOPG0_MASK);
1661 }
1662 else if (gopNum==E_GOP1)
1663 {
1664 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 6<<8, CKG_GOPG1_MASK);
1665 }
1666 else
1667 {
1668 MS_ASSERT(0);
1669 return GOP_INVALID_PARAMETERS;
1670 }
1671 break;
1672
1673 case E_DRV_GOP_DST_IP0_SUB:
1674 if (gopNum==E_GOP0)
1675 {
1676 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 6<<2, CKG_GOPG0_MASK);
1677 }
1678 else if (gopNum==E_GOP1)
1679 {
1680 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 6<<8, CKG_GOPG1_MASK);
1681 }
1682 else
1683 {
1684 MS_ASSERT(0);
1685 return GOP_INVALID_PARAMETERS;
1686 }
1687 break;
1688
1689 case E_DRV_GOP_DST_OP0:
1690 if (gopNum==E_GOP0)
1691 {
1692 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0<<2, CKG_GOPG0_MASK);
1693 }
1694 else if (gopNum==E_GOP1)
1695 {
1696 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0<<8, CKG_GOPG1_MASK);
1697 }
1698 else if (gopNum==E_GOP2)
1699 {
1700 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0<<2, CKG_GOPG2_MASK);
1701 }else if (gopNum==E_GOP3)
1702 {
1703 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0<<8, CKG_GOPG3_MASK);
1704 }else if (gopNum==E_GOP5)
1705 {
1706 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, 0<<8, CKG_GOPG5_MASK);
1707 }else
1708 {
1709 MS_ASSERT(0);
1710 return GOP_INVALID_PARAMETERS;
1711 }
1712 break;
1713
1714 case E_DRV_GOP_DST_IP1:
1715 if (gopNum==E_GOP0)
1716 {
1717 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 7<<2, CKG_GOPG0_MASK);
1718 }
1719 else if (gopNum==E_GOP1)
1720 {
1721 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 7<<8, CKG_GOPG1_MASK);
1722 }
1723 else if (gopNum==E_GOP2)
1724 {
1725 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 7<<2, CKG_GOPG2_MASK);
1726 }else if (gopNum==E_GOP3)
1727 {
1728 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 7<<8, CKG_GOPG3_MASK);
1729 }else if (gopNum==E_GOP5)
1730 {
1731 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, 7<<8, CKG_GOPG5_MASK);
1732 }else
1733 {
1734 MS_ASSERT(0);
1735 return GOP_INVALID_PARAMETERS;
1736 }
1737 break;
1738
1739 case E_DRV_GOP_DST_OP1:
1740 if (gopNum==E_GOP0)
1741 {
1742 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 2<<2, CKG_GOPG0_MASK);
1743 }
1744 else if (gopNum==E_GOP1)
1745 {
1746 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 2<<8, CKG_GOPG1_MASK);
1747 }
1748 else if (gopNum==E_GOP2)
1749 {
1750 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 2<<2, CKG_GOPG2_MASK);
1751 }else if (gopNum==E_GOP3)
1752 {
1753 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 2<<8, CKG_GOPG3_MASK);
1754 }else if (gopNum==E_GOP5)
1755 {
1756 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, 2<<8, CKG_GOPG5_MASK);
1757 }else
1758 {
1759 MS_ASSERT(0);
1760 return GOP_INVALID_PARAMETERS;
1761 }
1762 break;
1763
1764 case E_DRV_GOP_DST_DIP:
1765 if (gopNum==E_GOP0)
1766 {
1767 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 3<<2, CKG_GOPG0_MASK);
1768 }
1769 else if (gopNum==E_GOP1)
1770 {
1771 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 3<<8, CKG_GOPG1_MASK);
1772 }
1773 else if (gopNum==E_GOP2)
1774 {
1775 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 3<<2, CKG_GOPG2_MASK);
1776 }else if (gopNum==E_GOP3)
1777 {
1778 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 3<<8, CKG_GOPG3_MASK);
1779 }else if (gopNum==E_GOP5)
1780 {
1781 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, 3<<8, CKG_GOPG5_MASK);
1782 }else
1783 {
1784 MS_ASSERT(0);
1785 return GOP_INVALID_PARAMETERS;
1786 }
1787 break;
1788
1789 default:
1790 MS_ASSERT(0);
1791 return GOP_ENUM_NOT_SUPPORTED;
1792 }
1793
1794 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
1795 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
1796
1797 return GOP_SUCCESS;
1798 }
1799
1800
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1801 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1802 {
1803 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
1804 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1805 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
1806 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1807 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
1808 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1809 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
1810 else
1811 return GOP_INVALID_PARAMETERS;
1812
1813 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
1814 return GOP_SUCCESS;
1815 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1816 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
1817 {
1818 if (bEnable)
1819 {
1820 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
1821 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
1822 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
1823 }
1824 else
1825 {
1826 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
1827 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
1828 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
1829 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
1830 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
1831 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
1832 }
1833
1834 return GOP_SUCCESS;
1835 }
1836
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1837 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1838 {
1839 DRV_GOPDstType MixerDstType;
1840 MS_U16 regval = 0;
1841 MS_U8 u8MUXGOPNum = 0;
1842 int i = 0;
1843
1844 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
1845 #if 0 //TO DO: To disable mixer mux
1846 MS_U16 u16val;
1847 if( regval & 0x0001) //MIXER GOP0 enable -> enable GOP1
1848 {
1849 u16val = (bEnable? TRUE: FALSE);
1850 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (u16val<<1), GOP_BIT1);
1851 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1852 }
1853 else //enable GOP0
1854 {
1855 u16val = (bEnable? TRUE: FALSE);
1856 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16val, GOP_BIT0);
1857 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1858 }
1859 #else
1860 if((regval&(GOP_BIT0|GOP_BIT1)) == (GOP_BIT0|GOP_BIT1))
1861 {
1862 if((gopNum != ((regval&(GOP_BIT10|GOP_BIT11))>>10)) && (gopNum != ((regval&(GOP_BIT12|GOP_BIT13))>>12)))
1863 {
1864 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
1865 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1866 }
1867 }
1868 else if(regval&GOP_BIT0)
1869 {
1870 if(gopNum != ((regval&(GOP_BIT10|GOP_BIT11))>>10))
1871 {
1872 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT1, GOP_BIT1);
1873 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1874 }
1875 }
1876 else if(regval&GOP_BIT1) //gop1Enable
1877 {
1878 if(gopNum != ((regval&(GOP_BIT12|GOP_BIT13))>>12))
1879 {
1880 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT1, GOP_BIT1);
1881 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1882 }
1883 }
1884 else //no one enable
1885 {
1886 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
1887 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1888 }
1889 #endif
1890
1891 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //disable pseudo hsync
1892
1893 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT2); //alpha mode: 0 bypass mode: 1
1894
1895 HAL_GOP_GetMixerDst(pGOPHalLocal,&MixerDstType);
1896 if(MixerDstType == E_DRV_GOP_DST_MIXER2OP)
1897 {
1898 for (i=0; i<MAX_GOP_MUX - 1; i++) //mux3 not supported to OP
1899 {
1900 HAL_GOP_GWIN_GetMUX(pGOPHalLocal, &u8MUXGOPNum, (Gop_MuxSel)i);
1901 if (0x4==u8MUXGOPNum)
1902 {
1903 HAL_GOP_EnableSCNewAlphaMode(pGOPHalLocal, (Gop_MuxSel)i, TRUE);
1904 }
1905 else
1906 {
1907 HAL_GOP_EnableSCNewAlphaMode(pGOPHalLocal, (Gop_MuxSel)i, FALSE);
1908 }
1909 }
1910 }
1911 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, GOP_MIXER_EN_VFIL, GOP_MIXER_EN_VFIL_MASK);
1912 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, GOP_MIXER_VS_FLD_ON, GOP_MIXER_VS_FLD_ON_MASK);
1913 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_REG_DUMMY, GOP_BIT0, GOP_BIT0);
1914 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15); //Enable Mixer
1915
1916 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_PAL_HSTART_OFST, GOP_REG_WORD_MASK);
1917 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_PAL_VSTART_OFST, GOP_REG_WORD_MASK);
1918
1919
1920 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
1921
1922 #if 0 /* PAL System*/
1923 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
1924 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
1925 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_HSTART_OFST, GOP_REG_WORD_MASK);
1926 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_VSTART_OFST, GOP_REG_WORD_MASK);
1927 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, 0x330, GOP_REG_WORD_MASK);
1928 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, 0x25D, GOP_REG_WORD_MASK);
1929 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_PAL_HTOTAL-1, GOP_REG_WORD_MASK);
1930 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_HS_DELAY, GOP_REG_WORD_MASK);
1931 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HS_PIPE, GOP_MIXER_PD, GOP_REG_WORD_MASK);
1932 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
1933 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
1934 #endif
1935 return GOP_SUCCESS;
1936
1937 }
1938
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)1939 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
1940 {
1941 MS_U16 u16val;
1942
1943 if (muxNum >= MAX_MIXER_MUX)
1944 {
1945 MS_CRITICAL_MSG(printf("\n[%s] not support mux%d in this chip version!!",__FUNCTION__, muxNum));
1946 return GOP_FAIL;
1947 }
1948
1949 if(muxNum==MIXER_MUX0Id) //Set GOP to mux0
1950 {
1951 u16val = (bEnable? TRUE: FALSE);
1952 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16val, GOP_BIT0);
1953 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1954 }
1955 else //Set GOP to mux1
1956 {
1957 u16val = (bEnable? TRUE: FALSE);
1958 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (u16val<<1), GOP_BIT1);
1959 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1960 }
1961 return GOP_SUCCESS;
1962
1963 }
1964
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)1965 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
1966 {
1967 MS_U32 u32bankoffset = 0;
1968 DRV_GOPDstType gopDstType = E_DRV_GOP_DST_IP0;
1969 MS_U16 regval = 0x0;
1970
1971 HAL_GOP_GetGOPDst(pGOPHalLocal, u8GOP, &gopDstType);
1972
1973 if(gopDstType == E_DRV_GOP_DST_MIXER2VE)
1974 {
1975
1976 _GetBnkOfstByGop(u8GOP, &u32bankoffset);
1977
1978 if(bEn)
1979 {
1980
1981 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT2, GOP_BIT2); //alpha mode: 0 bypass mode: 1
1982 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoffset + GOP_4G_CTRL0, (MS_U16)~GOP_BIT15, GOP_BIT15);
1983
1984 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
1985
1986 if(u8GOP == ((regval&(GOP_BIT10|GOP_BIT11))>>10))
1987 {
1988 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD_EN, (~BIT(2))|BIT(1), BIT(1)|BIT(2));
1989 }
1990 else if(u8GOP == ((regval&(GOP_BIT12|GOP_BIT13))>>12))
1991 {
1992 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD1_EN, (~BIT(2))|BIT(1), BIT(1)|BIT(2));
1993 }
1994 else
1995 {
1996 printf("[%s][%d]GOP not exisit in VE mux\n",__FUNCTION__,__LINE__);
1997 return GOP_FAIL;
1998 }
1999 }
2000 else
2001 {
2002 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2003 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoffset + GOP_4G_CTRL0, (MS_U16)GOP_BIT15, GOP_BIT15);
2004
2005 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
2006
2007 if(u8GOP == ((regval&(GOP_BIT10|GOP_BIT11))>>10))
2008 {
2009 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD_EN, (~BIT(1))|BIT(2), BIT(1)|BIT(2));
2010 }
2011 else if(u8GOP == ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2012 {
2013 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD1_EN, (~BIT(1))|BIT(2), BIT(1)|BIT(2));
2014 }
2015 else
2016 {
2017 printf("[%s][%d]GOP not exisit in VE mux\n",__FUNCTION__,__LINE__);
2018 return GOP_FAIL;
2019 }
2020 }
2021 }
2022 else
2023 {
2024 printf("[%s][%d]GOP not on Mixer2VE path\n",__FUNCTION__,__LINE__);
2025 return GOP_FAIL;
2026 }
2027
2028 return GOP_SUCCESS;
2029
2030 }
2031
HAL_GOP_EnableSCNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel muxNum,MS_BOOL bEnable)2032 GOP_Result HAL_GOP_EnableSCNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, Gop_MuxSel muxNum, MS_BOOL bEnable)
2033 {
2034 MS_U16 bankTemp = 0;
2035 MS_U16 u16val = 0;
2036
2037 u16val = (bEnable? TRUE: FALSE);
2038 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &bankTemp);
2039 switch (muxNum) //Enable OP new alpha mode
2040 {
2041 case 0:
2042 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x2F, GOP_REG_WORD_MASK);
2043 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BLEND0_GOP_SWITCH, (u16val<<1), GOP_BIT1);
2044 break;
2045 case 1:
2046 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2047 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<6), GOP_BIT6);
2048 break;
2049 case 2:
2050 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2051 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<8), GOP_BIT8);
2052 break;
2053 default:
2054 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2055 break;
2056 }
2057 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, bankTemp, GOP_REG_WORD_MASK);
2058 return GOP_SUCCESS;
2059 }
2060
HAL_GOP_EnableSCPerPixelNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel muxNum,MS_BOOL bEnable)2061 GOP_Result HAL_GOP_EnableSCPerPixelNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, Gop_MuxSel muxNum, MS_BOOL bEnable)
2062 {
2063 MS_U16 bankTemp = 0;
2064 MS_U16 u16val = 0;
2065
2066 u16val = (bEnable? TRUE: FALSE);
2067 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &bankTemp);
2068 switch (muxNum) //Enable OP per pixel new alpha mode
2069 {
2070 case 0:
2071 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x2F, GOP_REG_WORD_MASK);
2072 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BLEND0_GOP_SWITCH, (u16val<<3), GOP_BIT3);
2073 break;
2074 case 1:
2075 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2076 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<14), GOP_BIT14);
2077 break;
2078 case 2:
2079 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2080 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<15), GOP_BIT15);
2081 break;
2082 default:
2083 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2084 break;
2085 }
2086 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, bankTemp, GOP_REG_WORD_MASK);
2087 return GOP_SUCCESS;
2088 }
2089
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)2090 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
2091 {
2092 MS_U32 u32GopIdx;
2093
2094 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
2095 pGOPHalLocal->pHALShared = pHALShared;
2096
2097 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
2098 {
2099 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
2100 }
2101 pGOPHalLocal->pGopChipPro = &pHALShared->gopChipProperty;
2102 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
2103 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2104 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2105 {
2106 }
2107
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)2108 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
2109 {
2110 MS_U8 u8Miu=0xff;
2111 MS_U16 u16RegVal_L=0;
2112 #ifdef GOP_MIU_GROUP2
2113 MS_U16 u16RegVal_H=0;
2114 #endif
2115
2116 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal_L);
2117 #ifdef GOP_MIU_GROUP2
2118 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2119 #endif
2120 if (gwinid<MAX_GOP0_GWIN) //gop0
2121 {
2122 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2123 #ifdef GOP_MIU_GROUP2
2124 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2125 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2126 #else
2127 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2128 #endif
2129 }
2130 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
2131 {
2132 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2133 #ifdef GOP_MIU_GROUP2
2134 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2135 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2136 #else
2137 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2138 #endif
2139 }
2140 else if (gwinid==GOP2_GwinIdBase) //gop2
2141 {
2142 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2143 #ifdef GOP_MIU_GROUP2
2144 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2145 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2146 #else
2147 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2148 #endif
2149 }
2150 else if (gwinid==GOP3_GwinIdBase) //gop3
2151 {
2152 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2153 #ifdef GOP_MIU_GROUP2
2154 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2155 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2156 #else
2157 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2158 #endif
2159 }
2160 else if (gwinid==GOP5_GwinIdBase) //gop5
2161 {
2162 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal_L);
2163 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP5);
2164 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP5);
2165 }
2166 else
2167 {
2168 return GOP_FAIL;
2169 }
2170
2171 if (u8Miu <= 2)
2172 {
2173 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
2174 }
2175 else
2176 {
2177 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2178 return GOP_FAIL;
2179 }
2180 return GOP_SUCCESS;
2181 }
2182
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)2183 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
2184 {
2185 MS_U8 u8Miu=0xff;
2186 MS_U16 u16RegVal_L=0;
2187 MS_U32 u32BnkOfst=0xFFFF;
2188 #ifdef GOP_MIU_GROUP2
2189 MS_U16 u16RegVal_H=0;
2190 #endif
2191
2192 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
2193 {
2194 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
2195 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal_L);
2196
2197 u8Miu= (u16RegVal_L& (GOP_BIT2|GOP_BIT3)) >>2;
2198 }
2199 else
2200 {
2201 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal_L);
2202 #ifdef GOP_MIU_GROUP2
2203 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2204 #endif
2205 switch (gopnum)
2206 {
2207 case 0:
2208 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2209 #ifdef GOP_MIU_GROUP2
2210 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2211 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2212 #else
2213 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2214 #endif
2215 break;
2216 case 1:
2217 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2218 #ifdef GOP_MIU_GROUP2
2219 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2220 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2221 #else
2222 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2223 #endif
2224 break;
2225
2226 case 2:
2227 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2228 #ifdef GOP_MIU_GROUP2
2229 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2230 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2231 #else
2232 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2233 #endif
2234 break;
2235
2236 case 3:
2237 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2238 #ifdef GOP_MIU_GROUP2
2239 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2240 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2241 #else
2242 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2243 #endif
2244 break;
2245 case 5:
2246 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal_L);
2247 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP5);
2248
2249 default:
2250 return 0xff;
2251 break;
2252 }
2253
2254 if(u8Miu > MAX_GOP_MIUSEL )
2255 {
2256 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2257 return 0xff;
2258 }
2259
2260 }
2261 return u8Miu;
2262 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)2263 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
2264 {
2265 MS_U16 u16Regval;
2266 MS_U32 u32pBankOffSet=0;
2267 GOP_Result ret;
2268
2269 if(u8gopNum >= MAX_GOP_SUPPORT)
2270 {
2271 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8gopNum);
2272 *pGopDst = E_DRV_GOP_DST_INVALID;
2273 return GOP_FAIL;
2274 }
2275
2276 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
2277 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
2278
2279 switch (u16Regval&GOP_DST_MASK)
2280 {
2281 case 0:
2282 *pGopDst = E_DRV_GOP_DST_IP0;
2283 ret = GOP_SUCCESS;
2284 break;
2285 case 1:
2286 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
2287 ret = GOP_SUCCESS;
2288 break;
2289 case 2:
2290 *pGopDst = E_DRV_GOP_DST_OP0;
2291 ret = GOP_SUCCESS;
2292 break;
2293 case 5:
2294 *pGopDst = E_DRV_GOP_DST_IP1;
2295 ret = GOP_SUCCESS;
2296 break;
2297 case 6:
2298 *pGopDst = E_DRV_GOP_DST_OP1;
2299 ret = GOP_SUCCESS;
2300 break;
2301 case 8:
2302 *pGopDst = E_DRV_GOP_DST_DIP;
2303 ret = GOP_SUCCESS;
2304 break;
2305 default:
2306 *pGopDst = E_DRV_GOP_DST_INVALID;
2307 ret = GOP_FAIL;
2308 break;
2309 }
2310
2311 return ret;
2312
2313 }
2314
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)2315 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
2316 {
2317 MS_U16 muxValue=0;
2318 MS_U16 u16RegVal= 0, u16RegMsk = 0;
2319 MS_BOOL bSC1_OP=0,bSC1_IP=0;
2320
2321 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
2322
2323 switch(ipSelGop)
2324 {
2325 case MS_DRV_IP0_SEL_GOP0:
2326 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2327 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2328 u16RegVal |= GOP_BIT12;//mux0
2329 else
2330 u16RegVal |= GOP_BIT13;//mux1
2331 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2332 bSC1_OP =FALSE;
2333 bSC1_IP =FALSE;
2334 break;
2335
2336 case MS_DRV_IP0_SEL_GOP1:
2337 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2338 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2339 u16RegVal |= GOP_BIT12;//mux0
2340 else
2341 u16RegVal |= GOP_BIT13;//mux1
2342 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2343 bSC1_OP =FALSE;
2344 bSC1_IP =FALSE;
2345 break;
2346 case MS_DRV_IP0_SEL_GOP2:
2347 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2348 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2349 u16RegVal |= GOP_BIT12;//mux0
2350 else
2351 u16RegVal |= GOP_BIT13;//mux1
2352 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2353 bSC1_OP =FALSE;
2354 bSC1_IP =FALSE;
2355 break;
2356
2357 case MS_DRV_NIP_SEL_GOP0:
2358 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2359 {
2360 u16RegVal = ~GOP_BIT12;//mux0
2361 u16RegMsk = GOP_BIT12;
2362 }
2363 else
2364 {
2365 u16RegVal = ~GOP_BIT13;//mux1
2366 u16RegMsk = GOP_BIT13;
2367 }
2368 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2369 bSC1_OP =FALSE;
2370 bSC1_IP =FALSE;
2371 break;
2372
2373 case MS_DRV_NIP_SEL_GOP1:
2374 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2375 {
2376 u16RegVal = ~GOP_BIT12;//mux0
2377 u16RegMsk = GOP_BIT12;
2378 }
2379 else
2380 {
2381 u16RegVal = ~GOP_BIT13;//mux1
2382 u16RegMsk = GOP_BIT13;
2383 }
2384 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2385 bSC1_OP =FALSE;
2386 bSC1_IP =FALSE;
2387 break;
2388 case MS_DRV_NIP_SEL_GOP2:
2389 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2390 {
2391 u16RegVal = ~GOP_BIT12;//mux0
2392 u16RegMsk = GOP_BIT12;
2393 }
2394 else
2395 {
2396 u16RegVal = ~GOP_BIT13;//mux1
2397 u16RegMsk = GOP_BIT13;
2398 }
2399 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2400 bSC1_OP =FALSE;
2401 bSC1_IP =FALSE;
2402 break;
2403 case MS_DRV_MVOP_SEL:
2404 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2405 u16RegVal |= GOP_BIT12; //mux0
2406 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2407 bSC1_OP =FALSE;
2408 bSC1_IP =FALSE;
2409 break;
2410 case MS_DRV_SC1OP_SEL:
2411 bSC1_OP =TRUE;
2412 bSC1_IP =FALSE;
2413 break;
2414 case MS_DRV_IP1_SEL:
2415 bSC1_OP =FALSE;
2416 bSC1_IP =TRUE;
2417 break;
2418 default:
2419 printf("[%s] ERROR invalid source select\n",__FUNCTION__);
2420 break;
2421 }
2422 if(0 != u16RegMsk)
2423 {
2424 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
2425 }
2426
2427 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bSC1_OP<<14, GOP_BIT14);
2428 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, !bSC1_IP<<11, GOP_BIT11);
2429 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, bSC1_IP<<12, GOP_BIT12);
2430
2431 }
2432
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2433 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2434 {
2435 return GOP_FUN_NOT_SUPPORTED;
2436 }
2437
2438
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2439 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2440 {
2441 return GOP_FUN_NOT_SUPPORTED;
2442 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)2443 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
2444 {
2445 return GOP_FUN_NOT_SUPPORTED;
2446 }
2447
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2448 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
2449 {
2450 return GOP_FUN_NOT_SUPPORTED;
2451 }
2452
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)2453 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
2454 {
2455 if(u32mode == E_GOP_PAL)
2456 {
2457 /* PAL System*/
2458 pGOPHalLocal->pGopChipPro->GOP_VE_PD = 0x73;
2459 pGOPHalLocal->pGopChipPro->GOP_VE_V_Offset = 0x13;
2460 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_BOT_HS, ~GOP_BIT2, GOP_BIT2);
2461 }
2462 else if(u32mode == E_GOP_NTSC)
2463 {
2464 /* NTSC System*/
2465 pGOPHalLocal->pGopChipPro->GOP_VE_PD = 0x65;
2466 pGOPHalLocal->pGopChipPro->GOP_VE_V_Offset = 0xF;
2467 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_BOT_HS, GOP_BIT2, GOP_BIT2);
2468 }
2469 return GOP_SUCCESS;
2470 }
2471
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)2472 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
2473 {
2474
2475 if(u32mode == E_GOP_PAL)
2476 {
2477 /* PAL System*/
2478 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2479 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2480 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_PAL_HSTART_OFST, GOP_REG_WORD_MASK);
2481 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_PAL_VSTART_OFST, GOP_REG_WORD_MASK);
2482 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, GOP_VE_PAL_WIDTH, GOP_REG_WORD_MASK);
2483 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, GOP_VE_PAL_HEIGHT, GOP_REG_WORD_MASK);
2484 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_PAL_HTOTAL-1, GOP_REG_WORD_MASK);
2485 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_PAL_HS_DELAY, GOP_REG_WORD_MASK);
2486 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2487
2488 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2489 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2490 }
2491 else if(u32mode == E_GOP_NTSC)
2492 {
2493 /* NTSC System*/
2494 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2495 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2496 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_NTSC_HSTART_OFST, GOP_REG_WORD_MASK);
2497 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_NTSC_VSTART_OFST, GOP_REG_WORD_MASK);
2498 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, GOP_VE_NTSC_WIDTH, GOP_REG_WORD_MASK);
2499 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, GOP_VE_NTSC_HEIGHT, GOP_REG_WORD_MASK);
2500 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_NTSC_HTOTAL, GOP_REG_WORD_MASK);
2501 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_NTSC_HS_DELAY, GOP_REG_WORD_MASK);
2502
2503 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2504
2505 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2506 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2507 }
2508 else if(u32mode == E_GOP_CUSTOM)
2509 {
2510 return GOP_FUN_NOT_SUPPORTED;
2511 /*
2512 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2513 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2514 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, pTM->hstart, GOP_REG_WORD_MASK);
2515 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, pTM->vstart, GOP_REG_WORD_MASK);
2516 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, pTM->hend, GOP_REG_WORD_MASK);
2517 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, pTM->vend, GOP_REG_WORD_MASK);
2518 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, pTM->htotal, GOP_REG_WORD_MASK);
2519 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, pTM->hsyncdelay, GOP_REG_WORD_MASK);
2520
2521 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2522
2523 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //enable pseudo hsync
2524 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2525 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2526 */
2527 }
2528 else if(u32mode == E_GOP_CUSTOM_OP)
2529 {
2530 return GOP_FUN_NOT_SUPPORTED;
2531 }
2532 return GOP_SUCCESS;
2533 }
2534
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)2535 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
2536 {
2537 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, bEn, GOP_MIXER_EN_VFIL_MASK);
2538 return GOP_SUCCESS;
2539 }
2540
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)2541 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
2542 {
2543 //fix me need to modify tile_32bpp mode in 64b_bus
2544 if(E_DRV_GOP_TILE_DATA_16BPP == tilemode)
2545 {
2546 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_GWIN0_CTRL(u8win), \
2547 bEnable?GOP_BIT15:~GOP_BIT15, GOP_BIT15);
2548 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_DRAM_FADE(u8win), \
2549 ~GOP_BIT7, GOP_BIT7);
2550
2551 }
2552 else if(E_DRV_GOP_TILE_DATA_32BPP == tilemode)
2553 {
2554 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_GWIN0_CTRL(u8win), \
2555 bEnable?GOP_BIT15:~GOP_BIT15, GOP_BIT15);
2556 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_DRAM_FADE(u8win), \
2557 ~GOP_BIT7, GOP_BIT7);
2558 }
2559 else
2560 {
2561 return GOP_FUN_NOT_SUPPORTED;
2562 }
2563
2564 return GOP_SUCCESS;
2565
2566 }
2567
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2568 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2569 {
2570 MS_U32 u32BankOffSet =0;
2571
2572 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2573
2574 if (bEn)
2575 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
2576 else
2577 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
2578
2579 return GOP_SUCCESS;
2580 }
2581
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2582 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2583 {
2584 MS_U32 u32BankOffSet =0;
2585
2586 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2587
2588 if (bEn)
2589 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
2590 else
2591 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
2592
2593 return GOP_SUCCESS;
2594 }
2595
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)2596 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
2597 {
2598 MS_U16 u16Val =0x0;
2599 if (u8win < GOP1_GwinIdBase)
2600 {
2601 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
2602 *pEnable = (MS_BOOL)(u16Val>>15);
2603 }
2604 else if (u8win < GOP2_GwinIdBase)
2605 {
2606 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
2607 *pEnable = (MS_BOOL)(u16Val>>15);
2608 }
2609 else if (u8win < GOP3_GwinIdBase)
2610 {
2611 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
2612 *pEnable = (MS_BOOL)(u16Val>>15);
2613 }
2614 else if (u8win < GOP4_GwinIdBase)
2615 {
2616 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
2617 *pEnable = (MS_BOOL)(u16Val>>15);
2618 }
2619 else if (u8win < GOP5_GwinIdBase)
2620 {
2621 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
2622 *pEnable = (MS_BOOL)(u16Val>>15);
2623 }
2624 else
2625 {
2626 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2627 return GOP_INVALID_PARAMETERS;
2628 }
2629
2630 return GOP_SUCCESS;
2631 }
2632
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)2633 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
2634 {
2635 MS_U16 u16Val = bEnable << 15;
2636 if (u8win < GOP1_GwinIdBase)
2637 {
2638 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), u16Val, GOP_BIT15);
2639 }
2640 else if (u8win < GOP2_GwinIdBase)
2641 {
2642 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), u16Val, GOP_BIT15);
2643 }
2644 else if (u8win < GOP3_GwinIdBase)
2645 {
2646 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u16Val, GOP_BIT15);
2647 }
2648 else if (u8win < GOP4_GwinIdBase)
2649 {
2650 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u16Val, GOP_BIT15);
2651 }
2652 else if (u8win < GOP5_GwinIdBase)
2653 {
2654 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u16Val, GOP_BIT15);
2655 }
2656 else
2657 {
2658 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2659 return GOP_INVALID_PARAMETERS;
2660 }
2661 return GOP_SUCCESS;
2662 }
2663
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)2664 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
2665 {
2666 MS_U16 u16Reg = 0;
2667 MS_U32 u32WordBase = 0;
2668 MS_U32 u32BankOffSet=0;
2669
2670 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2671
2672 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
2673
2674 if(u16Reg & GOP_BIT7)
2675 {
2676 u32WordBase = 1;
2677 }
2678 else
2679 {
2680 u32WordBase = GOP_WordUnit;
2681 }
2682
2683 u32SubAddr /= u32WordBase;
2684
2685 if(u8GOP == E_GOP2)
2686 {
2687 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2688 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2689 }
2690 else if(u8GOP == E_GOP3)
2691 {
2692 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2693 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2694
2695 }
2696 else if(u8GOP == E_GOP4)
2697 {
2698 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2699 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2700 }
2701 else if(u8GOP == E_GOP1)
2702 {
2703 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2704 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2705 }
2706 else //gop0
2707 {
2708 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2709 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2710 }
2711
2712 return GOP_SUCCESS;
2713
2714 }
2715
2716 //------------------------------------------------------------------------------
2717 /// Set VE output with OSD
2718 /// @return none
2719 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)2720 GOP_Result HAL_GOP_VE_SetOSDEnable(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
2721 {
2722 if(eOSD == EN_OSD_0)
2723 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bEnable<<14, GOP_BIT14);
2724
2725 if(eOSD == EN_OSD_1)
2726 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bEnable<<15, GOP_BIT15);
2727 return GOP_SUCCESS;
2728 }
2729
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)2730 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
2731 {
2732 /*
2733 MS_U32 u32BankOffSet=0;
2734 _GetBnkOfstByGop(gopNum, &u32BankOffSet);
2735
2736 //Direct to SC1 OP
2737 HAL_GOP_SetIPSel2SC(pGOPHalLocal, MS_DRV_SC1OP_SEL);
2738 HAL_GOP_SetGOPClk(pGOPHalLocal, gopNum, E_DRV_GOP_DST_OP1);
2739 HAL_GOP_GWIN_SetMUX(pGOPHalLocal,gopNum,E_GOP_OP1_MUX);
2740 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, (MS_U16)~GOP_BIT1, GOP_BIT1);
2741 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, (MS_U16)GOP_BIT15, GOP_BIT15);
2742 */
2743 return GOP_SUCCESS;
2744 }
2745
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)2746 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
2747 {
2748 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2749 MS_U16 u16MVOPMirrorCfg = 0;
2750 MS_U16 u16ScalerMirrorCfg = 0;
2751
2752 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
2753 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
2754 if(bHorizontal) // Horizontal
2755 {
2756 if(u16MVOPMirrorCfg & GOP_BIT1)
2757 {
2758 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2759 }
2760 else if(u16ScalerMirrorCfg & GOP_BIT12)
2761 {
2762 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2763 }
2764 }
2765 else //vertical
2766 {
2767 if(u16MVOPMirrorCfg & GOP_BIT0)
2768 {
2769 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2770 }
2771 else if(u16ScalerMirrorCfg & GOP_BIT13)
2772 {
2773 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2774 }
2775 }
2776 return enMirrorType;
2777 }
2778
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)2779 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
2780 {
2781 MS_U32 u32BankOffSet =0;
2782
2783 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2784 HAL_GOP_Write16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_3D_MIDDLE, u16Middle, GOP_REG_WORD_MASK);
2785 return GOP_SUCCESS;
2786 }
2787
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)2788 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
2789 {
2790 MS_U8 i=0, eGopMux=0, FRCMuxOffset=0;
2791 MS_U16 u16Val=0;
2792 MS_U16 u16Mux[MAX_GOP_MUX];
2793
2794 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16Val);
2795 u16Mux[0] =( u16Val & GOP_MUX0_MASK);
2796 u16Mux[1] =( u16Val & GOP_MUX1_MASK) >> (GOP_MUX_SHIFT*1);
2797 u16Mux[2] =( u16Val & GOP_MUX2_MASK) >> (GOP_MUX_SHIFT*2);
2798 u16Mux[3] =( u16Val & GOP_MUX3_MASK) >> (GOP_MUX_SHIFT*3);
2799 #if (MAX_GOP_MUX>4)
2800 u16Mux[4] =( u16Val & GOP_MUX4_MASK) >> (GOP_MUX_SHIFT*4);
2801 #endif
2802 switch(u8GOP)
2803 {
2804 case E_GOP0:
2805 case E_GOP1:
2806 case E_GOP2:
2807 case E_GOP3:
2808 #if (MAX_GOP_MUX>4)
2809 case E_GOP4:
2810 #endif
2811 for(i=0; i<MAX_GOP_MUX; i++)
2812 {
2813 if(u8GOP == u16Mux[i])
2814 {
2815 eGopMux = i;
2816 #if (MAX_GOP_MUX>4)
2817 if(eGopMux == 4)
2818 {
2819 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, bOCEn<<15, GOP_BIT15);
2820 }
2821 else
2822 #endif
2823 {
2824 FRCMuxOffset = 12 + eGopMux;
2825 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, bOCEn<<FRCMuxOffset, 1<<FRCMuxOffset);
2826 }
2827 }
2828 }
2829 break;
2830 default:
2831 return GOP_FAIL;
2832 break;
2833 }
2834
2835 return GOP_SUCCESS;
2836 }
2837
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)2838 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
2839 {
2840 return GOP_FUN_NOT_SUPPORTED;
2841 }
2842
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)2843 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
2844 {
2845 return GOP_FUN_NOT_SUPPORTED;
2846 }
2847
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)2848 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
2849 {
2850 return GOP_FUN_NOT_SUPPORTED;
2851 }
2852
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)2853 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
2854 {
2855 MS_U32 u32BankOffSet = 0;
2856 MS_BOOL bInverse = 0xFF;
2857 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
2858
2859 switch (eDstType)
2860 {
2861 case E_DRV_GOP_DST_IP0:
2862 case E_DRV_GOP_DST_IP1:
2863 case E_DRV_GOP_DST_OP1:
2864 bInverse = TRUE;
2865 break;
2866 default:
2867 bInverse = FALSE;
2868 break;
2869 }
2870 if(bInverse == TRUE)
2871 {
2872 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 1<<4, 0x10);
2873 }
2874 else
2875 {
2876 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 0<<4, 0x10);
2877 }
2878 return GOP_SUCCESS;
2879 }
2880
2881 /********************************************************************************/
2882 ///Test Pattern
2883 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)2884 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
2885 {
2886 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
2887 {
2888 return GOP_SUCCESS;
2889 }
2890 else
2891 {
2892 return GOP_FAIL;
2893 }
2894
2895 }
2896
2897
2898 /********************************************************************************/
2899 ///GOP Scaling down (internal)
2900 /********************************************************************************/
2901
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2902 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
2903 {
2904 return GOP_FUN_NOT_SUPPORTED;
2905 }
2906
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)2907 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
2908 {
2909 return GOP_FUN_NOT_SUPPORTED;
2910 }
2911
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)2912 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
2913 {
2914 return GOP_FUN_NOT_SUPPORTED;
2915 }
2916
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)2917 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
2918 {
2919 MS_U32 u32BankOffSet=0;
2920
2921 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2922 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
2923 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
2924 return GOP_SUCCESS;
2925 }
2926
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)2927 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
2928 {
2929 MS_U32 u32BankOffSet=0;
2930 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
2931
2932 if (u32GopIdx < MAX_GOP_SUPPORT)
2933 {
2934 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
2935 }
2936 else
2937 {
2938 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
2939 *u16Val = 0;
2940 }
2941 return GOP_SUCCESS;
2942 }
2943
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)2944 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
2945 {
2946 MS_U32 u32BankOffSet=0;
2947 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
2948
2949 if (u32GopIdx < MAX_GOP_SUPPORT)
2950 {
2951 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
2952 }
2953 else
2954 {
2955 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
2956 }
2957 return GOP_SUCCESS;
2958 }
2959
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)2960 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
2961 {
2962 switch(u32PowerState)
2963 {
2964 case E_POWER_SUSPEND:
2965 {
2966 //CLK
2967 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
2968 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
2969 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
2970 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP4CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
2971 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
2972 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[5]));
2973
2974 //XC
2975 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
2976 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
2977 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
2978 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
2979 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
2980 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
2981 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
2982 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
2983 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
2984 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
2985 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
2986 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCALPHA, &(pGOP_STRPrivate->XC_GopReg[11]));
2987 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[12]));
2988 }
2989 break;
2990 case E_POWER_RESUME:
2991 {
2992 //CLK
2993 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
2994 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
2995 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
2996 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
2997 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
2998 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[5], GOP_REG_WORD_MASK);
2999
3000 //XC
3001 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
3002 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
3003 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
3004 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
3005 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
3006 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
3007 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
3008 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
3009 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
3010 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
3011 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
3012 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, pGOP_STRPrivate->XC_GopReg[11], GOP_BIT2);
3013 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[12], GOP_REG_WORD_MASK);
3014 }
3015 break;
3016 default:
3017 break;
3018 }
3019 return GOP_SUCCESS;
3020 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)3021 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
3022 {
3023 return GOP_FUN_NOT_SUPPORTED;
3024 }
3025
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3026 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
3027 {
3028 MS_U32 u32BankOffSet=0xFFFF;
3029
3030 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3031 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SRAM_BORROW, bEnable?GOP_BIT10:0, GOP_BIT10);
3032
3033 return GOP_SUCCESS;
3034 }
3035
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)3036 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
3037 {
3038 MS_U32 u32BankOffSet=0xFFFF;
3039 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3040
3041 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_L, u32size&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3042 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_H, u32size>>16, GOP_REG_WORD_MASK);
3043
3044 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3045 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3046
3047 return GOP_SUCCESS;
3048 }
3049
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)3050 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
3051 {
3052 MS_U32 u32BankOffSet=0xFFFF;
3053 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3054
3055 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3056 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3057
3058 return GOP_SUCCESS;
3059 }
3060
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3061 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3062 {
3063 MS_U32 u32BankOffSet=0xFFFF;
3064 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3065
3066 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
3067 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
3068
3069 return GOP_SUCCESS;
3070 }
3071
HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8win,MS_U16 hstart,MS_U16 hend,MS_U16 vstart,MS_U16 vend)3072 GOP_Result HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 u8win, MS_U16 hstart, MS_U16 hend, MS_U16 vstart, MS_U16 vend)
3073 {
3074 GOP_Result ret = GOP_SUCCESS;
3075
3076 switch(u8GOP)
3077 {
3078 case E_GOP0:
3079 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3080 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3081 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VSTR(u8win), vstart, GOP_REG_WORD_MASK);
3082 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VEND(u8win), vend, GOP_REG_WORD_MASK);
3083 break;
3084
3085 case E_GOP1:
3086 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3087 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3088 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VSTR(u8win), vstart, GOP_REG_WORD_MASK); // 1 pixel
3089 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VEND(u8win), vend, GOP_REG_WORD_MASK); // 1 pixel
3090 break;
3091
3092 case E_GOP2:
3093 case E_GOP3:
3094 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HSTR:GOP_1GX_HSTR, hstart, GOP_REG_WORD_MASK); // word pixels
3095 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HEND:GOP_1GX_HEND, hend, GOP_REG_WORD_MASK); // word pixels
3096 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VSTR:GOP_1GX_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3097 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VEND:GOP_1GX_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3098 break;
3099
3100 default:
3101 printf("invalid Gwin number:%d\n",u8win);
3102 break;
3103 }
3104
3105 return ret;
3106 }
3107
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3108 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3109 {
3110 MS_U32 u32BankOffSet=0xFFFF;
3111 MS_U16 mask_shift=0xFF;
3112
3113 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3114 switch(u8GOP)
3115 {
3116 case E_GOP0:
3117 mask_shift = GOP_MIU_CLIENT_GOP0;
3118 break;
3119 case E_GOP1:
3120 mask_shift = GOP_MIU_CLIENT_GOP1;
3121 break;
3122 case E_GOP2:
3123 mask_shift = GOP_MIU_CLIENT_GOP2;
3124 break;
3125 case E_GOP3:
3126 mask_shift = GOP_MIU_CLIENT_GOP3;
3127 break;
3128 case E_GOP5:
3129 mask_shift = GOP_MIU_CLIENT_GOP5;
3130 break;
3131 break;
3132 default:
3133 mask_shift = 0xFF;
3134 MS_CRITICAL_MSG(printf("ERROR gop miu client\n"));
3135 break;
3136 }
3137 if(u8GOP==E_GOP5)
3138 HAL_GOP_Write16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3139 else
3140 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3141 #ifdef GOP_MIU_GROUP2
3142 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3143 #endif
3144
3145 return GOP_SUCCESS;
3146 }
3147
Hal_SetCropWindow(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,EN_GOP_CROP_CTL crop_mode)3148 GOP_Result Hal_SetCropWindow(
3149 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3150 MS_U8 u8GOP,
3151 EN_GOP_CROP_CTL crop_mode
3152 )
3153 {
3154 return GOP_SUCCESS;
3155 }
3156
HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * u8Core)3157 GOP_Result HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8* u8Core)
3158 {
3159 if(u8GOP==0)
3160 {
3161 *u8Core=0;
3162 }
3163 else
3164 {
3165 *u8Core=1;
3166 }
3167 return GOP_SUCCESS;
3168 }
3169
3170 #ifdef GOP_CMDQ_ENABLE
HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * cmdq_struct,MS_U32 * number,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)3171 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
3172 {
3173 MS_U16 u16xcSubbank=0;
3174 MS_U32 bank;
3175 MS_U32 direct_addr;
3176
3177 switch (u32addr & 0xFF00)
3178 {
3179 case GOP_REG_BASE:
3180 {
3181 bank = (u32addr & 0xFF0000) >> 8;
3182 #if 0 //for GOP4
3183 if(bank==0xE00)//GOP4: 0x121B00
3184 {
3185 bank=GOP_REG_GOP4_BK_OFFSET;
3186 }
3187 else if(bank==0xF00)//GWIN4: 0x121E00
3188 {
3189 bank=GOP_REG_GOP4_GW_OFFSET;
3190 }
3191 else if(bank==0x1000) //GOP4_ST
3192 {
3193 bank=GOP_REG_GOP4_ST_OFFSET;
3194 }
3195 #endif
3196 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
3197
3198 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3199 cmdq_struct[(*number)].destionation_value = u16val;
3200 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3201 cmdq_struct[(*number)].operation = 0x57;
3202 (*number)++;
3203 break;
3204 }
3205 case SC1_REG_BASE:
3206 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
3207 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
3208
3209 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3210 cmdq_struct[(*number)].destionation_value = u16val;
3211 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3212 cmdq_struct[(*number)].operation = 0x57;
3213 (*number)++;
3214 break;
3215 case GE_REG_BASE:
3216 case CKG_REG_BASE:
3217 case MIU_REG_BASE:
3218 {
3219 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
3220 cmdq_struct[(*number)].destionation_value = u16val;
3221 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3222 cmdq_struct[(*number)].operation = 0x57;
3223 (*number)++;
3224 break;
3225 }
3226 #ifdef GOP_MIU_GROUP2
3227 case (MIU2_REG_BASE & 0xFF00):
3228 {
3229 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3230
3231 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3232 cmdq_struct[(*number)].destionation_value = u16val;
3233 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3234 cmdq_struct[(*number)].operation = 0x57;
3235 (*number)++;
3236 break;
3237 }
3238 #endif
3239 default:
3240 {
3241 //Gop lib current do not support this HW ip base
3242 MS_ASSERT(0);
3243 break;
3244 }
3245
3246 }
3247 return GOP_SUCCESS;
3248 }
HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 * u32GopIdx)3249 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
3250 {
3251 MS_U32 u32BankOffSet=0xFFFF;
3252 MS_U16 u16RegVal1 = 0;
3253 MS_BOOL bCheckValidGop = FALSE;
3254 MS_U8 u8CheckTimeCnt = 0;
3255 MS_U8 u8CurrentCmdGop = 0;
3256
3257 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
3258 {
3259 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
3260 {
3261 u8CurrentCmdGop = 0;
3262 }
3263 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
3264 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
3265 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
3266 {
3267 bCheckValidGop = FALSE;
3268 }
3269 else
3270 {
3271 bCheckValidGop = TRUE;
3272 break;
3273 }
3274
3275 // if current gop not init, use next gop instead, check order 0->2->1->3
3276 switch (u8CurrentCmdGop)
3277 {
3278 case 0:
3279 u8CurrentCmdGop = 2;
3280 break;
3281 case 1:
3282 u8CurrentCmdGop = 0;
3283 break;
3284 case 2:
3285 u8CurrentCmdGop = 3;
3286 break;
3287 case 3:
3288 u8CurrentCmdGop = 1;
3289 break;
3290 default:
3291 u8CurrentCmdGop = 0;
3292 break;
3293 }
3294 u8CheckTimeCnt++;
3295 }
3296 if (!bCheckValidGop)
3297 {
3298 printf("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
3299 }
3300
3301 *u32GopIdx = u8CurrentCmdGop;
3302 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
3303 (*number)++;
3304 return GOP_SUCCESS;
3305 }
HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 u32GopIdx)3306 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
3307 {
3308 CH_Struct ch_fire;
3309 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,u32FireBankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
3310 MS_U16 u16ret = 0,u16ret1 = 0;
3311 int i = 0;
3312
3313
3314 _GetBnkOfstByGop(0, &u32BankOffSet);
3315 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
3316 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
3317 #if 0 //for Debug
3318 for(i=0;i<(*number);i++)
3319 {
3320 printf("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
3321 }
3322 #endif
3323 ch_fire.Command_Number = *number;
3324 ch_fire.Pointer_To_CAFArray = target;
3325 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
3326 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
3327 {
3328 Receive_Return_Value = 0;
3329 MDrv_CMDQ_Printf_Crash_Command();
3330 }
3331
3332 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
3333 MsOS_DelayTask(1);
3334 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
3335 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
3336
3337 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3338 timer1 = MsOS_GetSystemTime();
3339 timer2 = MsOS_GetSystemTime();
3340 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
3341 {
3342 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3343 MsOS_DelayTask(1);
3344 timer2 = MsOS_GetSystemTime();
3345 }
3346 if(u16ret1 != (u16ret+1))
3347 {
3348 printf("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
3349 MDrv_CMDQ_Printf_Crash_Command();
3350 }
3351 return GOP_SUCCESS;
3352 }
3353
HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)3354 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
3355 {
3356 CAF_Struct fire_struct[24];
3357 MS_U32 u32BankOffSet;
3358 MS_U32 number = 0;
3359 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
3360 MS_U16 u16RegMiu=0, u16RegCoreEna=0;
3361 MS_U32 fireGOP=0;
3362
3363 _GetBnkOfstByGop(gop, &u32BankOffSet);
3364
3365 if(gop == E_GOP5)
3366 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal1);
3367 else
3368 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3369 #ifdef GOP_MIU_GROUP2
3370 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3371 #endif
3372 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3373 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3374
3375 switch(gop)
3376 {
3377 case E_GOP0:
3378 {
3379 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3380 break;
3381 }
3382 case E_GOP1:
3383 {
3384 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3385 break;
3386 }
3387 case E_GOP2:
3388 {
3389 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3390 break;
3391 }
3392 case E_GOP3:
3393 {
3394 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3395 break;
3396 }
3397 case E_GOP4:
3398 {
3399 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3400 break;
3401 }
3402 default:
3403 {
3404 MS_ASSERT(0);
3405 break;
3406 }
3407 }
3408 if(bMIUSelect[gop] == TRUE)
3409 {
3410 if(u16MIUSelect[gop] == 0)
3411 {
3412 u16RegVal1 &= ~(1<<u16MiuClient);
3413 u16RegVal3 &= ~(1<<u16MiuClient);
3414 }
3415 else if(u16MIUSelect[gop] == 1)
3416 {
3417 u16RegVal1 |= (1<<u16MiuClient);
3418 u16RegVal3 &= ~(1<<u16MiuClient);
3419 }
3420 else if(u16MIUSelect[gop] == 2)
3421 {
3422 u16RegVal1 &= ~(1<<u16MiuClient);
3423 u16RegVal3 |= (1<<u16MiuClient);
3424 }
3425 else if(u16MIUSelect[gop] == 3)
3426 {
3427 u16RegVal1 |= (1<<u16MiuClient);
3428 u16RegVal3 |= (1<<u16MiuClient);
3429 }
3430 bMIUSelect[gop] = FALSE;
3431 }
3432
3433 if(bAFBCMIUSelect[gop] == TRUE)
3434 {
3435 bAFBCMIUSelect[gop] = FALSE;
3436 }
3437 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3438 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3439 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3440
3441 MS_U8 u8Core=0;
3442 HAL_GOP_AFBC_GetCore(pGOPHalLocal, gop, &u8Core);
3443 if(g_GopChipPro.bAFBCCore_Merge_GOP_Trig[gop] ==FALSE)
3444 {
3445 if(bAFBCMIUSelect[gop] == TRUE)
3446 {
3447 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU(u8Core),u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3448 bAFBCMIUSelect[gop] = FALSE;
3449 }
3450 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU(u8Core),u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3451 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER(u8Core),GOP_BIT1, 0xFFFF);
3452 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER(u8Core),GOP_BIT0, 0xFFFF);
3453 }
3454 #ifdef GOP_MIU_GROUP2
3455 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3456 #endif
3457
3458 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3459 return GOP_SUCCESS;
3460 }
3461
HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)3462 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
3463 {
3464 CAF_Struct fire_struct[24];
3465 MS_U32 u32BankOffSet=0;
3466 MS_U32 number = 0;
3467 MS_U8 gop=0;
3468 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
3469 MS_U16 u16RegMiu=0,u16RegCoreEna=0;
3470 MS_U8 u8Core=0;
3471 MS_U32 fireGOP=0;
3472 MS_BOOL bCoreTrig[AFBC_CORE_COUNT];
3473 MS_BOOL bCoreMiu[AFBC_CORE_COUNT];
3474 MS_U8 i=0;
3475
3476 for(i=0;i<AFBC_CORE_COUNT;i++)
3477 {
3478 bCoreTrig[i]=FALSE;
3479 }
3480
3481 if(gop == E_GOP5)
3482 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal1);
3483 else
3484 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3485 #ifdef GOP_MIU_GROUP2
3486 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3487 #endif
3488 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3489
3490 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
3491 {
3492 switch(gop)
3493 {
3494 case E_GOP0:
3495 {
3496 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3497 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP0, &u8Core);
3498 bCoreTrig[u8Core]=TRUE;
3499 break;
3500 }
3501 case E_GOP1:
3502 {
3503 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3504 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP1, &u8Core);
3505 bCoreTrig[u8Core]=TRUE;
3506 break;
3507 }
3508 case E_GOP2:
3509 {
3510 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3511 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP2, &u8Core);
3512 bCoreTrig[u8Core]=TRUE;
3513 break;
3514 }
3515 case E_GOP3:
3516 {
3517 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3518 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP3, &u8Core);
3519 bCoreTrig[u8Core]=TRUE;
3520 break;
3521 }
3522 case E_GOP5:
3523 {
3524 u16MiuClient = GOP_MIU_CLIENT_GOP5;
3525 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP5, &u8Core);
3526 bCoreTrig[u8Core]=TRUE;
3527 break;
3528 }
3529 default:
3530 {
3531 continue;
3532 }
3533 }
3534 if( ( u16GopMask & (1<<gop) ) )
3535 {
3536 _GetBnkOfstByGop(gop, &u32BankOffSet);
3537 if(bMIUSelect[gop] == TRUE)
3538 {
3539 if(u16MIUSelect[gop] == 0)
3540 {
3541 u16RegVal1 &= ~(1<<u16MiuClient);
3542 u16RegVal3 &= ~(1<<u16MiuClient);
3543 }
3544 else if(u16MIUSelect[gop] == 1)
3545 {
3546 u16RegVal1 |= (1<<u16MiuClient);
3547 u16RegVal3 &= ~(1<<u16MiuClient);
3548 }
3549 else if(u16MIUSelect[gop] == 2)
3550 {
3551 u16RegVal1 &= ~(1<<u16MiuClient);
3552 u16RegVal3 |= (1<<u16MiuClient);
3553 }
3554 else if(u16MIUSelect[gop] == 3)
3555 {
3556 u16RegVal1 |= (1<<u16MiuClient);
3557 u16RegVal3 |= (1<<u16MiuClient);
3558 }
3559 bMIUSelect[gop] = FALSE;
3560 }
3561 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3562 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3563 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3564 }
3565
3566 if(bAFBCMIUSelect[gop] == TRUE)
3567 {
3568 HAL_GOP_AFBC_GetCore(pGOPHalLocal, gop, &u8Core);
3569 bCoreMiu[gop]=TRUE;
3570 bAFBCMIUSelect[gop] = FALSE;
3571 }
3572 }
3573
3574 for(i=0;i<AFBC_CORE_COUNT;i++)
3575 {
3576 if(g_GopChipPro.bAFBCCore_Merge_GOP_Trig[i] == FALSE)
3577 {
3578 if(bCoreTrig[i]==TRUE)
3579 {
3580 if((g_GopChipPro.bAFBCMIUSelDoubleBuffer[i] == FALSE)&&(bCoreMiu[i]==TRUE))
3581 {
3582 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU(i),u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3583 }
3584 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER(i),GOP_BIT1, 0xFFFF);
3585 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER(i),GOP_BIT0, 0xFFFF);
3586 }
3587 }
3588 }
3589
3590 if(gop == E_GOP5)
3591 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP5_MIU_GROUP1,u16RegVal1,0xFFFF);
3592 else
3593 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3594 #ifdef GOP_MIU_GROUP2
3595 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3596 #endif
3597 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3598 return GOP_SUCCESS;
3599 }
3600 #endif
3601