1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _REG_MIU_H_ 80 #define _REG_MIU_H_ 81 82 //------------------------------------------------------------------------------------------------- 83 // Hardware Capability 84 //------------------------------------------------------------------------------------------------- 85 86 //------------------------------------------------------------------------------------------------- 87 // Macro and Define 88 //------------------------------------------------------------------------------------------------- 89 #define BITS_RANGE(range) (BIT(((1)?range)+1) - BIT((0)?range)) 90 #define BITS_RANGE_VAL(x, range) ((x & BITS_RANGE(range)) >> ((0)?range)) 91 92 #define MIU_REG_BASE (0x1200UL) 93 #define MIU1_REG_BASE (0x0600UL) 94 #define MIU2_REG_BASE (0x62000UL) 95 #define MIU3_REG_BASE (0x62400UL) 96 #define MIU_ARB_REG_BASE (0x61500UL) //MIU0, Group 4~7 97 #define MIU1_ARB_REG_BASE (0x62200UL) //MIU1, Group 4~7 98 #define MIU2_ARB_REG_BASE (0x62300UL) //MIU2, Group 4~7 99 100 #define PM_REG_BASE (0x1E00UL) 101 #define MIU_ATOP_BASE (0x10D00UL) 102 #define MIU1_ATOP_BASE (0x61600UL) 103 #define MIU2_ATOP_BASE (0x62100UL) 104 #define MIU3_ATOP_BASE (0x62500UL) 105 #define CHIP_TOP_BASE (0x1E00UL) 106 107 #define PM_CHIP_REVISION (PM_REG_BASE + 0x03) //0x001E03 108 //#define DDR_FREQ_SET_0 (MIU_REG_BASE + 0x20) //0x101220 109 //#define DDR_FREQ_SET_1 (MIU_REG_BASE + 0x21) //0x101221 110 //#define DDR_FREQ_DIV_1 (MIU_REG_BASE + 0x25) //0x101225 111 //#define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE + 0x26) //0x101226 112 //#define DDR_FREQ_LOOP_DIV_2 (MIU_REG_BASE + 0x27) //0x101227 113 //#define DDR_CLK_SELECT (MIU_REG_BASE + 0x3e) //0x10123E 114 //#define DDR_FREQ_STATUS (MIU_REG_BASE + 0x3f) //0x10123F 115 116 #define MIU_RQ0L_MASK (MIU_REG_BASE + 0x46) 117 #define MIU_RQ0H_MASK (MIU_REG_BASE + 0x47) 118 #define MIU_RQ1L_MASK (MIU_REG_BASE + 0x66) 119 #define MIU_RQ1H_MASK (MIU_REG_BASE + 0x67) 120 #define MIU_RQ2L_MASK (MIU_REG_BASE + 0x86) 121 #define MIU_RQ2H_MASK (MIU_REG_BASE + 0x87) 122 #define REG_MIU_RQX_MASK(x) (0x46 + 0x20 * x) 123 #define REG_MIU_ARB_RQX_MASK(x) (0x06+0x20*x) //MIU Arb, Group 4~7 124 #define REG_MIU_RQX_HPMASK(x) (0x48 + 0x20 * x) 125 126 #define MIU_PROTECT_EN (MIU_REG_BASE + 0xD2) 127 #define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE + 0xD3) 128 //#define MIU_PROTECT_DDR_SIZE_MASK BITS_RANGE(11:8) 129 #define MIU_PROTECT_DDR_32MB (0x50) 130 #define MIU_PROTECT_DDR_64MB (0x60) 131 #define MIU_PROTECT_DDR_128MB (0x70) 132 #define MIU_PROTECT_DDR_256MB (0x80) 133 #define MIU_PROTECT_DDR_512MB (0x90) 134 #define MIU_PROTECT_DDR_1024MB (0xA0) 135 #define MIU_PROTECT_DDR_2048MB (0xB0) 136 137 #define MIU_PROTECT0_ID0 (MIU_REG_BASE + 0x2E) 138 #define MIU_BW_REQUEST (MIU_REG_BASE + 0x1A) 139 #define MIU_BW_RESULT (MIU_REG_BASE + 0x1C) 140 #define MIU_PROTECT0_ID_ENABLE (MIU_REG_BASE + 0x20) 141 #define MIU_PROTECT1_ID_ENABLE (MIU_REG_BASE + 0x22) 142 #define MIU_PROTECT2_ID_ENABLE (MIU_REG_BASE + 0x24) 143 #define MIU_PROTECT3_ID_ENABLE (MIU_REG_BASE + 0x26) 144 #define MIU_PROTECT0_MSB (MIU_REG_BASE + 0xD0) 145 #define MIU_PROTECT0_START (MIU_REG_BASE + 0xC0) 146 #define MIU_PROTECT1_START (MIU_REG_BASE + 0xC4) 147 #define MIU_PROTECT2_START (MIU_REG_BASE + 0xC8) 148 #define MIU_PROTECT3_START (MIU_REG_BASE + 0xCC) 149 #define REG_MIU_PROTECT_LOADDR (0x6D << 1) //0xDE 150 #define REG_MIU_PROTECT_HIADDR (0x6E << 1) //0xDE 151 #define REG_MIU_GROUP_PRIORITY (0x7F << 1) 152 #define REG_MIU_PROTECT_STATUS (0x6F << 1) //0xDE 153 154 // MIU selection registers 155 #define REG_MIU_SEL0 (MIU_REG_BASE + 0xf0) //0x12F0 156 #define REG_MIU_SEL1 (MIU_REG_BASE + 0xf2) //0x12F1 157 #define REG_MIU_SEL2 (MIU_REG_BASE + 0xf4) //0x12F2 158 #define REG_MIU_SEL3 (MIU_REG_BASE + 0xf6) //0x12F3 159 #define REG_MIU_SELX(x) (0xF0 + x * 2) 160 161 //MIU1 162 #define MIU1_PROTECT_EN (MIU1_REG_BASE + 0xD2) 163 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE + 0xD3) 164 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE + 0x2E) 165 #define MIU1_BW_REQUEST (MIU1_REG_BASE + 0x1A) 166 #define MIU1_BW_RESULT (MIU1_REG_BASE + 0x1C) 167 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE + 0x20) 168 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE + 0x22) 169 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE + 0x24) 170 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE + 0x26) 171 #define MIU1_PROTECT0_MSB (MIU1_REG_BASE + 0xD0) 172 #define MIU1_PROTECT0_START (MIU1_REG_BASE + 0xC0) 173 #define MIU1_PROTECT1_START (MIU1_REG_BASE + 0xC4) 174 #define MIU1_PROTECT2_START (MIU1_REG_BASE + 0xC8) 175 #define MIU1_PROTECT3_START (MIU1_REG_BASE + 0xCC) 176 177 //MIU2 178 #define MIU2_PROTECT_EN (MIU2_REG_BASE + 0xD2) 179 #define MIU2_PROTECT_DDR_SIZE (MIU2_REG_BASE + 0xD3) 180 #define MIU2_PROTECT0_ID0 (MIU2_REG_BASE + 0x2E) 181 #define MIU2_BW_REQUEST (MIU2_REG_BASE + 0x1A) 182 #define MIU2_BW_RESULT (MIU2_REG_BASE + 0x1C) 183 #define MIU2_PROTECT0_ID_ENABLE (MIU2_REG_BASE + 0x20) 184 #define MIU2_PROTECT1_ID_ENABLE (MIU2_REG_BASE + 0x22) 185 #define MIU2_PROTECT2_ID_ENABLE (MIU2_REG_BASE + 0x24) 186 #define MIU2_PROTECT3_ID_ENABLE (MIU2_REG_BASE + 0x26) 187 #define MIU2_PROTECT0_MSB (MIU2_REG_BASE + 0xD0) 188 #define MIU2_PROTECT0_START (MIU2_REG_BASE + 0xC0) 189 #define MIU2_PROTECT1_START (MIU2_REG_BASE + 0xC4) 190 #define MIU2_PROTECT2_START (MIU2_REG_BASE + 0xC8) 191 #define MIU2_PROTECT3_START (MIU2_REG_BASE + 0xCC) 192 193 //MIU2 194 #define MIU3_PROTECT_EN (MIU3_REG_BASE + 0xD2) 195 #define MIU3_PROTECT_DDR_SIZE (MIU3_REG_BASE + 0xD3) 196 #define MIU3_PROTECT0_ID0 (MIU3_REG_BASE + 0x2E) 197 #define MIU3_BW_REQUEST (MIU3_REG_BASE + 0x1A) 198 #define MIU3_BW_RESULT (MIU3_REG_BASE + 0x1C) 199 #define MIU3_PROTECT0_ID_ENABLE (MIU3_REG_BASE + 0x20) 200 #define MIU3_PROTECT1_ID_ENABLE (MIU3_REG_BASE + 0x22) 201 #define MIU3_PROTECT2_ID_ENABLE (MIU3_REG_BASE + 0x24) 202 #define MIU3_PROTECT3_ID_ENABLE (MIU3_REG_BASE + 0x26) 203 #define MIU3_PROTECT0_MSB (MIU3_REG_BASE + 0xD0) 204 #define MIU3_PROTECT0_START (MIU3_REG_BASE + 0xC0) 205 #define MIU3_PROTECT1_START (MIU3_REG_BASE + 0xC4) 206 #define MIU3_PROTECT2_START (MIU3_REG_BASE + 0xC8) 207 #define MIU3_PROTECT3_START (MIU3_REG_BASE + 0xCC) 208 209 #define REG_MIU_I64_MODE (BIT7) 210 #define REG_MIU_INIT_DONE (BIT15) 211 212 //Protection Status 213 #define REG_MIU_PROTECT_LOG_CLR (BIT0) 214 #define REG_MIU_PROTECT_IRQ_MASK (BIT1) 215 #define REG_MIU_PROTECT_HIT_FALG (BIT4) 216 #define REG_MIU_PROTECT_HIT_ID 14:8 217 #define REG_MIU_PROTECT_HIT_NO 7:5 218 219 // MIU Scramble 220 #define REG_MIU_SCRAMBLE_EN (MIU_REG_BASE + 0x06) 221 222 //MIU Bus Width 223 #define REG_MI64_FORCE (CHIP_TOP_BASE + 0x40) 224 //------------------------------------------------------------------------------------------------- 225 //MAU 226 // 227 //------------------------------------------------------------------------------------------------- 228 #define RIUBASE_MAU0 0x1840UL 229 #define RIUBASE_MAU1 0x1860UL 230 231 232 //------------------------------------------------------------------------------------------------- 233 // MIU ATOP registers 234 //------------------------------------------------------------------------------------------------- 235 #define MIU_DDFSTEP (0x28)//0x110D28 236 #define MIU_SSC_EN (0x29)//0x110D29 237 #define MIU_DDFSPAN (0x2A)//0x110D2A 238 #define MIU_DDFSET (0x30) 239 //#define MIU_PLL_INPUT_DIV_2ND (0x34) // no this reg in Einstein 240 #define MIU_PLL_LOOP_DIV_2ND (0x34) 241 //xxx_div_first 242 #define MIU_PLLCTRL (0x36) 243 #define MIU_DDRPLL_DIV_FIRST (0x37) 244 245 //------------------------------------------------------------------------------------------------- 246 // Type and Structure 247 //------------------------------------------------------------------------------------------------- 248 249 250 #endif // _REG_MIU_H_ 251 252