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Searched refs:L_BK_LPLL (Results 1 – 25 of 71) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_display.c839 W2BYTEMSK(L_BK_LPLL(0x7E), BIT(15), BIT(15)); //open sprend mode in _MApi_XC_FPLL_EnableSpreadMode()
840 W2BYTEMSK(L_BK_LPLL(0x7A), u8FrameOutdiv-1 , 0x00FF); in _MApi_XC_FPLL_EnableSpreadMode()
841 W2BYTEMSK(L_BK_LPLL(0x19), u32Spreadmodetemp, 0xFFFF); in _MApi_XC_FPLL_EnableSpreadMode()
842 W2BYTEMSK(L_BK_LPLL(0x1A), u32Spreadmodetemp>>16, 0xFFFF); in _MApi_XC_FPLL_EnableSpreadMode()
849 W2BYTEMSK(L_BK_LPLL(0x7E), 0 , BIT(15)); //close sprend mode in _MApi_XC_FPLL_EnableSpreadMode()
850 W2BYTEMSK(L_BK_LPLL(0x7A), 0, 0x00FF); in _MApi_XC_FPLL_EnableSpreadMode()
851 W2BYTEMSK(L_BK_LPLL(0x19), 0, 0xFFFF); in _MApi_XC_FPLL_EnableSpreadMode()
852 W2BYTEMSK(L_BK_LPLL(0x1A), 0, 0xFFFF); in _MApi_XC_FPLL_EnableSpreadMode()
1189 MDrv_Write2ByteMask(L_BK_LPLL(0x3C), 0, BIT(11)); in MDrv_SC_Cal_FRC_Output_Vfreq()
1193 MDrv_Write2ByteMask(L_BK_LPLL(0x3C), BIT(11), BIT(11)); in MDrv_SC_Cal_FRC_Output_Vfreq()
[all …]
H A Dmdrv_sc_display.c.0839 W2BYTEMSK(L_BK_LPLL(0x7E), BIT(15), BIT(15)); //open sprend mode
840 W2BYTEMSK(L_BK_LPLL(0x7A), u8FrameOutdiv-1 , 0x00FF);
841 W2BYTEMSK(L_BK_LPLL(0x19), u32Spreadmodetemp, 0xFFFF);
842 W2BYTEMSK(L_BK_LPLL(0x1A), u32Spreadmodetemp>>16, 0xFFFF);
849 W2BYTEMSK(L_BK_LPLL(0x7E), 0 , BIT(15)); //close sprend mode
850 W2BYTEMSK(L_BK_LPLL(0x7A), 0, 0x00FF);
851 W2BYTEMSK(L_BK_LPLL(0x19), 0, 0xFFFF);
852 W2BYTEMSK(L_BK_LPLL(0x1A), 0, 0xFFFF);
1187 MDrv_Write2ByteMask(L_BK_LPLL(0x3C), 0, BIT(11));
1191 MDrv_Write2ByteMask(L_BK_LPLL(0x3C), BIT(11), BIT(11));
[all …]
/utopia/UTPA2-700.0.x/modules/xc/drv/pnl/
H A DdrvPNL.c456 W2BYTEMSK(L_BK_LPLL(0x0C), FALSE, BIT(3)); in _MDrv_PNL_Init_Output_Dclk()
457 W4BYTE(L_BK_LPLL(0x0F), u32OutputDclk); in _MDrv_PNL_Init_Output_Dclk()
1052 u32PLL_SET = R4BYTE(L_BK_LPLL(0x0F)); in MDrv_PNL_SetSSC()
1063 W2BYTE(L_BK_LPLL(0x17), u16Step & 0x03FF);// LPLL_STEP in MDrv_PNL_SetSSC()
1064 W2BYTE(L_BK_LPLL(0x18), u16Span & 0x3FFF);// LPLL_SPAN in MDrv_PNL_SetSSC()
1065 W2BYTEMSK((L_BK_LPLL(0x0D)), (bEnable << 11), BIT(11)); // Enable ssc in MDrv_PNL_SetSSC()
1368 W2BYTEMSK((L_BK_LPLL(0x0D)), (bEnable << 11), BIT(11)); // Enable ssc in MDrv_PNL_SetSSC_En()
1385 u32PLL_SET = R4BYTE(L_BK_LPLL(0x0F)); in MDrv_PNL_SetSSC_Fmodulation()
1391 W2BYTE(L_BK_LPLL(0x18), (MS_U16)u64Span & 0x3FFF);// LPLL_SPAN in MDrv_PNL_SetSSC_Fmodulation()
1405 u32PLL_SET = R4BYTE(L_BK_LPLL(0x48)); in MDrv_PNL_SetOSDSSC_Fmodulation()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.c405 W2BYTE(L_BK_LPLL(0x42),0x1000); // {H_BK_MOD(0x42), 0x10}, //PDP must set to 1 in MHal_PNL_Init_LPLL()
407 W2BYTE(L_BK_LPLL(0x00), ((PANEL_LPLL_INPUT_DIV_2nd<<8) | PANEL_LPLL_INPUT_DIV_1st)); in MHal_PNL_Init_LPLL()
408 W2BYTE(L_BK_LPLL(0x01), ((PANEL_LPLL_LOOP_DIV_2nd<<8) | PANEL_LPLL_LOOP_DIV_1st)); in MHal_PNL_Init_LPLL()
409 W2BYTE(L_BK_LPLL(0x02), ((PANEL_LPLL_OUTPUT_DIV_2nd<<8) | PANEL_LPLL_OUTPUT_DIV_1st)); in MHal_PNL_Init_LPLL()
414 W2BYTE(L_BK_LPLL(0x03), DAC_LPLL_ICTRL);//DAC output: better value(ICTRL) for stable LPLL in MHal_PNL_Init_LPLL()
418 W2BYTE(L_BK_LPLL(0x03), LVDS_LPLL_ICTRL); in MHal_PNL_Init_LPLL()
421 W2BYTEMSK(L_BK_LPLL(0x03), 0, BIT(6)); in MHal_PNL_Init_LPLL()
423 W2BYTEMSK(L_BK_LPLL(0x03), (eLPLL_Mode << 7) , BIT(7)); in MHal_PNL_Init_LPLL()
903 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
907 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.c405 W2BYTE(L_BK_LPLL(0x42),0x1000); // {H_BK_MOD(0x42), 0x10}, //PDP must set to 1 in MHal_PNL_Init_LPLL()
407 W2BYTE(L_BK_LPLL(0x00), ((PANEL_LPLL_INPUT_DIV_2nd<<8) | PANEL_LPLL_INPUT_DIV_1st)); in MHal_PNL_Init_LPLL()
408 W2BYTE(L_BK_LPLL(0x01), ((PANEL_LPLL_LOOP_DIV_2nd<<8) | PANEL_LPLL_LOOP_DIV_1st)); in MHal_PNL_Init_LPLL()
409 W2BYTE(L_BK_LPLL(0x02), ((PANEL_LPLL_OUTPUT_DIV_2nd<<8) | PANEL_LPLL_OUTPUT_DIV_1st)); in MHal_PNL_Init_LPLL()
414 W2BYTE(L_BK_LPLL(0x03), DAC_LPLL_ICTRL);//DAC output: better value(ICTRL) for stable LPLL in MHal_PNL_Init_LPLL()
418 W2BYTE(L_BK_LPLL(0x03), LVDS_LPLL_ICTRL); in MHal_PNL_Init_LPLL()
421 W2BYTEMSK(L_BK_LPLL(0x03), 0, BIT(6)); in MHal_PNL_Init_LPLL()
423 W2BYTEMSK(L_BK_LPLL(0x03), (eLPLL_Mode << 7) , BIT(7)); in MHal_PNL_Init_LPLL()
903 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
907 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.c405 W2BYTE(L_BK_LPLL(0x42),0x1000); // {H_BK_MOD(0x42), 0x10}, //PDP must set to 1 in MHal_PNL_Init_LPLL()
407 W2BYTE(L_BK_LPLL(0x00), ((PANEL_LPLL_INPUT_DIV_2nd<<8) | PANEL_LPLL_INPUT_DIV_1st)); in MHal_PNL_Init_LPLL()
408 W2BYTE(L_BK_LPLL(0x01), ((PANEL_LPLL_LOOP_DIV_2nd<<8) | PANEL_LPLL_LOOP_DIV_1st)); in MHal_PNL_Init_LPLL()
409 W2BYTE(L_BK_LPLL(0x02), ((PANEL_LPLL_OUTPUT_DIV_2nd<<8) | PANEL_LPLL_OUTPUT_DIV_1st)); in MHal_PNL_Init_LPLL()
414 W2BYTE(L_BK_LPLL(0x03), DAC_LPLL_ICTRL);//DAC output: better value(ICTRL) for stable LPLL in MHal_PNL_Init_LPLL()
418 W2BYTE(L_BK_LPLL(0x03), LVDS_LPLL_ICTRL); in MHal_PNL_Init_LPLL()
421 W2BYTEMSK(L_BK_LPLL(0x03), 0, BIT(6)); in MHal_PNL_Init_LPLL()
423 W2BYTEMSK(L_BK_LPLL(0x03), (eLPLL_Mode << 7) , BIT(7)); in MHal_PNL_Init_LPLL()
903 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
907 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.c405 W2BYTE(L_BK_LPLL(0x42),0x1000); // {H_BK_MOD(0x42), 0x10}, //PDP must set to 1 in MHal_PNL_Init_LPLL()
407 W2BYTE(L_BK_LPLL(0x00), ((PANEL_LPLL_INPUT_DIV_2nd<<8) | PANEL_LPLL_INPUT_DIV_1st)); in MHal_PNL_Init_LPLL()
408 W2BYTE(L_BK_LPLL(0x01), ((PANEL_LPLL_LOOP_DIV_2nd<<8) | PANEL_LPLL_LOOP_DIV_1st)); in MHal_PNL_Init_LPLL()
409 W2BYTE(L_BK_LPLL(0x02), ((PANEL_LPLL_OUTPUT_DIV_2nd<<8) | PANEL_LPLL_OUTPUT_DIV_1st)); in MHal_PNL_Init_LPLL()
414 W2BYTE(L_BK_LPLL(0x03), DAC_LPLL_ICTRL);//DAC output: better value(ICTRL) for stable LPLL in MHal_PNL_Init_LPLL()
418 W2BYTE(L_BK_LPLL(0x03), LVDS_LPLL_ICTRL); in MHal_PNL_Init_LPLL()
421 W2BYTEMSK(L_BK_LPLL(0x03), 0, BIT(6)); in MHal_PNL_Init_LPLL()
423 W2BYTEMSK(L_BK_LPLL(0x03), (eLPLL_Mode << 7) , BIT(7)); in MHal_PNL_Init_LPLL()
903 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
907 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A DhalPNL.c769 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
770 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
774 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
775 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
776 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0 in MHal_PNL_FRC_lpll_src_sel()
1261 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
1285 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
2675 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
2679 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
3127 W4BYTE(L_BK_LPLL(0x48), (MS_U32)u64LdPllSet); in MHal_PNL_CalExtLPLLSETbyDClk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A DhalPNL.c815 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
816 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
819 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
820 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
821 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0 in MHal_PNL_FRC_lpll_src_sel()
1021 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
2343 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
2347 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
2748 u32PLL_SET = R4BYTE(L_BK_LPLL(0x48)); in MHal_PNL_SetOSDSSC()
2759 W2BYTE(L_BK_LPLL(0x4E), u16Step & 0x0FFF);// LPLL_STEP in MHal_PNL_SetOSDSSC()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A DhalPNL.c815 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
816 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
819 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
820 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
821 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0 in MHal_PNL_FRC_lpll_src_sel()
1021 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
2343 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
2347 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
2748 u32PLL_SET = R4BYTE(L_BK_LPLL(0x48)); in MHal_PNL_SetOSDSSC()
2759 W2BYTE(L_BK_LPLL(0x4E), u16Step & 0x0FFF);// LPLL_STEP in MHal_PNL_SetOSDSSC()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A DhalPNL.c924 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
925 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
929 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
930 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
931 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0 in MHal_PNL_FRC_lpll_src_sel()
1489 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
1513 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
3073 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
3077 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
3525 W4BYTE(L_BK_LPLL(0x48), (MS_U32)u64LdPllSet); in MHal_PNL_CalExtLPLLSETbyDClk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.c1030 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
1031 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
1035 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
1036 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
1037 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0 in MHal_PNL_FRC_lpll_src_sel()
1749 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
1773 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
3364 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
3368 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
3826 W4BYTE(L_BK_LPLL(0x48), (MS_U32)u64LdPllSet); in MHal_PNL_CalExtLPLLSETbyDClk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.c1031 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
1032 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
1036 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
1037 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
1038 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0 in MHal_PNL_FRC_lpll_src_sel()
1640 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
1664 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
3412 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
3416 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
3872 W4BYTE(L_BK_LPLL(0x48), (MS_U32)u64LdPllSet); in MHal_PNL_CalExtLPLLSETbyDClk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.c1031 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
1032 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
1036 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
1037 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
1038 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0 in MHal_PNL_FRC_lpll_src_sel()
1640 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
1664 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
3412 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
3416 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
3872 W4BYTE(L_BK_LPLL(0x48), (MS_U32)u64LdPllSet); in MHal_PNL_CalExtLPLLSETbyDClk()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.c1792 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
1793 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
1797 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
1798 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
1799 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0 in MHal_PNL_FRC_lpll_src_sel()
2391 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
2415 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
2443 W2BYTEMSK(L_BK_LPLL(0x3C),0x0000 ,BIT(12)); in MHal_PNL_Init_LPLL()
4327 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
4331 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.c1796 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
1797 W2BYTEMSK(L_BK_LPLL(0x7F), u8src?BIT(8):0, BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
1801 W2BYTEMSK(L_BK_LPLL(0x00), 0x01, 0x0F); in MHal_PNL_FRC_lpll_src_sel()
1802 W2BYTEMSK(L_BK_LPLL(0x7F), BIT(8), BIT(8)); in MHal_PNL_FRC_lpll_src_sel()
1803 W2BYTEMSK(L_BK_LPLL(0x00), 0x00, 0x0F); // restore to sub bnak 0 in MHal_PNL_FRC_lpll_src_sel()
2395 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
2419 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL_Ext[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
2447 W2BYTEMSK(L_BK_LPLL(0x3C),0x0000 ,BIT(12)); in MHal_PNL_Init_LPLL()
4354 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
4358 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_sc.c2542 MDrv_WriteByteMask(L_BK_LPLL(0x0C), BIT(3), BIT(3)); in HAL_SC_EnableFPLL()
2543 MDrv_WriteByteMask(L_BK_LPLL(0x0C), 0, BIT(6)); in HAL_SC_EnableFPLL()
2554 pFpllPhaseDiff->u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in _HAL_SC_GetFPLLPhaseDiffISR()
2555 …pFpllPhaseDiff->eFpllDir = (MDrv_Read2Byte(L_BK_LPLL(0x12)) & BIT(0)) == BIT(0) ? E_XC_FPLL_DIR_UP… in _HAL_SC_GetFPLLPhaseDiffISR()
2598 u16Value =(MS_U16)((u32XTAL_Clock * 100) / MDrv_Read4Byte(L_BK_LPLL(0x23))); in HAL_SC_GetOutputVFreqX100()
2766 MDrv_WriteByteMask(L_BK_LPLL(0x0D), 0x00, BIT(4)); // turn off 2 limit in HAL_SC_Set_FPLL_Limit()
2771 MDrv_Write3Byte(L_BK_LPLL(0x06), _U32LimitD5D6D7); in HAL_SC_Set_FPLL_Limit()
2772 MDrv_Write3Byte(L_BK_LPLL(0x08), _U32LimitD5D6D7); in HAL_SC_Set_FPLL_Limit()
2777 MDrv_WriteByteMask(L_BK_LPLL(0x0D), BIT(4), BIT(4)); // turn on 2 limit in HAL_SC_Set_FPLL_Limit()
2799 MDrv_Write3Byte(L_BK_LPLL(0x06), u32LpllLimitHigh); in HAL_SC_Set_FPLL_Limit()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_sc.c2562 MDrv_WriteByteMask(L_BK_LPLL(0x0C), BIT(3), BIT(3)); in HAL_SC_EnableFPLL()
2563 MDrv_WriteByteMask(L_BK_LPLL(0x0C), 0, BIT(6)); in HAL_SC_EnableFPLL()
2574 pFpllPhaseDiff->u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in _HAL_SC_GetFPLLPhaseDiffISR()
2575 …pFpllPhaseDiff->eFpllDir = (MDrv_Read2Byte(L_BK_LPLL(0x12)) & BIT(0)) == BIT(0) ? E_XC_FPLL_DIR_UP… in _HAL_SC_GetFPLLPhaseDiffISR()
2618 u16Value =(MS_U16)((u32XTAL_Clock * 100) / MDrv_Read4Byte(L_BK_LPLL(0x23))); in HAL_SC_GetOutputVFreqX100()
2786 MDrv_WriteByteMask(L_BK_LPLL(0x0D), 0x00, BIT(4)); // turn off 2 limit in HAL_SC_Set_FPLL_Limit()
2791 MDrv_Write3Byte(L_BK_LPLL(0x06), _U32LimitD5D6D7); in HAL_SC_Set_FPLL_Limit()
2792 MDrv_Write3Byte(L_BK_LPLL(0x08), _U32LimitD5D6D7); in HAL_SC_Set_FPLL_Limit()
2797 MDrv_WriteByteMask(L_BK_LPLL(0x0D), BIT(4), BIT(4)); // turn on 2 limit in HAL_SC_Set_FPLL_Limit()
2819 MDrv_Write3Byte(L_BK_LPLL(0x06), u32LpllLimitHigh); in HAL_SC_Set_FPLL_Limit()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_sc.c3236 MDrv_WriteByteMask(L_BK_LPLL(0x0C), BIT(3), BIT(3)); in HAL_SC_EnableFPLL()
3237 MDrv_WriteByteMask(L_BK_LPLL(0x0C), 0, BIT(6)); in HAL_SC_EnableFPLL()
3245 pFpllPhaseDiff->u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in _HAL_SC_GetFPLLPhaseDiffISR()
3246 …pFpllPhaseDiff->eFpllDir = (MDrv_Read2Byte(L_BK_LPLL(0x12)) & BIT(0)) == BIT(0) ? E_XC_FPLL_DIR_UP… in _HAL_SC_GetFPLLPhaseDiffISR()
3285 return ((MS_U16) ((u32XTAL_Clock * 100) / MDrv_Read4Byte(L_BK_LPLL(0x23)))); in HAL_SC_GetOutputVFreqX100()
3510 MDrv_WriteByteMask(L_BK_LPLL(0x0D), 0x00, BIT(4)); // turn off 2 limit in HAL_SC_Set_FPLL_Limit()
3513 MDrv_Write3Byte(L_BK_LPLL(0x06), _U32LimitD5D6D7); in HAL_SC_Set_FPLL_Limit()
3518 MDrv_WriteByteMask(L_BK_LPLL(0x0D), BIT(4), BIT(4)); // turn on 2 limit in HAL_SC_Set_FPLL_Limit()
3539 MDrv_Write3Byte(L_BK_LPLL(0x06), u32LpllLimitHigh); in HAL_SC_Set_FPLL_Limit()
3540 MDrv_Write3Byte(L_BK_LPLL(0x08), u32LpllLimitLow); in HAL_SC_Set_FPLL_Limit()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_sc.c3754 MDrv_WriteByteMask(L_BK_LPLL(0x0C), BIT(6)|BIT(3), BIT(6)|BIT(3)); in HAL_SC_EnableFPLL()
3775 u16PhaseLimit = MDrv_Read2Byte(L_BK_LPLL(0x0A)); in HAL_SC_WaitFPLLDone()
3781 u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in HAL_SC_WaitFPLLDone()
3785 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x21)), in HAL_SC_WaitFPLLDone()
3786 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x28)) in HAL_SC_WaitFPLLDone()
3799 MDrv_WriteRegBit(L_BK_LPLL(0x0C), 0, BIT(6)); //enable i_gain for lock phase in HAL_SC_WaitFPLLDone()
3805 u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in HAL_SC_WaitFPLLDone()
3809 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x21)), in HAL_SC_WaitFPLLDone()
3810 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x28)) in HAL_SC_WaitFPLLDone()
3831 pFpllPhaseDiff->u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in _HAL_SC_GetFPLLPhaseDiffISR()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_sc.c3667 MDrv_WriteByteMask(L_BK_LPLL(0x0C), BIT(6)|BIT(3), BIT(6)|BIT(3)); in HAL_SC_EnableFPLL()
3688 u16PhaseLimit = MDrv_Read2Byte(L_BK_LPLL(0x0A)); in HAL_SC_WaitFPLLDone()
3694 u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in HAL_SC_WaitFPLLDone()
3698 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x21)), in HAL_SC_WaitFPLLDone()
3699 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x28)) in HAL_SC_WaitFPLLDone()
3712 MDrv_WriteRegBit(L_BK_LPLL(0x0C), 0, BIT(6)); //enable i_gain for lock phase in HAL_SC_WaitFPLLDone()
3718 u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in HAL_SC_WaitFPLLDone()
3722 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x21)), in HAL_SC_WaitFPLLDone()
3723 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x28)) in HAL_SC_WaitFPLLDone()
3744 pFpllPhaseDiff->u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in _HAL_SC_GetFPLLPhaseDiffISR()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_sc.c3785 MDrv_WriteByteMask(L_BK_LPLL(0x0C), BIT(6)|BIT(3), BIT(6)|BIT(3)); in HAL_SC_EnableFPLL()
3806 u16PhaseLimit = MDrv_Read2Byte(L_BK_LPLL(0x0A)); in HAL_SC_WaitFPLLDone()
3812 u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in HAL_SC_WaitFPLLDone()
3816 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x21)), in HAL_SC_WaitFPLLDone()
3817 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x28)) in HAL_SC_WaitFPLLDone()
3830 MDrv_WriteRegBit(L_BK_LPLL(0x0C), 0, BIT(6)); //enable i_gain for lock phase in HAL_SC_WaitFPLLDone()
3836 u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in HAL_SC_WaitFPLLDone()
3840 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x21)), in HAL_SC_WaitFPLLDone()
3841 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x28)) in HAL_SC_WaitFPLLDone()
3862 pFpllPhaseDiff->u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in _HAL_SC_GetFPLLPhaseDiffISR()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_sc.c3985 MDrv_WriteByteMask(L_BK_LPLL(0x0C), BIT(6)|BIT(3), BIT(6)|BIT(3)); in HAL_SC_EnableFPLL()
4006 u16PhaseLimit = MDrv_Read2Byte(L_BK_LPLL(0x0A)); in HAL_SC_WaitFPLLDone()
4012 u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in HAL_SC_WaitFPLLDone()
4016 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x21)), in HAL_SC_WaitFPLLDone()
4017 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x28)) in HAL_SC_WaitFPLLDone()
4030 MDrv_WriteRegBit(L_BK_LPLL(0x0C), 0, BIT(6)); //enable i_gain for lock phase in HAL_SC_WaitFPLLDone()
4036 u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in HAL_SC_WaitFPLLDone()
4040 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x21)), in HAL_SC_WaitFPLLDone()
4041 (unsigned int)MDrv_Read4Byte(L_BK_LPLL(0x28)) in HAL_SC_WaitFPLLDone()
4062 pFpllPhaseDiff->u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11)); in _HAL_SC_GetFPLLPhaseDiffISR()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.c730 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
747 W2BYTEMSK(L_BK_LPLL(0x6D), 0x84, 0xFF); in MHal_PNL_Init_LPLL()
1791 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
1795 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.c730 W2BYTEMSK(L_BK_LPLL(LPLLSettingTBL[LPLLTblIndex][indexCounter].address), in _MHal_PNL_DumpLPLLTable()
747 W2BYTEMSK(L_BK_LPLL(0x6D), 0x84, 0xFF); in MHal_PNL_Init_LPLL()
1791 W2BYTEMSK(L_BK_LPLL(0x03), BIT(5), BIT(5)); in MHal_PNL_PowerDownLPLL()
1795 W2BYTEMSK(L_BK_LPLL(0x03), FALSE, BIT(5)); in MHal_PNL_PowerDownLPLL()

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