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Searched refs:E_FIQEXPL_START (Results 1 – 25 of 58) sorted by relevance

123

/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DhalIRQTBL.h260 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
261 E_FIQ_32 = E_FIQEXPL_START + 0,
262 E_FIQ_33 = E_FIQEXPL_START + 1,
263 E_FIQ_34 = E_FIQEXPL_START + 2,
264 E_FIQ_35 = E_FIQEXPL_START + 3,
265 E_FIQ_36 = E_FIQEXPL_START + 4,
266 E_FIQ_37 = E_FIQEXPL_START + 5,
267 E_FIQ_38 = E_FIQEXPL_START + 6,
268 E_FIQ_39 = E_FIQEXPL_START + 7,
269 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
H A DregCHIP.h189 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START))
190 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START))
191 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START))
193 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_36 - E_FIQEXPL_START))
194 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_37 - E_FIQEXPL_START))
195 #define FIQEXPL_8051_TO_MIPS_VPE0 (0x01 << (E_FIQ_38 - E_FIQEXPL_START))
196 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START))
197 #define FIQEXPL_MIPS_VPE0_TO_AEON (0x01 << (E_FIQ_40 - E_FIQEXPL_START))
198 #define FIQEXPL_MIPS_VPE0_TO_MIPS_VPE1 (0x01 << (E_FIQ_41 - E_FIQEXPL_START))
199 #define FIQEXPL_MIPS_VPE0_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START))
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DhalIRQTBL.h294 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
295 E_FIQ_32 = E_FIQEXPL_START + 0,
296 E_FIQ_33 = E_FIQEXPL_START + 1,
297 E_FIQ_34 = E_FIQEXPL_START + 2,
298 E_FIQ_35 = E_FIQEXPL_START + 3,
299 E_FIQ_36 = E_FIQEXPL_START + 4,
300 E_FIQ_37 = E_FIQEXPL_START + 5,
301 E_FIQ_38 = E_FIQEXPL_START + 6,
302 E_FIQ_39 = E_FIQEXPL_START + 7,
303 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
H A DregCHIP.h189 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START))
190 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START))
191 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START))
193 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_36 - E_FIQEXPL_START))
194 #define FIQEXPL_8051_TO_BEON (0x01 << (E_FIQ_37 - E_FIQEXPL_START))
195 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_38 - E_FIQEXPL_START))
196 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START))
197 #define FIQEXPL_AEON_TO_MIPS_VPE1 (0x01 << (E_FIQ_40 - E_FIQEXPL_START))
198 #define FIQEXPL_AEON_TO_BEON (0x01 << (E_FIQ_41 - E_FIQEXPL_START))
199 #define FIQEXPL_AEON_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START))
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DhalIRQTBL.h294 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
295 E_FIQ_32 = E_FIQEXPL_START + 0,
296 E_FIQ_33 = E_FIQEXPL_START + 1,
297 E_FIQ_34 = E_FIQEXPL_START + 2,
298 E_FIQ_35 = E_FIQEXPL_START + 3,
299 E_FIQ_36 = E_FIQEXPL_START + 4,
300 E_FIQ_37 = E_FIQEXPL_START + 5,
301 E_FIQ_38 = E_FIQEXPL_START + 6,
302 E_FIQ_39 = E_FIQEXPL_START + 7,
303 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
H A DregCHIP.h189 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START))
190 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START))
191 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START))
193 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_36 - E_FIQEXPL_START))
194 #define FIQEXPL_8051_TO_BEON (0x01 << (E_FIQ_37 - E_FIQEXPL_START))
195 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_38 - E_FIQEXPL_START))
196 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START))
197 #define FIQEXPL_AEON_TO_MIPS_VPE1 (0x01 << (E_FIQ_40 - E_FIQEXPL_START))
198 #define FIQEXPL_AEON_TO_BEON (0x01 << (E_FIQ_41 - E_FIQEXPL_START))
199 #define FIQEXPL_AEON_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START))
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DregCHIP.h237 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START))
238 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START))
239 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START))
241 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_36 - E_FIQEXPL_START))
242 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_37 - E_FIQEXPL_START))
243 #define FIQEXPL_8051_TO_MIPS_VPE0 (0x01 << (E_FIQ_38 - E_FIQEXPL_START))
244 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START))
245 #define FIQEXPL_MIPS_VPE0_TO_AEON (0x01 << (E_FIQ_40 - E_FIQEXPL_START))
246 #define FIQEXPL_MIPS_VPE0_TO_MIPS_VPE1 (0x01 << (E_FIQ_41 - E_FIQEXPL_START))
247 #define FIQEXPL_MIPS_VPE0_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START))
[all …]
H A DhalIRQTBL.h323 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
324 E_FIQ_32 = E_FIQEXPL_START + 0,
325 E_FIQ_33 = E_FIQEXPL_START + 1,
326 E_FIQ_34 = E_FIQEXPL_START + 2,
327 E_FIQ_35 = E_FIQEXPL_START + 3,
328 E_FIQ_36 = E_FIQEXPL_START + 4,
329 E_FIQ_37 = E_FIQEXPL_START + 5,
330 E_FIQ_38 = E_FIQEXPL_START + 6,
331 E_FIQ_39 = E_FIQEXPL_START + 7,
332 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DregCHIP.h237 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START))
238 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START))
239 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START))
241 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_36 - E_FIQEXPL_START))
242 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_37 - E_FIQEXPL_START))
243 #define FIQEXPL_8051_TO_MIPS_VPE0 (0x01 << (E_FIQ_38 - E_FIQEXPL_START))
244 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START))
245 #define FIQEXPL_MIPS_VPE0_TO_AEON (0x01 << (E_FIQ_40 - E_FIQEXPL_START))
246 #define FIQEXPL_MIPS_VPE0_TO_MIPS_VPE1 (0x01 << (E_FIQ_41 - E_FIQEXPL_START))
247 #define FIQEXPL_MIPS_VPE0_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START))
[all …]
H A DhalIRQTBL.h323 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
324 E_FIQ_32 = E_FIQEXPL_START + 0,
325 E_FIQ_33 = E_FIQEXPL_START + 1,
326 E_FIQ_34 = E_FIQEXPL_START + 2,
327 E_FIQ_35 = E_FIQEXPL_START + 3,
328 E_FIQ_36 = E_FIQEXPL_START + 4,
329 E_FIQ_37 = E_FIQEXPL_START + 5,
330 E_FIQ_38 = E_FIQEXPL_START + 6,
331 E_FIQ_39 = E_FIQEXPL_START + 7,
332 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DregCHIP.h237 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START))
238 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START))
239 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START))
241 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_36 - E_FIQEXPL_START))
242 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_37 - E_FIQEXPL_START))
243 #define FIQEXPL_8051_TO_MIPS_VPE0 (0x01 << (E_FIQ_38 - E_FIQEXPL_START))
244 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START))
245 #define FIQEXPL_MIPS_VPE0_TO_AEON (0x01 << (E_FIQ_40 - E_FIQEXPL_START))
246 #define FIQEXPL_MIPS_VPE0_TO_MIPS_VPE1 (0x01 << (E_FIQ_41 - E_FIQEXPL_START))
247 #define FIQEXPL_MIPS_VPE0_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START))
[all …]
H A DhalIRQTBL.h323 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
324 E_FIQ_32 = E_FIQEXPL_START + 0,
325 E_FIQ_33 = E_FIQEXPL_START + 1,
326 E_FIQ_34 = E_FIQEXPL_START + 2,
327 E_FIQ_35 = E_FIQEXPL_START + 3,
328 E_FIQ_36 = E_FIQEXPL_START + 4,
329 E_FIQ_37 = E_FIQEXPL_START + 5,
330 E_FIQ_38 = E_FIQEXPL_START + 6,
331 E_FIQ_39 = E_FIQEXPL_START + 7,
332 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DregCHIP.h237 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START))
238 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START))
239 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START))
241 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_36 - E_FIQEXPL_START))
242 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_37 - E_FIQEXPL_START))
243 #define FIQEXPL_8051_TO_MIPS_VPE0 (0x01 << (E_FIQ_38 - E_FIQEXPL_START))
244 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START))
245 #define FIQEXPL_MIPS_VPE0_TO_AEON (0x01 << (E_FIQ_40 - E_FIQEXPL_START))
246 #define FIQEXPL_MIPS_VPE0_TO_MIPS_VPE1 (0x01 << (E_FIQ_41 - E_FIQEXPL_START))
247 #define FIQEXPL_MIPS_VPE0_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START))
[all …]
H A DhalIRQTBL.h323 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
324 E_FIQ_32 = E_FIQEXPL_START + 0,
325 E_FIQ_33 = E_FIQEXPL_START + 1,
326 E_FIQ_34 = E_FIQEXPL_START + 2,
327 E_FIQ_35 = E_FIQEXPL_START + 3,
328 E_FIQ_36 = E_FIQEXPL_START + 4,
329 E_FIQ_37 = E_FIQEXPL_START + 5,
330 E_FIQ_38 = E_FIQEXPL_START + 6,
331 E_FIQ_39 = E_FIQEXPL_START + 7,
332 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DregCHIP.h237 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START))
238 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START))
239 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START))
241 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_36 - E_FIQEXPL_START))
242 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_37 - E_FIQEXPL_START))
243 #define FIQEXPL_8051_TO_MIPS_VPE0 (0x01 << (E_FIQ_38 - E_FIQEXPL_START))
244 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START))
245 #define FIQEXPL_MIPS_VPE0_TO_AEON (0x01 << (E_FIQ_40 - E_FIQEXPL_START))
246 #define FIQEXPL_MIPS_VPE0_TO_MIPS_VPE1 (0x01 << (E_FIQ_41 - E_FIQEXPL_START))
247 #define FIQEXPL_MIPS_VPE0_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START))
[all …]
H A DhalIRQTBL.h323 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
324 E_FIQ_32 = E_FIQEXPL_START + 0,
325 E_FIQ_33 = E_FIQEXPL_START + 1,
326 E_FIQ_34 = E_FIQEXPL_START + 2,
327 E_FIQ_35 = E_FIQEXPL_START + 3,
328 E_FIQ_36 = E_FIQEXPL_START + 4,
329 E_FIQ_37 = E_FIQEXPL_START + 5,
330 E_FIQ_38 = E_FIQEXPL_START + 6,
331 E_FIQ_39 = E_FIQEXPL_START + 7,
332 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DhalIRQTBL.h304 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
305 E_FIQ_32 = E_FIQEXPL_START + 0,
306 E_FIQ_33 = E_FIQEXPL_START + 1,
307 E_FIQ_34 = E_FIQEXPL_START + 2,
308 E_FIQ_35 = E_FIQEXPL_START + 3,
309 E_FIQ_36 = E_FIQEXPL_START + 4,
310 E_FIQ_37 = E_FIQEXPL_START + 5,
311 E_FIQ_38 = E_FIQEXPL_START + 6,
312 E_FIQ_39 = E_FIQEXPL_START + 7,
313 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
H A DregCHIP.h297 …QEXPL_IR_INT_RC (0x1 << (E_FIQEXPL_IR_INT_RC - E_FIQEXPL_START) )
298 …QEXPL_AU_DMA_BUF_INT (0x1 << (E_FIQEXPL_AU_DMA_BUF_INT - E_FIQEXPL_START) )
299 …QEXPL_IR_IN (0x1 << (E_FIQEXPL_IR_IN - E_FIQEXPL_START) )
300 …QEXPL_8051_TO_MIPS_VPE0 (0x1 << (E_FIQEXPL_8051_TO_MIPS_VPE0 - E_FIQEXPL_START) )
301 …QEXPL_EXT_GPIO_INT0 (0x1 << (E_FIQEXPL_EXT_GPIO_INT0 - E_FIQEXPL_START) )
302 …QEXPL_MIPS_VPE0_TO_8051 (0x1 << (E_FIQEXPL_MIPS_VPE1_TO_8051 - E_FIQEXPL_START) )
303 …QEXPL_EXT_GPIO_INT1 (0x1 << (E_FIQEXPL_EXT_GPIO_INT1 - E_FIQEXPL_START) )
304 …QEXPL_EXT_GPIO_INT2 (0x1 << (E_FIQEXPL_EXT_GPIO_INT2 - E_FIQEXPL_START) )
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DhalIRQTBL.h304 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
305 E_FIQ_32 = E_FIQEXPL_START + 0,
306 E_FIQ_33 = E_FIQEXPL_START + 1,
307 E_FIQ_34 = E_FIQEXPL_START + 2,
308 E_FIQ_35 = E_FIQEXPL_START + 3,
309 E_FIQ_36 = E_FIQEXPL_START + 4,
310 E_FIQ_37 = E_FIQEXPL_START + 5,
311 E_FIQ_38 = E_FIQEXPL_START + 6,
312 E_FIQ_39 = E_FIQEXPL_START + 7,
313 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DhalIRQTBL.h304 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
305 E_FIQ_32 = E_FIQEXPL_START + 0,
306 E_FIQ_33 = E_FIQEXPL_START + 1,
307 E_FIQ_34 = E_FIQEXPL_START + 2,
308 E_FIQ_35 = E_FIQEXPL_START + 3,
309 E_FIQ_36 = E_FIQEXPL_START + 4,
310 E_FIQ_37 = E_FIQEXPL_START + 5,
311 E_FIQ_38 = E_FIQEXPL_START + 6,
312 E_FIQ_39 = E_FIQEXPL_START + 7,
313 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
H A DregCHIP.h297 …QEXPL_IR_INT_RC (0x1 << (E_FIQEXPL_IR_INT_RC - E_FIQEXPL_START) )
298 …QEXPL_AU_DMA_BUF_INT (0x1 << (E_FIQEXPL_AU_DMA_BUF_INT - E_FIQEXPL_START) )
299 …QEXPL_IR_IN (0x1 << (E_FIQEXPL_IR_IN - E_FIQEXPL_START) )
300 …QEXPL_8051_TO_MIPS_VPE0 (0x1 << (E_FIQEXPL_8051_TO_MIPS_VPE0 - E_FIQEXPL_START) )
301 …QEXPL_EXT_GPIO_INT0 (0x1 << (E_FIQEXPL_EXT_GPIO_INT0 - E_FIQEXPL_START) )
302 …QEXPL_MIPS_VPE0_TO_8051 (0x1 << (E_FIQEXPL_MIPS_VPE1_TO_8051 - E_FIQEXPL_START) )
303 …QEXPL_EXT_GPIO_INT1 (0x1 << (E_FIQEXPL_EXT_GPIO_INT1 - E_FIQEXPL_START) )
304 …QEXPL_EXT_GPIO_INT2 (0x1 << (E_FIQEXPL_EXT_GPIO_INT2 - E_FIQEXPL_START) )
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DhalIRQTBL.h304 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
305 E_FIQ_32 = E_FIQEXPL_START + 0,
306 E_FIQ_33 = E_FIQEXPL_START + 1,
307 E_FIQ_34 = E_FIQEXPL_START + 2,
308 E_FIQ_35 = E_FIQEXPL_START + 3,
309 E_FIQ_36 = E_FIQEXPL_START + 4,
310 E_FIQ_37 = E_FIQEXPL_START + 5,
311 E_FIQ_38 = E_FIQEXPL_START + 6,
312 E_FIQ_39 = E_FIQEXPL_START + 7,
313 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DhalIRQTBL.h311 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
312 E_FIQ_32 = E_FIQEXPL_START + 0,
313 E_FIQ_33 = E_FIQEXPL_START + 1,
314 E_FIQ_34 = E_FIQEXPL_START + 2,
315 E_FIQ_35 = E_FIQEXPL_START + 3,
316 E_FIQ_36 = E_FIQEXPL_START + 4,
317 E_FIQ_37 = E_FIQEXPL_START + 5,
318 E_FIQ_38 = E_FIQEXPL_START + 6,
319 E_FIQ_39 = E_FIQEXPL_START + 7,
320 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DhalIRQTBL.h311 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS, enumerator
312 E_FIQ_32 = E_FIQEXPL_START + 0,
313 E_FIQ_33 = E_FIQEXPL_START + 1,
314 E_FIQ_34 = E_FIQEXPL_START + 2,
315 E_FIQ_35 = E_FIQEXPL_START + 3,
316 E_FIQ_36 = E_FIQEXPL_START + 4,
317 E_FIQ_37 = E_FIQEXPL_START + 5,
318 E_FIQ_38 = E_FIQEXPL_START + 6,
319 E_FIQ_39 = E_FIQEXPL_START + 7,
320 E_FIQ_40 = E_FIQEXPL_START + 8,
[all …]
H A DregCHIP.h303 …QEXPL_IR_INT_RC (0x1 << (E_FIQEXPL_IR_INT_RC - E_FIQEXPL_START) )
304 …QEXPL_AU_DMA_BUF_INT (0x1 << (E_FIQEXPL_AU_DMA_BUF_INT - E_FIQEXPL_START) )
305 …QEXPL_IR_IN (0x1 << (E_FIQEXPL_IR_IN - E_FIQEXPL_START) )
306 …QEXPL_8051_TO_MIPS_VPE0 (0x1 << (E_FIQEXPL_8051_TO_MIPS_VPE0 - E_FIQEXPL_START) )
307 …QEXPL_EXT_GPIO_INT0 (0x1 << (E_FIQEXPL_EXT_GPIO_INT0 - E_FIQEXPL_START) )
308 …QEXPL_MIPS_VPE0_TO_8051 (0x1 << (E_FIQEXPL_MIPS_VPE1_TO_8051 - E_FIQEXPL_START) )
309 …QEXPL_EXT_GPIO_INT1 (0x1 << (E_FIQEXPL_EXT_GPIO_INT1 - E_FIQEXPL_START) )
310 …QEXPL_EXT_GPIO_INT2 (0x1 << (E_FIQEXPL_EXT_GPIO_INT2 - E_FIQEXPL_START) )

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