1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
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28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
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31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
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41 // consequential damages, including without limitation, lost of profit or
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43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
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50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
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53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
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61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78
79 #ifndef _HAL_IRQTBL_H_
80 #define _HAL_IRQTBL_H_
81
82 #ifdef __cplusplus
83 extern "C"
84 {
85 #endif
86
87 #define E_INT_RESERVED E_INT_IRQ_FIQ_NONE
88
89 #if defined(MSOS_TYPE_LINUX)
90 #ifdef CHIP_INT_SPI_MODE
91 #define CONFIG_IRQL_BASE_ADDRESS 0x00
92 #define CONFIG_IRQH_BASE_ADDRESS 0x10
93 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x20
94 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x30
95 #define CONFIG_FIQL_BASE_ADDRESS 0x40
96 #define CONFIG_FIQH_BASE_ADDRESS 0x50
97 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
98 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
99 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
100 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
101 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xA0
102 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xB0
103 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xC0
104 #define CONFIG_FIQHYPH_BASE_ADDRESS 0xD0
105 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xE0
106 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xF0
107 #else
108 #define CONFIG_FIQL_BASE_ADDRESS 0x00
109 #define CONFIG_FIQH_BASE_ADDRESS 0x10
110 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x20
111 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x30
112 #define CONFIG_IRQL_BASE_ADDRESS 0x40
113 #define CONFIG_IRQH_BASE_ADDRESS 0x50
114 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x60
115 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x70
116 #define CONFIG_FIQHYPL_BASE_ADDRESS 0x80
117 #define CONFIG_FIQHYPH_BASE_ADDRESS 0x90
118 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xA0
119 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xB0
120 #define CONFIG_IRQHYPL_BASE_ADDRESS 0xC0
121 #define CONFIG_IRQHYPH_BASE_ADDRESS 0xD0
122 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xE0
123 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xF0
124 #endif
125
126 #elif defined(MSOS_TYPE_NOS) || defined(MSOS_TYPE_UCOS)
127 #define CONFIG_IRQL_BASE_ADDRESS 0x00
128 #define CONFIG_IRQH_BASE_ADDRESS 0x10
129 #define CONFIG_FIQL_BASE_ADDRESS 0x20
130 #define CONFIG_FIQH_BASE_ADDRESS 0x30
131 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x40
132 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x50
133 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
134 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
135 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
136 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
137 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xA0
138 #define CONFIG_FIQHYPH_BASE_ADDRESS 0xB0
139 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xC0
140 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xD0
141 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xE0
142 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xF0
143
144 #elif defined(MSOS_TYPE_ECOS)
145 #define CONFIG_FIQL_BASE_ADDRESS 0x00
146 #define CONFIG_FIQH_BASE_ADDRESS 0x10
147 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x20
148 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x30
149 #define CONFIG_IRQL_BASE_ADDRESS 0x40
150 #define CONFIG_IRQH_BASE_ADDRESS 0x50
151 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x60
152 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x70
153 #define CONFIG_FIQHYPL_BASE_ADDRESS 0x80
154 #define CONFIG_FIQHYPH_BASE_ADDRESS 0x90
155 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xA0
156 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xB0
157 #define CONFIG_IRQHYPL_BASE_ADDRESS 0xC0
158 #define CONFIG_IRQHYPH_BASE_ADDRESS 0xD0
159 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xE0
160 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xF0
161
162
163 #elif defined(MSOS_TYPE_NUTTX)
164 #define CONFIG_IRQL_BASE_ADDRESS 0x00
165 #define CONFIG_IRQH_BASE_ADDRESS 0x10
166 #define CONFIG_FIQL_BASE_ADDRESS 0x20
167 #define CONFIG_FIQH_BASE_ADDRESS 0x30
168 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x40
169 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x50
170 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
171 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
172 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
173 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
174 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xA0
175 #define CONFIG_FIQHYPH_BASE_ADDRESS 0xB0
176 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xC0
177 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xD0
178 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xE0
179 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xF0
180
181 #elif defined(MSOS_TYPE_LINUX_KERNEL)
182 // Interrupt Base definition needed to macth Kernel define ./arch/arm/arm-boards/napoli/chip_int.h
183 #define MSTAR_INT_BASE 0x80 //PPI mode
184
185 #define CONFIG_IRQL_BASE_ADDRESS 0x40
186 #define CONFIG_IRQH_BASE_ADDRESS 0x50
187 #define CONFIG_FIQL_BASE_ADDRESS 0x00
188 #define CONFIG_FIQH_BASE_ADDRESS 0x10
189 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x60
190 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x70
191 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x20
192 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x30
193
194 #define CONFIG_IRQHYPL_BASE_ADDRESS 0xC0
195 #define CONFIG_IRQHYPH_BASE_ADDRESS 0xD0
196 #define CONFIG_FIQHYPL_BASE_ADDRESS 0x80
197 #define CONFIG_FIQHYPH_BASE_ADDRESS 0x90
198 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xE0
199 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xF0
200 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xA0
201 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xB0
202
203 #else
204 #error "Unknown Platform Selection"
205 #endif
206
207 typedef enum
208 {
209 E_IRQL_START = CONFIG_IRQL_BASE_ADDRESS,
210 E_IRQ_00 = E_IRQL_START + 0,
211 E_IRQ_01 = E_IRQL_START + 1,
212 E_IRQ_02 = E_IRQL_START + 2,
213 E_IRQ_03 = E_IRQL_START + 3,
214 E_IRQ_04 = E_IRQL_START + 4,
215 E_IRQ_05 = E_IRQL_START + 5,
216 E_IRQ_06 = E_IRQL_START + 6,
217 E_IRQ_07 = E_IRQL_START + 7,
218 E_IRQ_08 = E_IRQL_START + 8,
219 E_IRQ_09 = E_IRQL_START + 9,
220 E_IRQ_10 = E_IRQL_START + 10,
221 E_IRQ_11 = E_IRQL_START + 11,
222 E_IRQ_12 = E_IRQL_START + 12,
223 E_IRQ_13 = E_IRQL_START + 13,
224 E_IRQ_14 = E_IRQL_START + 14,
225 E_IRQ_15 = E_IRQL_START + 15,
226 E_IRQL_END = E_IRQL_START + 15,
227
228 E_IRQH_START = CONFIG_IRQH_BASE_ADDRESS,
229 E_IRQ_16 = E_IRQH_START + 0,
230 E_IRQ_17 = E_IRQH_START + 1,
231 E_IRQ_18 = E_IRQH_START + 2,
232 E_IRQ_19 = E_IRQH_START + 3,
233 E_IRQ_20 = E_IRQH_START + 4,
234 E_IRQ_21 = E_IRQH_START + 5,
235 E_IRQ_22 = E_IRQH_START + 6,
236 E_IRQ_23 = E_IRQH_START + 7,
237 E_IRQ_24 = E_IRQH_START + 8,
238 E_IRQ_25 = E_IRQH_START + 9,
239 E_IRQ_26 = E_IRQH_START + 10,
240 E_IRQ_27 = E_IRQH_START + 11,
241 E_IRQ_28 = E_IRQH_START + 12,
242 E_IRQ_29 = E_IRQH_START + 13,
243 E_IRQ_30 = E_IRQH_START + 14,
244 E_IRQ_31 = E_IRQH_START + 15,
245 E_IRQH_END = E_IRQH_START + 15,
246
247 E_FIQL_START = CONFIG_FIQL_BASE_ADDRESS,
248 E_FIQ_00 = E_FIQL_START + 0,
249 E_FIQ_01 = E_FIQL_START + 1,
250 E_FIQ_02 = E_FIQL_START + 2,
251 E_FIQ_03 = E_FIQL_START + 3,
252 E_FIQ_04 = E_FIQL_START + 4,
253 E_FIQ_05 = E_FIQL_START + 5,
254 E_FIQ_06 = E_FIQL_START + 6,
255 E_FIQ_07 = E_FIQL_START + 7,
256 E_FIQ_08 = E_FIQL_START + 8,
257 E_FIQ_09 = E_FIQL_START + 9,
258 E_FIQ_10 = E_FIQL_START + 10,
259 E_FIQ_11 = E_FIQL_START + 11,
260 E_FIQ_12 = E_FIQL_START + 12,
261 E_FIQ_13 = E_FIQL_START + 13,
262 E_FIQ_14 = E_FIQL_START + 14,
263 E_FIQ_15 = E_FIQL_START + 15,
264 E_FIQL_END = E_FIQL_START + 15,
265
266 E_FIQH_START = CONFIG_FIQH_BASE_ADDRESS,
267 E_FIQ_16 = E_FIQH_START + 0,
268 E_FIQ_17 = E_FIQH_START + 1,
269 E_FIQ_18 = E_FIQH_START + 2,
270 E_FIQ_19 = E_FIQH_START + 3,
271 E_FIQ_20 = E_FIQH_START + 4,
272 E_FIQ_21 = E_FIQH_START + 5,
273 E_FIQ_22 = E_FIQH_START + 6,
274 E_FIQ_23 = E_FIQH_START + 7,
275 E_FIQ_24 = E_FIQH_START + 8,
276 E_FIQ_25 = E_FIQH_START + 9,
277 E_FIQ_26 = E_FIQH_START + 10,
278 E_FIQ_27 = E_FIQH_START + 11,
279 E_FIQ_28 = E_FIQH_START + 12,
280 E_FIQ_29 = E_FIQH_START + 13,
281 E_FIQ_30 = E_FIQH_START + 14,
282 E_FIQ_31 = E_FIQH_START + 15,
283 E_FIQH_END = E_FIQH_START + 15,
284
285 E_IRQEXPL_START = CONFIG_IRQEXPL_BASE_ADDRESS,
286 E_IRQ_32 = E_IRQEXPL_START + 0,
287 E_IRQ_33 = E_IRQEXPL_START + 1,
288 E_IRQ_34 = E_IRQEXPL_START + 2,
289 E_IRQ_35 = E_IRQEXPL_START + 3,
290 E_IRQ_36 = E_IRQEXPL_START + 4,
291 E_IRQ_37 = E_IRQEXPL_START + 5,
292 E_IRQ_38 = E_IRQEXPL_START + 6,
293 E_IRQ_39 = E_IRQEXPL_START + 7,
294 E_IRQ_40 = E_IRQEXPL_START + 8,
295 E_IRQ_41 = E_IRQEXPL_START + 9,
296 E_IRQ_42 = E_IRQEXPL_START + 10,
297 E_IRQ_43 = E_IRQEXPL_START + 11,
298 E_IRQ_44 = E_IRQEXPL_START + 12,
299 E_IRQ_45 = E_IRQEXPL_START + 13,
300 E_IRQ_46 = E_IRQEXPL_START + 14,
301 E_IRQ_47 = E_IRQEXPL_START + 15,
302 E_IRQEXPL_END = E_IRQEXPL_START + 15,
303
304 E_IRQEXPH_START = CONFIG_IRQEXPH_BASE_ADDRESS,
305 E_IRQ_48 = E_IRQEXPH_START + 0,
306 E_IRQ_49 = E_IRQEXPH_START + 1,
307 E_IRQ_50 = E_IRQEXPH_START + 2,
308 E_IRQ_51 = E_IRQEXPH_START + 3,
309 E_IRQ_52 = E_IRQEXPH_START + 4,
310 E_IRQ_53 = E_IRQEXPH_START + 5,
311 E_IRQ_54 = E_IRQEXPH_START + 6,
312 E_IRQ_55 = E_IRQEXPH_START + 7,
313 E_IRQ_56 = E_IRQEXPH_START + 8,
314 E_IRQ_57 = E_IRQEXPH_START + 9,
315 E_IRQ_58 = E_IRQEXPH_START + 10,
316 E_IRQ_59 = E_IRQEXPH_START + 11,
317 E_IRQ_60 = E_IRQEXPH_START + 12,
318 E_IRQ_61 = E_IRQEXPH_START + 13,
319 E_IRQ_62 = E_IRQEXPH_START + 14,
320 E_IRQ_63 = E_IRQEXPH_START + 15,
321 E_IRQEXPH_END = E_IRQEXPH_START + 15,
322
323 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS,
324 E_FIQ_32 = E_FIQEXPL_START + 0,
325 E_FIQ_33 = E_FIQEXPL_START + 1,
326 E_FIQ_34 = E_FIQEXPL_START + 2,
327 E_FIQ_35 = E_FIQEXPL_START + 3,
328 E_FIQ_36 = E_FIQEXPL_START + 4,
329 E_FIQ_37 = E_FIQEXPL_START + 5,
330 E_FIQ_38 = E_FIQEXPL_START + 6,
331 E_FIQ_39 = E_FIQEXPL_START + 7,
332 E_FIQ_40 = E_FIQEXPL_START + 8,
333 E_FIQ_41 = E_FIQEXPL_START + 9,
334 E_FIQ_42 = E_FIQEXPL_START + 10,
335 E_FIQ_43 = E_FIQEXPL_START + 11,
336 E_FIQ_44 = E_FIQEXPL_START + 12,
337 E_FIQ_45 = E_FIQEXPL_START + 13,
338 E_FIQ_46 = E_FIQEXPL_START + 14,
339 E_FIQ_47 = E_FIQEXPL_START + 15,
340 E_FIQEXPL_END = E_FIQEXPL_START + 15,
341
342 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS,
343 E_FIQ_48 = E_FIQEXPH_START + 0,
344 E_FIQ_49 = E_FIQEXPH_START + 1,
345 E_FIQ_50 = E_FIQEXPH_START + 2,
346 E_FIQ_51 = E_FIQEXPH_START + 3,
347 E_FIQ_52 = E_FIQEXPH_START + 4,
348 E_FIQ_53 = E_FIQEXPH_START + 5,
349 E_FIQ_54 = E_FIQEXPH_START + 6,
350 E_FIQ_55 = E_FIQEXPH_START + 7,
351 E_FIQ_56 = E_FIQEXPH_START + 8,
352 E_FIQ_57 = E_FIQEXPH_START + 9,
353 E_FIQ_58 = E_FIQEXPH_START + 10,
354 E_FIQ_59 = E_FIQEXPH_START + 11,
355 E_FIQ_60 = E_FIQEXPH_START + 12,
356 E_FIQ_61 = E_FIQEXPH_START + 13,
357 E_FIQ_62 = E_FIQEXPH_START + 14,
358 E_FIQ_63 = E_FIQEXPH_START + 15,
359 E_FIQEXPH_END = E_FIQEXPH_START + 15,
360
361 E_IRQHYPL_START = CONFIG_IRQHYPL_BASE_ADDRESS,
362 E_IRQ_64 = E_IRQHYPL_START + 0,
363 E_IRQ_65 = E_IRQHYPL_START + 1,
364 E_IRQ_66 = E_IRQHYPL_START + 2,
365 E_IRQ_67 = E_IRQHYPL_START + 3,
366 E_IRQ_68 = E_IRQHYPL_START + 4,
367 E_IRQ_69 = E_IRQHYPL_START + 5,
368 E_IRQ_70 = E_IRQHYPL_START + 6,
369 E_IRQ_71 = E_IRQHYPL_START + 7,
370 E_IRQ_72 = E_IRQHYPL_START + 8,
371 E_IRQ_73 = E_IRQHYPL_START + 9,
372 E_IRQ_74 = E_IRQHYPL_START + 10,
373 E_IRQ_75 = E_IRQHYPL_START + 11,
374 E_IRQ_76 = E_IRQHYPL_START + 12,
375 E_IRQ_77 = E_IRQHYPL_START + 13,
376 E_IRQ_78 = E_IRQHYPL_START + 14,
377 E_IRQ_79 = E_IRQHYPL_START + 15,
378 E_IRQHYPL_END = E_IRQHYPL_START + 15,
379
380 E_IRQHYPH_START = CONFIG_IRQHYPH_BASE_ADDRESS,
381 E_IRQ_80 = E_IRQHYPH_START + 0,
382 E_IRQ_81 = E_IRQHYPH_START + 1,
383 E_IRQ_82 = E_IRQHYPH_START + 2,
384 E_IRQ_83 = E_IRQHYPH_START + 3,
385 E_IRQ_84 = E_IRQHYPH_START + 4,
386 E_IRQ_85 = E_IRQHYPH_START + 5,
387 E_IRQ_86 = E_IRQHYPH_START + 6,
388 E_IRQ_87 = E_IRQHYPH_START + 7,
389 E_IRQ_88 = E_IRQHYPH_START + 8,
390 E_IRQ_89 = E_IRQHYPH_START + 9,
391 E_IRQ_90 = E_IRQHYPH_START + 10,
392 E_IRQ_91 = E_IRQHYPH_START + 11,
393 E_IRQ_92 = E_IRQHYPH_START + 12,
394 E_IRQ_93 = E_IRQHYPH_START + 13,
395 E_IRQ_94 = E_IRQHYPH_START + 14,
396 E_IRQ_95 = E_IRQHYPH_START + 15,
397 E_IRQHYPH_END = E_IRQHYPH_START + 15,
398
399
400 E_FIQHYPL_START = CONFIG_FIQHYPL_BASE_ADDRESS,
401 E_FIQ_64 = E_FIQHYPL_START + 0,
402 E_FIQ_65 = E_FIQHYPL_START + 1,
403 E_FIQ_66 = E_FIQHYPL_START + 2,
404 E_FIQ_67 = E_FIQHYPL_START + 3,
405 E_FIQ_68 = E_FIQHYPL_START + 4,
406 E_FIQ_69 = E_FIQHYPL_START + 5,
407 E_FIQ_70 = E_FIQHYPL_START + 6,
408 E_FIQ_71 = E_FIQHYPL_START + 7,
409 E_FIQ_72 = E_FIQHYPL_START + 8,
410 E_FIQ_73 = E_FIQHYPL_START + 9,
411 E_FIQ_74 = E_FIQHYPL_START + 10,
412 E_FIQ_75 = E_FIQHYPL_START + 11,
413 E_FIQ_76 = E_FIQHYPL_START + 12,
414 E_FIQ_77 = E_FIQHYPL_START + 13,
415 E_FIQ_78 = E_FIQHYPL_START + 14,
416 E_FIQ_79 = E_FIQHYPL_START + 15,
417 E_FIQHYPL_END = E_FIQHYPL_START + 15,
418
419 E_FIQHYPH_START = CONFIG_FIQHYPH_BASE_ADDRESS,
420 E_FIQ_80 = E_FIQHYPH_START + 0,
421 E_FIQ_81 = E_FIQHYPH_START + 1,
422 E_FIQ_82 = E_FIQHYPH_START + 2,
423 E_FIQ_83 = E_FIQHYPH_START + 3,
424 E_FIQ_84 = E_FIQHYPH_START + 4,
425 E_FIQ_85 = E_FIQHYPH_START + 5,
426 E_FIQ_86 = E_FIQHYPH_START + 6,
427 E_FIQ_87 = E_FIQHYPH_START + 7,
428 E_FIQ_88 = E_FIQHYPH_START + 8,
429 E_FIQ_89 = E_FIQHYPH_START + 9,
430 E_FIQ_90 = E_FIQHYPH_START + 10,
431 E_FIQ_91 = E_FIQHYPH_START + 11,
432 E_FIQ_92 = E_FIQHYPH_START + 12,
433 E_FIQ_93 = E_FIQHYPH_START + 13,
434 E_FIQ_94 = E_FIQHYPH_START + 14,
435 E_FIQ_95 = E_FIQHYPH_START + 15,
436 E_FIQHYPH_END = E_FIQHYPH_START + 15,
437
438 E_IRQ_FIQ_NONE = 0xFE,
439 E_IRQ_FIQ_ALL = 0xFF
440
441 } IRQFIQNum;
442
443 static MS_U32 IntEnum2HWIdx[E_INT_IRQ_MAX];
444 static MS_U32 HWIdx2IntEnum[E_IRQ_FIQ_ALL];
445 #if defined(MSOS_TYPE_LINUX_KERNEL)
446 static char DefaultName[5] = "NONE";
447 static char* HWIdx2IRQname[E_IRQ_FIQ_ALL] = {DefaultName};
448 #endif
449
450
HAL_UpdateIrqTable(MS_U32 byHardwareIndex,MS_U32 bySoftwareIndex)451 static void HAL_UpdateIrqTable(MS_U32 byHardwareIndex, MS_U32 bySoftwareIndex)
452 {
453 if(bySoftwareIndex == E_INT_RESERVED)
454 {
455 IntEnum2HWIdx[bySoftwareIndex] = E_IRQ_FIQ_NONE;
456 HWIdx2IntEnum[byHardwareIndex] = E_INT_IRQ_FIQ_NONE;
457 }
458 else
459 {
460 IntEnum2HWIdx[bySoftwareIndex] = byHardwareIndex;
461 HWIdx2IntEnum[byHardwareIndex] = bySoftwareIndex;
462 }
463 }
464
HAL_InitIrqTable(void)465 static void HAL_InitIrqTable(void)
466 {
467 unsigned int dwDataCounter = 0;
468
469 for(dwDataCounter = 0; dwDataCounter < E_IRQ_FIQ_ALL; dwDataCounter ++)
470 {
471 IntEnum2HWIdx[dwDataCounter] = E_IRQ_FIQ_NONE;
472 HWIdx2IntEnum[dwDataCounter] = E_INT_IRQ_FIQ_NONE;
473 }
474
475 for(dwDataCounter = E_IRQ_FIQ_ALL; dwDataCounter < E_INT_IRQ_MAX; dwDataCounter++)
476 {
477 IntEnum2HWIdx[dwDataCounter] = E_IRQ_FIQ_NONE;
478 }
479
480 HAL_UpdateIrqTable(E_IRQ_00, E_INT_IRQ_UART0); //int_uart0
481 HAL_UpdateIrqTable(E_IRQ_01, E_INT_IRQ_MIIC_INT1); //miic1_int
482 HAL_UpdateIrqTable(E_IRQ_02, E_INT_IRQ_MVD2MIPS); //mvd2mips_int
483 HAL_UpdateIrqTable(E_IRQ_03, E_INT_IRQ_MVD); //mvd_int
484 HAL_UpdateIrqTable(E_IRQ_04, E_INT_IRQ_FIQ_NONE); //~reg_top_gpio_in[2]
485 HAL_UpdateIrqTable(E_IRQ_05, E_INT_IRQ_CA_NSK_INT); //ca_nsk_int
486 HAL_UpdateIrqTable(E_IRQ_06, E_INT_IRQ_USB); //usb_int
487 HAL_UpdateIrqTable(E_IRQ_07, E_INT_IRQ_UHC); //uhc_int
488 HAL_UpdateIrqTable(E_IRQ_08, E_INT_IRQ_ZDEC); //zdec_irq
489 HAL_UpdateIrqTable(E_IRQ_09, E_INT_IRQ_GMAC); //gmac_int
490 HAL_UpdateIrqTable(E_IRQ_10, E_INT_IRQ_DISP); //disp_int
491 HAL_UpdateIrqTable(E_IRQ_11, E_INT_IRQ_DHC); //dhc_int
492 HAL_UpdateIrqTable(E_IRQ_12, E_INT_IRQ_MSPI0); //mspi_int
493 HAL_UpdateIrqTable(E_IRQ_13, E_INT_IRQ_EVD); //evd_int
494 HAL_UpdateIrqTable(E_IRQ_14, E_INT_IRQ_EVD_LITE); //evd_lite_int
495 HAL_UpdateIrqTable(E_IRQ_15, E_INT_IRQ_FIQ_NONE); //Reserved.
496
497 HAL_UpdateIrqTable(E_IRQ_16, E_INT_IRQ_TSP2HK); //tsp2hk_int
498 HAL_UpdateIrqTable(E_IRQ_17, E_INT_IRQ_VE); //ve_int
499 HAL_UpdateIrqTable(E_IRQ_18, E_INT_IRQ_AEON2HI); //irq_aeon2hi
500 HAL_UpdateIrqTable(E_IRQ_19, E_INT_IRQ_DC); //dc_int
501 HAL_UpdateIrqTable(E_IRQ_20, E_INT_IRQ_GOP); //gop_int
502 HAL_UpdateIrqTable(E_IRQ_21, E_INT_IRQ_FIQ_NONE); //Reserved.
503 HAL_UpdateIrqTable(E_IRQ_22, E_INT_IRQ_MIIC_INT0); //miic0_int
504 HAL_UpdateIrqTable(E_IRQ_23, E_INT_IRQ_RTC); //rtc0_int
505 HAL_UpdateIrqTable(E_IRQ_24, E_INT_IRQ_KEYPAD); //keypad_int
506 HAL_UpdateIrqTable(E_IRQ_25, E_INT_IRQ_PM); //pm_int
507 HAL_UpdateIrqTable(E_IRQ_26, E_INT_IRQ_MFE); //mfe_int
508 HAL_UpdateIrqTable(E_IRQ_27, E_INT_FIQ_UP_IRQ_EMM_ECM); //up_irq_emm_ecm
509 HAL_UpdateIrqTable(E_IRQ_28, E_INT_IRQ_UP_IRQ_UART_CA); //up_irq_uart_ca
510 HAL_UpdateIrqTable(E_IRQ_29, E_INT_IRQ_RTC1); //rtc1_int
511 HAL_UpdateIrqTable(E_IRQ_30, E_INT_IRQ_CA_IP_INT); //ca_ip_int
512 HAL_UpdateIrqTable(E_IRQ_31, E_INT_IRQ_ADCDVI2RIU); //adcdvi2riu_int
513
514 HAL_UpdateIrqTable(E_IRQ_32, E_INT_IRQ_TSP_TSO0); //tsp_tso0_int
515 HAL_UpdateIrqTable(E_IRQ_33, E_INT_IRQ_USB1); //usb_int1
516 HAL_UpdateIrqTable(E_IRQ_34, E_INT_IRQ_UHC1); //uhc_int1
517 HAL_UpdateIrqTable(E_IRQ_35, E_INT_IRQ_MIU); //miu_int
518 HAL_UpdateIrqTable(E_IRQ_36, E_INT_IRQ_ERROR_RESP); //error_resp_int
519 HAL_UpdateIrqTable(E_IRQ_37, E_INT_IRQ_OTG); //otg_int
520 HAL_UpdateIrqTable(E_IRQ_38, E_INT_IRQ_FIQ_NONE); //Reserved.
521 HAL_UpdateIrqTable(E_IRQ_39, E_INT_IRQ_UART1); //int_uart1
522 HAL_UpdateIrqTable(E_IRQ_40, E_INT_IRQ_SVD_HVD); //hvd_int
523 HAL_UpdateIrqTable(E_IRQ_41, E_INT_IRQ_FIQ_NONE); //reg_top_gpio_in[4]
524 HAL_UpdateIrqTable(E_IRQ_42, E_INT_IRQ_FIQ_NONE); //~reg_top_gpio_in[4]
525 HAL_UpdateIrqTable(E_IRQ_43, E_INT_IRQ_EMMC_OSP_INT); //emmc_osp_int
526 HAL_UpdateIrqTable(E_IRQ_44, E_INT_IRQ_CA_RSA_INT0); //ca_crypto_dma_int
527 HAL_UpdateIrqTable(E_IRQ_45, E_INT_IRQ_JPD); //jpd_int
528 HAL_UpdateIrqTable(E_IRQ_46, E_INT_IRQ_DISP1); //disp1_int
529 HAL_UpdateIrqTable(E_IRQ_47, E_INT_IRQ_AKL_INT); //akl_intrrupt
530
531 HAL_UpdateIrqTable(E_IRQ_48, E_INT_IRQ_BDMA0); //int_bdma[0]
532 HAL_UpdateIrqTable(E_IRQ_49, E_INT_IRQ_BDMA1); //int_bdma[1]
533 HAL_UpdateIrqTable(E_IRQ_50, E_INT_IRQ_UART2MCU); //uart2mcu_intr
534 HAL_UpdateIrqTable(E_IRQ_51, E_INT_IRQ_URDMA2MCU); //urdma2mcu_intr
535 HAL_UpdateIrqTable(E_IRQ_52, E_INT_IRQ_FIQ_NONE); //Reserved.
536 HAL_UpdateIrqTable(E_IRQ_53, E_INT_IRQ_CEC); //cec_irq_out
537 HAL_UpdateIrqTable(E_IRQ_54, E_INT_IRQ_HDMI_LEVEL); //HDMITX_IRQ_LEVEL
538 HAL_UpdateIrqTable(E_IRQ_55, E_INT_IRQ_FCIE2RIU); //fcie_int
539 HAL_UpdateIrqTable(E_IRQ_56, E_INT_IRQ_HDCP_X74); //hdcp_x74_int
540 HAL_UpdateIrqTable(E_IRQ_57, E_INT_IRQ_GPD); //gpd_int
541 HAL_UpdateIrqTable(E_IRQ_58, E_INT_IRQ_SAR1); //SAR1_int
542 HAL_UpdateIrqTable(E_IRQ_59, E_INT_IRQ_IDAC_PLUG_DET); //irq_dac_plug_det
543 HAL_UpdateIrqTable(E_IRQ_60, E_INT_IRQ_FIQ_NONE); //reg_top_gpio_in[2]
544 HAL_UpdateIrqTable(E_IRQ_61, E_INT_IRQ_RASP); //rasp0_int
545 HAL_UpdateIrqTable(E_IRQ_62, E_INT_IRQ_TSP_FI_QUEUE_INT); //fi_queue_int
546 HAL_UpdateIrqTable(E_IRQ_63, E_INT_IRQ_FRM_PM); //irq_frm_pm
547 HAL_UpdateIrqTable(E_IRQ_64, E_INT_IRQ_MIIC_INT2); //miic2_int
548 HAL_UpdateIrqTable(E_IRQ_65, E_INT_IRQ_MIIC_INT3); //miic3_int
549 HAL_UpdateIrqTable(E_IRQ_66, E_INT_IRQ_MIIC_INT4); //miic4_int
550 HAL_UpdateIrqTable(E_IRQ_67, E_INT_IRQ_MIIC_INT5); //miic5_int
551 HAL_UpdateIrqTable(E_IRQ_68, E_INT_IRQ_HDMITX); //hdmitx_phy_int
552 HAL_UpdateIrqTable(E_IRQ_69, E_INT_IRQ_GE); //ge_int
553 HAL_UpdateIrqTable(E_IRQ_70, E_INT_IRQ_MIU_SECURE); //miu_security_int
554 HAL_UpdateIrqTable(E_IRQ_71, E_INT_IRQ_FIQ_NONE); //Reserved.
555 HAL_UpdateIrqTable(E_IRQ_72, E_INT_IRQ_G3D2MCU); //g3d2mcu_irq_dft
556 HAL_UpdateIrqTable(E_IRQ_73, E_INT_FIQEXPH_CMDQ); //cmdq_int
557 HAL_UpdateIrqTable(E_IRQ_74, E_INT_IRQ_AUDMA_V2_INT); //AUDMA_V2_INTR
558 HAL_UpdateIrqTable(E_IRQ_75, E_INT_IRQ_SCDC_PM_INT); //scdc_int_pm
559 HAL_UpdateIrqTable(E_IRQ_76, E_FRCINT_IRQ_MSPI2); //mspi2_int
560 HAL_UpdateIrqTable(E_IRQ_77, E_INT_IRQ_SMART); //smart_int0
561 HAL_UpdateIrqTable(E_IRQ_78, E_INT_IRQ_FIQ_NONE); //Reserved..
562 HAL_UpdateIrqTable(E_IRQ_79, E_INT_IRQ_DCSUB); //dc_sub_int
563 HAL_UpdateIrqTable(E_IRQ_80, E_INT_IRQ_SDIO); //sdio_int
564 HAL_UpdateIrqTable(E_IRQ_81, E_INT_IRQ_EMAC); //emac
565 HAL_UpdateIrqTable(E_IRQ_82, E_INT_IRQ_FIQ_NONE); //Reserved.
566 HAL_UpdateIrqTable(E_IRQ_83, E_INT_IRQ_FIQ_NONE); //Reserved.
567 HAL_UpdateIrqTable(E_IRQ_84, E_INT_IRQ_FIQ_NONE); //Reserved.
568 HAL_UpdateIrqTable(E_IRQ_85, E_INT_IRQ_FIQ_NONE); //Reserved
569 HAL_UpdateIrqTable(E_IRQ_86, E_INT_IRQ_USB2); //ubb_int_p2
570 HAL_UpdateIrqTable(E_IRQ_87, E_INT_IRQ_UHC2); //uhc_int_p2
571 HAL_UpdateIrqTable(E_IRQ_88, E_INT_IRQ_FIQ_NONE); //miu_ns_int
572 HAL_UpdateIrqTable(E_IRQ_89, E_INT_IRQ_FIQ_NONE); //Reserved.
573 HAL_UpdateIrqTable(E_IRQ_90, E_INT_IRQ_VIVALDI_V9_MIU_AL); //INT_v9_mui_al
574 HAL_UpdateIrqTable(E_IRQ_91, E_INT_IRQ_SDIO_OSP_INT); //sdio_osp_int
575 HAL_UpdateIrqTable(E_IRQ_92, E_INT_IRQ_MIU_TLB_INT); //miu_tlb_int
576 HAL_UpdateIrqTable(E_IRQ_93, E_INT_IRQ_DIPW); //dipw_INT
577 HAL_UpdateIrqTable(E_IRQ_94, E_INT_IRQ_FIQ_NONE); //diamond_reg_rxiu_timeout_nodefine_int
578 HAL_UpdateIrqTable(E_IRQ_95, E_INT_IRQ_PAS_PTS_COMBINE_INT); //PAS_PTS_INTRL_COMBINE
579
580 HAL_UpdateIrqTable(E_FIQ_00, E_INT_FIQ_EXTIMER0); //int_timer0
581 HAL_UpdateIrqTable(E_FIQ_01, E_INT_FIQ_EXTIMER1); //int_timer1
582 HAL_UpdateIrqTable(E_FIQ_02, E_INT_FIQ_WDT); //int_wdt
583 HAL_UpdateIrqTable(E_FIQ_03, E_INT_FIQ_SEC_TIMER0); //int_sec_timer0
584 HAL_UpdateIrqTable(E_FIQ_04, E_INT_FIQ_SEC_TIMER1); //int_sec_timer1
585 HAL_UpdateIrqTable(E_FIQ_05, E_INT_FIQ_R2TOMCU_INT0); //MB_auR2to_MCU_INT[0]
586 HAL_UpdateIrqTable(E_FIQ_06, E_INT_FIQ_DSPTOMCU_INT0); //MB_DSP2toMCU_INT[0]
587 HAL_UpdateIrqTable(E_FIQ_07, E_INT_FIQ_DSPTOMCU_INT1); //MB_DSP2toMCU_INT[1]
588 HAL_UpdateIrqTable(E_FIQ_08, E_INT_FIQ_R2TOMCU_INT1); //MB_auR2to_MCU_INT[1]
589 HAL_UpdateIrqTable(E_FIQ_09, E_INT_FIQ_UP_IRQ_UART_CA); //up_irq_uart_ca
590 HAL_UpdateIrqTable(E_FIQ_10, E_INT_FIQ_R2TOMCU_INT2); //MB_auR2to_MCU_INT[2]
591 HAL_UpdateIrqTable(E_FIQ_11, E_INT_FIQ_HDMI_NON_PCM); //HDMI_NON_PCM_MODE_INT_OUT
592 HAL_UpdateIrqTable(E_FIQ_12, E_INT_FIQ_SPDIF_IN_NON_PCM); //SPDIF_IN_NON_PCM_INT_OUT
593 HAL_UpdateIrqTable(E_FIQ_13, E_INT_FIQ_LAN_ESD_INT); //lan_esd_int
594 HAL_UpdateIrqTable(E_FIQ_14, E_INT_FIQ_SE_DSP2UP); //SE_DSP2UP_intr
595 HAL_UpdateIrqTable(E_FIQ_15, E_INT_FIQ_TSP2AEON); //tsp2aeon_int
596
597 HAL_UpdateIrqTable(E_FIQ_16, E_INT_FIQ_VIVALDI_STR); //vivaldi_str_intr
598 HAL_UpdateIrqTable(E_FIQ_17, E_INT_FIQ_VIVALDI_PTS); //vivaldi_pts_intr
599 HAL_UpdateIrqTable(E_FIQ_18, E_INT_FIQ_DSP_MIU_PROT); //DSP_MIU_PROT_intr
600 HAL_UpdateIrqTable(E_FIQ_19, E_INT_FIQ_XIU_TIMEOUT); //xiu_timeout_int
601 HAL_UpdateIrqTable(E_FIQ_20, E_INT_IRQ_FIQ_NONE); //Reserved.
602 HAL_UpdateIrqTable(E_FIQ_21, E_INT_FIQ_VSYNC_VE4VBI); //ve_vbi_f0_int
603 HAL_UpdateIrqTable(E_FIQ_22, E_INT_FIQ_FIELD_VE4VBI); //ve_vbi_f1_int
604 HAL_UpdateIrqTable(E_FIQ_23, E_INT_FIQ_R2TOMCU_INT3); //MB_auR2to_MCU_INT[3]
605 HAL_UpdateIrqTable(E_FIQ_24, E_INT_FIQ_VE_DONE_TT); //ve_done_TT_irq
606 HAL_UpdateIrqTable(E_FIQ_25, E_INT_FIQ_INT_CCFL); //INT_CCFL
607 HAL_UpdateIrqTable(E_FIQ_26, E_INT_IRQ_FIQ_NONE); //int_in
608 HAL_UpdateIrqTable(E_FIQ_27, E_INT_FIQ_IR); //ir_int
609 HAL_UpdateIrqTable(E_FIQ_28, E_INT_FIQ_AU_SPDIF_TX_CS0); //AU_SPDIF_TX_CS_INT[0]
610 HAL_UpdateIrqTable(E_FIQ_29, E_INT_IRQ_FIQ_NONE); //Reserved
611 HAL_UpdateIrqTable(E_FIQ_30, E_INT_FIQ_AU_SPDIF_TX_CS1); //AU_SPDIF_TX_CS_INT[1]
612 HAL_UpdateIrqTable(E_FIQ_31, E_INT_FIQ_DEC_DSP2MIPS); //DSP2MIPS_INT
613
614 HAL_UpdateIrqTable(E_FIQ_32, E_INT_FIQ_IR_INT_RC); //ir_int_rc
615 HAL_UpdateIrqTable(E_FIQ_33, E_INT_FIQ_AU_DMA_BUF_INT); //AU_DMA_BUFFER_INT_EDGE
616 HAL_UpdateIrqTable(E_FIQ_34, E_INT_FIQ_VE_SW_WR2BUF); //ve_sw_wr2buf_int
617 HAL_UpdateIrqTable(E_FIQ_35, E_INT_IRQ_UP_IRQ_EMM_ECM); //up_irq_emm_ecm
618 HAL_UpdateIrqTable(E_FIQ_36, E_INT_IRQ_FIQ_NONE); //reg_hst0to3_int # HOST 0 - PM 8051
619 HAL_UpdateIrqTable(E_FIQ_37, E_INT_FIQ_8051_TO_BEON); //reg_hst0to2_int # HOST 1 - Secure R2
620 HAL_UpdateIrqTable(E_FIQ_38, E_INT_FIQ_8051_TO_SECURER2); //reg_hst0to1_int # HOST 2 - ACPU Core0 (BEON)
621 HAL_UpdateIrqTable(E_FIQ_39, E_INT_IRQ_FIQ_NONE); //Reserved # HOST 3 - Secure 8051/ACPU Core1 (No used)
622 HAL_UpdateIrqTable(E_FIQ_40, E_INT_IRQ_FIQ_NONE); //reg_hst1to3_int
623 HAL_UpdateIrqTable(E_FIQ_41, E_INT_FIQ_SECURER2_TO_BEON); //reg_hst1to2_int
624 HAL_UpdateIrqTable(E_FIQ_42, E_INT_FIQ_SECURER2_TO_8051); //reg_hst1to0_int
625 HAL_UpdateIrqTable(E_FIQ_43, E_INT_IRQ_FIQ_NONE); //Reserved.
626 HAL_UpdateIrqTable(E_FIQ_44, E_INT_IRQ_FIQ_NONE); //reg_hst2to3_int
627 HAL_UpdateIrqTable(E_FIQ_45, E_INT_FIQ_BEON_TO_SECURER2); //reg_hst2to1_int
628 HAL_UpdateIrqTable(E_FIQ_46, E_INT_FIQ_BEON_TO_8051); //reg_hst2to0_int
629 HAL_UpdateIrqTable(E_FIQ_47, E_INT_IRQ_FIQ_NONE); //Reserved.
630
631 HAL_UpdateIrqTable(E_FIQ_48, E_INT_IRQ_FIQ_NONE); //reg_hst3to2_int
632 HAL_UpdateIrqTable(E_FIQ_49, E_INT_IRQ_FIQ_NONE); //reg_hst3to1_int
633 HAL_UpdateIrqTable(E_FIQ_50, E_INT_IRQ_FIQ_NONE); //reg_hst3to0_int
634 HAL_UpdateIrqTable(E_FIQ_51, E_INT_IRQ_FIQ_NONE); //Reserved.
635 HAL_UpdateIrqTable(E_FIQ_52, E_INT_IRQ_FIQ_NONE); //Reserved.
636 HAL_UpdateIrqTable(E_FIQ_53, E_INT_IRQ_FIQ_NONE); //Reserved.
637 HAL_UpdateIrqTable(E_FIQ_54, E_INT_FIQ_HDMITX_IRQ_EDGE); //HDMITX_IRQ_EDGE
638 HAL_UpdateIrqTable(E_FIQ_55, E_INT_IRQ_FIQ_NONE); //Reserved.
639 HAL_UpdateIrqTable(E_FIQ_56, E_INT_FIQ_CA_CRYPTO_DMA); //crypto_dma_int
640 HAL_UpdateIrqTable(E_FIQ_57, E_INT_IRQ_FIQ_NONE); //Reserved
641 HAL_UpdateIrqTable(E_FIQ_58, E_INT_IRQ_FIQ_NONE); //Reserved
642 HAL_UpdateIrqTable(E_FIQ_59, E_INT_IRQ_FIQ_NONE); //Reserved
643 HAL_UpdateIrqTable(E_FIQ_60, E_INT_IRQ_FIQ_NONE); //Reserved
644 HAL_UpdateIrqTable(E_FIQ_61, E_INT_IRQ_FIQ_NONE); //Reserved
645 HAL_UpdateIrqTable(E_FIQ_62, E_INT_IRQ_FIQ_NONE); //Reserved
646 HAL_UpdateIrqTable(E_FIQ_63, E_INT_FIQ_FRM_PM); //fiq_frm_pm
647
648 HAL_UpdateIrqTable(E_FIQ_64, E_INT_FIQ_SEC_GUARD_INT); //sec_guard_int
649 HAL_UpdateIrqTable(E_FIQ_65, E_INT_FIQ_PM_SD_CDZ0); //SD_CDZ_IN
650
651 }
652
653 #ifdef __cplusplus
654 }
655 #endif
656
657 #endif // _HAL_IRQTBL_H_
658
659