1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78
79 #ifndef _HAL_IRQTBL_H_
80 #define _HAL_IRQTBL_H_
81
82 #ifdef __cplusplus
83 extern "C"
84 {
85 #endif
86
87 #define E_INT_RESERVED E_INT_IRQ_FIQ_NONE
88 #define CONFIG_MAX_INTERRUPT_CLIENT 350
89 #define CONFIG_MAX_INTERRUPT_ENUM_ID 350
90
91 #if defined(MSOS_TYPE_LINUX)
92
93 #ifdef CONFIG_INT_SPI_MODE
94 //Set Interrupt Base Address in SPI Mode
95 #define CONFIG_IRQL_BASE_ADDRESS 0x00
96 #define CONFIG_IRQH_BASE_ADDRESS 0x10
97 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x20
98 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x30
99 #define CONFIG_FIQL_BASE_ADDRESS 0x40
100 #define CONFIG_FIQH_BASE_ADDRESS 0x50
101 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
102 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
103
104 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
105 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
106 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xA0
107 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xB0
108 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xC0
109 #define CONFIG_FIQHYPH_BASE_ADDRESS 0xD0
110 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xE0
111 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xF0
112
113 #else
114 //Set Interrupt Base Address in PPI Mode
115 #define CONFIG_IRQL_BASE_ADDRESS 0x40
116 #define CONFIG_IRQH_BASE_ADDRESS 0x50
117 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x60
118 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x70
119 #define CONFIG_FIQL_BASE_ADDRESS 0x00
120 #define CONFIG_FIQH_BASE_ADDRESS 0x10
121 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x20
122 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x30
123
124 #define CONFIG_IRQHYPL_BASE_ADDRESS 0xC0
125 #define CONFIG_IRQHYPH_BASE_ADDRESS 0xD0
126 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xE0
127 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xF0
128 #define CONFIG_FIQHYPL_BASE_ADDRESS 0x80
129 #define CONFIG_FIQHYPH_BASE_ADDRESS 0x90
130 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xA0
131 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xB0
132
133 #endif
134
135 #elif defined(MSOS_TYPE_NOS)
136 //Set Interrupt Base Address in PPI Mode
137 #define CONFIG_IRQL_BASE_ADDRESS 0x00
138 #define CONFIG_IRQH_BASE_ADDRESS 0x10
139 #define CONFIG_FIQL_BASE_ADDRESS 0x20
140 #define CONFIG_FIQH_BASE_ADDRESS 0x30
141 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x40
142 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x50
143 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
144 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
145
146 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
147 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
148 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xA0
149 #define CONFIG_FIQHYPH_BASE_ADDRESS 0xB0
150 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xC0
151 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xD0
152 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xE0
153 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xF0
154
155 #elif defined(MSOS_TYPE_NUTTX)
156 //Set Interrupt Base Address in PPI Mode
157 #define CONFIG_IRQL_BASE_ADDRESS 0x00
158 #define CONFIG_IRQH_BASE_ADDRESS 0x10
159 #define CONFIG_FIQL_BASE_ADDRESS 0x20
160 #define CONFIG_FIQH_BASE_ADDRESS 0x30
161 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x40
162 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x50
163 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
164 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
165
166 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
167 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
168 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xA0
169 #define CONFIG_FIQHYPH_BASE_ADDRESS 0xB0
170 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xC0
171 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xD0
172 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xE0
173 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xF0
174 #else
175 #error "Unknown Platform Selection"
176 #endif
177
178 typedef enum
179 {
180 E_IRQL_START = CONFIG_IRQL_BASE_ADDRESS,
181 E_IRQ_00 = E_IRQL_START + 0,
182 E_IRQ_01 = E_IRQL_START + 1,
183 E_IRQ_02 = E_IRQL_START + 2,
184 E_IRQ_03 = E_IRQL_START + 3,
185 E_IRQ_04 = E_IRQL_START + 4,
186 E_IRQ_05 = E_IRQL_START + 5,
187 E_IRQ_06 = E_IRQL_START + 6,
188 E_IRQ_07 = E_IRQL_START + 7,
189 E_IRQ_08 = E_IRQL_START + 8,
190 E_IRQ_09 = E_IRQL_START + 9,
191 E_IRQ_10 = E_IRQL_START + 10,
192 E_IRQ_11 = E_IRQL_START + 11,
193 E_IRQ_12 = E_IRQL_START + 12,
194 E_IRQ_13 = E_IRQL_START + 13,
195 E_IRQ_14 = E_IRQL_START + 14,
196 E_IRQ_15 = E_IRQL_START + 15,
197 E_IRQL_END = E_IRQL_START + 15,
198
199 E_IRQH_START = CONFIG_IRQH_BASE_ADDRESS,
200 E_IRQ_16 = E_IRQH_START + 0,
201 E_IRQ_17 = E_IRQH_START + 1,
202 E_IRQ_18 = E_IRQH_START + 2,
203 E_IRQ_19 = E_IRQH_START + 3,
204 E_IRQ_20 = E_IRQH_START + 4,
205 E_IRQ_21 = E_IRQH_START + 5,
206 E_IRQ_22 = E_IRQH_START + 6,
207 E_IRQ_23 = E_IRQH_START + 7,
208 E_IRQ_24 = E_IRQH_START + 8,
209 E_IRQ_25 = E_IRQH_START + 9,
210 E_IRQ_26 = E_IRQH_START + 10,
211 E_IRQ_27 = E_IRQH_START + 11,
212 E_IRQ_28 = E_IRQH_START + 12,
213 E_IRQ_29 = E_IRQH_START + 13,
214 E_IRQ_30 = E_IRQH_START + 14,
215 E_IRQ_31 = E_IRQH_START + 15,
216 E_IRQH_END = E_IRQH_START + 15,
217
218 E_FIQL_START = CONFIG_FIQL_BASE_ADDRESS,
219 E_FIQ_00 = E_FIQL_START + 0,
220 E_FIQ_01 = E_FIQL_START + 1,
221 E_FIQ_02 = E_FIQL_START + 2,
222 E_FIQ_03 = E_FIQL_START + 3,
223 E_FIQ_04 = E_FIQL_START + 4,
224 E_FIQ_05 = E_FIQL_START + 5,
225 E_FIQ_06 = E_FIQL_START + 6,
226 E_FIQ_07 = E_FIQL_START + 7,
227 E_FIQ_08 = E_FIQL_START + 8,
228 E_FIQ_09 = E_FIQL_START + 9,
229 E_FIQ_10 = E_FIQL_START + 10,
230 E_FIQ_11 = E_FIQL_START + 11,
231 E_FIQ_12 = E_FIQL_START + 12,
232 E_FIQ_13 = E_FIQL_START + 13,
233 E_FIQ_14 = E_FIQL_START + 14,
234 E_FIQ_15 = E_FIQL_START + 15,
235 E_FIQL_END = E_FIQL_START + 15,
236
237 E_FIQH_START = CONFIG_FIQH_BASE_ADDRESS,
238 E_FIQ_16 = E_FIQH_START + 0,
239 E_FIQ_17 = E_FIQH_START + 1,
240 E_FIQ_18 = E_FIQH_START + 2,
241 E_FIQ_19 = E_FIQH_START + 3,
242 E_FIQ_20 = E_FIQH_START + 4,
243 E_FIQ_21 = E_FIQH_START + 5,
244 E_FIQ_22 = E_FIQH_START + 6,
245 E_FIQ_23 = E_FIQH_START + 7,
246 E_FIQ_24 = E_FIQH_START + 8,
247 E_FIQ_25 = E_FIQH_START + 9,
248 E_FIQ_26 = E_FIQH_START + 10,
249 E_FIQ_27 = E_FIQH_START + 11,
250 E_FIQ_28 = E_FIQH_START + 12,
251 E_FIQ_29 = E_FIQH_START + 13,
252 E_FIQ_30 = E_FIQH_START + 14,
253 E_FIQ_31 = E_FIQH_START + 15,
254 E_FIQH_END = E_FIQH_START + 15,
255
256 E_IRQEXPL_START = CONFIG_IRQEXPL_BASE_ADDRESS,
257 E_IRQ_32 = E_IRQEXPL_START + 0,
258 E_IRQ_33 = E_IRQEXPL_START + 1,
259 E_IRQ_34 = E_IRQEXPL_START + 2,
260 E_IRQ_35 = E_IRQEXPL_START + 3,
261 E_IRQ_36 = E_IRQEXPL_START + 4,
262 E_IRQ_37 = E_IRQEXPL_START + 5,
263 E_IRQ_38 = E_IRQEXPL_START + 6,
264 E_IRQ_39 = E_IRQEXPL_START + 7,
265 E_IRQ_40 = E_IRQEXPL_START + 8,
266 E_IRQ_41 = E_IRQEXPL_START + 9,
267 E_IRQ_42 = E_IRQEXPL_START + 10,
268 E_IRQ_43 = E_IRQEXPL_START + 11,
269 E_IRQ_44 = E_IRQEXPL_START + 12,
270 E_IRQ_45 = E_IRQEXPL_START + 13,
271 E_IRQ_46 = E_IRQEXPL_START + 14,
272 E_IRQ_47 = E_IRQEXPL_START + 15,
273 E_IRQEXPL_END = E_IRQEXPL_START + 15,
274
275 E_IRQEXPH_START = CONFIG_IRQEXPH_BASE_ADDRESS,
276 E_IRQ_48 = E_IRQEXPH_START + 0,
277 E_IRQ_49 = E_IRQEXPH_START + 1,
278 E_IRQ_50 = E_IRQEXPH_START + 2,
279 E_IRQ_51 = E_IRQEXPH_START + 3,
280 E_IRQ_52 = E_IRQEXPH_START + 4,
281 E_IRQ_53 = E_IRQEXPH_START + 5,
282 E_IRQ_54 = E_IRQEXPH_START + 6,
283 E_IRQ_55 = E_IRQEXPH_START + 7,
284 E_IRQ_56 = E_IRQEXPH_START + 8,
285 E_IRQ_57 = E_IRQEXPH_START + 9,
286 E_IRQ_58 = E_IRQEXPH_START + 10,
287 E_IRQ_59 = E_IRQEXPH_START + 11,
288 E_IRQ_60 = E_IRQEXPH_START + 12,
289 E_IRQ_61 = E_IRQEXPH_START + 13,
290 E_IRQ_62 = E_IRQEXPH_START + 14,
291 E_IRQ_63 = E_IRQEXPH_START + 15,
292 E_IRQEXPH_END = E_IRQEXPH_START + 15,
293
294 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS,
295 E_FIQ_32 = E_FIQEXPL_START + 0,
296 E_FIQ_33 = E_FIQEXPL_START + 1,
297 E_FIQ_34 = E_FIQEXPL_START + 2,
298 E_FIQ_35 = E_FIQEXPL_START + 3,
299 E_FIQ_36 = E_FIQEXPL_START + 4,
300 E_FIQ_37 = E_FIQEXPL_START + 5,
301 E_FIQ_38 = E_FIQEXPL_START + 6,
302 E_FIQ_39 = E_FIQEXPL_START + 7,
303 E_FIQ_40 = E_FIQEXPL_START + 8,
304 E_FIQ_41 = E_FIQEXPL_START + 9,
305 E_FIQ_42 = E_FIQEXPL_START + 10,
306 E_FIQ_43 = E_FIQEXPL_START + 11,
307 E_FIQ_44 = E_FIQEXPL_START + 12,
308 E_FIQ_45 = E_FIQEXPL_START + 13,
309 E_FIQ_46 = E_FIQEXPL_START + 14,
310 E_FIQ_47 = E_FIQEXPL_START + 15,
311 E_FIQEXPL_END = E_FIQEXPL_START + 15,
312
313 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS,
314 E_FIQ_48 = E_FIQEXPH_START + 0,
315 E_FIQ_49 = E_FIQEXPH_START + 1,
316 E_FIQ_50 = E_FIQEXPH_START + 2,
317 E_FIQ_51 = E_FIQEXPH_START + 3,
318 E_FIQ_52 = E_FIQEXPH_START + 4,
319 E_FIQ_53 = E_FIQEXPH_START + 5,
320 E_FIQ_54 = E_FIQEXPH_START + 6,
321 E_FIQ_55 = E_FIQEXPH_START + 7,
322 E_FIQ_56 = E_FIQEXPH_START + 8,
323 E_FIQ_57 = E_FIQEXPH_START + 9,
324 E_FIQ_58 = E_FIQEXPH_START + 10,
325 E_FIQ_59 = E_FIQEXPH_START + 11,
326 E_FIQ_60 = E_FIQEXPH_START + 12,
327 E_FIQ_61 = E_FIQEXPH_START + 13,
328 E_FIQ_62 = E_FIQEXPH_START + 14,
329 E_FIQ_63 = E_FIQEXPH_START + 15,
330 E_FIQEXPH_END = E_FIQEXPH_START + 15,
331
332 E_IRQHYPL_START = CONFIG_IRQHYPL_BASE_ADDRESS,
333 E_IRQ_64 = E_IRQHYPL_START + 0,
334 E_IRQ_65 = E_IRQHYPL_START + 1,
335 E_IRQ_66 = E_IRQHYPL_START + 2,
336 E_IRQ_67 = E_IRQHYPL_START + 3,
337 E_IRQ_68 = E_IRQHYPL_START + 4,
338 E_IRQ_69 = E_IRQHYPL_START + 5,
339 E_IRQ_70 = E_IRQHYPL_START + 6,
340 E_IRQ_71 = E_IRQHYPL_START + 7,
341 E_IRQ_72 = E_IRQHYPL_START + 8,
342 E_IRQ_73 = E_IRQHYPL_START + 9,
343 E_IRQ_74 = E_IRQHYPL_START + 10,
344 E_IRQ_75 = E_IRQHYPL_START + 11,
345 E_IRQ_76 = E_IRQHYPL_START + 12,
346 E_IRQ_77 = E_IRQHYPL_START + 13,
347 E_IRQ_78 = E_IRQHYPL_START + 14,
348 E_IRQ_79 = E_IRQHYPL_START + 15,
349 E_IRQHYPL_END = E_IRQHYPL_START + 15,
350
351 E_IRQHYPH_START = CONFIG_IRQHYPH_BASE_ADDRESS,
352 E_IRQ_80 = E_IRQHYPH_START + 0,
353 E_IRQ_81 = E_IRQHYPH_START + 1,
354 E_IRQ_82 = E_IRQHYPH_START + 2,
355 E_IRQ_83 = E_IRQHYPH_START + 3,
356 E_IRQ_84 = E_IRQHYPH_START + 4,
357 E_IRQ_85 = E_IRQHYPH_START + 5,
358 E_IRQ_86 = E_IRQHYPH_START + 6,
359 E_IRQ_87 = E_IRQHYPH_START + 7,
360 E_IRQ_88 = E_IRQHYPH_START + 8,
361 E_IRQ_89 = E_IRQHYPH_START + 9,
362 E_IRQ_90 = E_IRQHYPH_START + 10,
363 E_IRQ_91 = E_IRQHYPH_START + 11,
364 E_IRQ_92 = E_IRQHYPH_START + 12,
365 E_IRQ_93 = E_IRQHYPH_START + 13,
366 E_IRQ_94 = E_IRQHYPH_START + 14,
367 E_IRQ_95 = E_IRQHYPH_START + 15,
368 E_IRQHYPH_END = E_IRQHYPH_START + 15,
369
370 E_FIQHYPL_START = CONFIG_FIQHYPL_BASE_ADDRESS,
371 E_FIQ_64 = E_FIQHYPL_START + 0,
372 E_FIQ_65 = E_FIQHYPL_START + 1,
373 E_FIQ_66 = E_FIQHYPL_START + 2,
374 E_FIQ_67 = E_FIQHYPL_START + 3,
375 E_FIQ_68 = E_FIQHYPL_START + 4,
376 E_FIQ_69 = E_FIQHYPL_START + 5,
377 E_FIQ_70 = E_FIQHYPL_START + 6,
378 E_FIQ_71 = E_FIQHYPL_START + 7,
379 E_FIQ_72 = E_FIQHYPL_START + 8,
380 E_FIQ_73 = E_FIQHYPL_START + 9,
381 E_FIQ_74 = E_FIQHYPL_START + 10,
382 E_FIQ_75 = E_FIQHYPL_START + 11,
383 E_FIQ_76 = E_FIQHYPL_START + 12,
384 E_FIQ_77 = E_FIQHYPL_START + 13,
385 E_FIQ_78 = E_FIQHYPL_START + 14,
386 E_FIQ_79 = E_FIQHYPL_START + 15,
387 E_FIQHYPL_END = E_FIQHYPL_START + 15,
388
389 E_FIQHYPH_START = CONFIG_FIQHYPH_BASE_ADDRESS,
390 E_FIQ_80 = E_FIQHYPH_START + 0,
391 E_FIQ_81 = E_FIQHYPH_START + 1,
392 E_FIQ_82 = E_FIQHYPH_START + 2,
393 E_FIQ_83 = E_FIQHYPH_START + 3,
394 E_FIQ_84 = E_FIQHYPH_START + 4,
395 E_FIQ_85 = E_FIQHYPH_START + 5,
396 E_FIQ_86 = E_FIQHYPH_START + 6,
397 E_FIQ_87 = E_FIQHYPH_START + 7,
398 E_FIQ_88 = E_FIQHYPH_START + 8,
399 E_FIQ_89 = E_FIQHYPH_START + 9,
400 E_FIQ_90 = E_FIQHYPH_START + 10,
401 E_FIQ_91 = E_FIQHYPH_START + 11,
402 E_FIQ_92 = E_FIQHYPH_START + 12,
403 E_FIQ_93 = E_FIQHYPH_START + 13,
404 E_FIQ_94 = E_FIQHYPH_START + 14,
405 E_FIQ_95 = E_FIQHYPH_START + 15,
406 E_FIQHYPH_END = E_FIQHYPH_START + 15,
407
408 E_IRQ_FIQ_NONE = 0xFE,
409 E_IRQ_FIQ_ALL = 0xFF
410
411 } IRQFIQNum;
412
413 static MS_U32 IntEnum2HWIdx[CONFIG_MAX_INTERRUPT_ENUM_ID];
414 static MS_U32 HWIdx2IntEnum[CONFIG_MAX_INTERRUPT_CLIENT];
415
HAL_UpdateIrqTable(MS_U32 dwHardwareIndex,MS_U32 dwSoftwareIndex)416 static void HAL_UpdateIrqTable(MS_U32 dwHardwareIndex, MS_U32 dwSoftwareIndex)
417 {
418 if(dwSoftwareIndex == E_INT_RESERVED)
419 {
420 IntEnum2HWIdx[dwSoftwareIndex] = E_IRQ_FIQ_NONE;
421 HWIdx2IntEnum[dwHardwareIndex] = E_INT_IRQ_FIQ_NONE;
422 }
423 else
424 {
425 IntEnum2HWIdx[dwSoftwareIndex] = dwHardwareIndex;
426 HWIdx2IntEnum[dwHardwareIndex] = dwSoftwareIndex;
427 }
428 }
429
HAL_InitIrqTable(void)430 static void HAL_InitIrqTable(void)
431 {
432 unsigned int dwDataCounter = 0;
433
434 for(dwDataCounter = 0; dwDataCounter < CONFIG_MAX_INTERRUPT_CLIENT; dwDataCounter ++)
435 {
436 HWIdx2IntEnum[dwDataCounter] = E_INT_IRQ_FIQ_NONE;
437 }
438
439 for(dwDataCounter = 0; dwDataCounter < CONFIG_MAX_INTERRUPT_ENUM_ID; dwDataCounter ++)
440 {
441 IntEnum2HWIdx[dwDataCounter] = E_IRQ_FIQ_NONE;
442 }
443
444 HAL_UpdateIrqTable(E_IRQ_00, E_INT_IRQ_UART0); //int_uart0
445 HAL_UpdateIrqTable(E_IRQ_01, E_INT_IRQ_PMSLEEP); //pm_sleep_int
446 HAL_UpdateIrqTable(E_IRQ_02, E_INT_IRQ_VD_EVD_R22HI_INT);//irq_vd_evd_r22hi (*)
447 HAL_UpdateIrqTable(E_IRQ_03, E_INT_IRQ_MVD); //mvd_int
448 HAL_UpdateIrqTable(E_IRQ_04, E_INT_IRQ_PS); //ps_int
449 HAL_UpdateIrqTable(E_IRQ_05, E_INT_IRQ_NFIE); //nfie_int
450 HAL_UpdateIrqTable(E_IRQ_06, E_INT_IRQ_USB); //usb_int
451 HAL_UpdateIrqTable(E_IRQ_07, E_INT_IRQ_UHC); //uhc_int
452 HAL_UpdateIrqTable(E_IRQ_08, E_INT_RESERVED); //Reserved
453 HAL_UpdateIrqTable(E_IRQ_09, E_INT_IRQ_EMAC); //emac_int
454 HAL_UpdateIrqTable(E_IRQ_10, E_INT_RESERVED); //Reserved
455 HAL_UpdateIrqTable(E_IRQ_11, E_INT_IRQ_MSPI0); //mspi_int
456 HAL_UpdateIrqTable(E_IRQ_12, E_INT_IRQ_GE); //ge_int
457 HAL_UpdateIrqTable(E_IRQ_13, E_INT_IRQ_EVD); //evd_int
458 HAL_UpdateIrqTable(E_IRQ_14, E_INT_IRQ_COMB); //comb_int / vbi_int
459 HAL_UpdateIrqTable(E_IRQ_15, E_INT_RESERVED); //Reserved
460
461 HAL_UpdateIrqTable(E_IRQ_16, E_INT_IRQ_TSP2HK); //tsp2hk_int
462 HAL_UpdateIrqTable(E_IRQ_17, E_INT_IRQ_CEC); //cec_int_pm
463 HAL_UpdateIrqTable(E_IRQ_18, E_INT_IRQ_DISP); //disp_int
464 HAL_UpdateIrqTable(E_IRQ_19, E_INT_IRQ_DC); //dc_int
465 HAL_UpdateIrqTable(E_IRQ_20, E_INT_IRQ_GOP); //gop_int
466 HAL_UpdateIrqTable(E_IRQ_21, E_INT_IRQ_SCDC_PM_INT); //scdc_int_pm (*)
467 HAL_UpdateIrqTable(E_IRQ_22, E_INT_IRQ_SMART); //smart card int
468 HAL_UpdateIrqTable(E_IRQ_23, E_INT_IRQ_DDC2BI); //d2b_int
469 HAL_UpdateIrqTable(E_IRQ_24, E_INT_IRQ_AUDMA_V2_INT); //AUDMA_V2_INTR
470 HAL_UpdateIrqTable(E_IRQ_25, E_INT_RESERVED); //Reserved
471 HAL_UpdateIrqTable(E_IRQ_26, E_INT_IRQ_EMMC_OSP_INT); //emmc_osp_int
472 HAL_UpdateIrqTable(E_IRQ_27, E_INT_IRQ_SCM); //scm_int
473 HAL_UpdateIrqTable(E_IRQ_28, E_INT_IRQ_VBI); //vbi_int
474 HAL_UpdateIrqTable(E_IRQ_29, E_INT_IRQ_MVD2MIPS); //mvd2mips_int
475 HAL_UpdateIrqTable(E_IRQ_30, E_INT_IRQ_GPD); //gpd_int
476 HAL_UpdateIrqTable(E_IRQ_31, E_INT_IRQ_ADCDVI2RIU); //adcdvi2riu_int
477
478 HAL_UpdateIrqTable(E_IRQ_32, E_INT_IRQ_SVD_HVD); //hvd_int
479 HAL_UpdateIrqTable(E_IRQ_33, E_INT_IRQ_USB1); //usb_int1
480 HAL_UpdateIrqTable(E_IRQ_34, E_INT_IRQ_UHC1); //uhc_int1
481 HAL_UpdateIrqTable(E_IRQ_35, E_INT_IRQ_ERROR_RESP); //error_resp_int
482 HAL_UpdateIrqTable(E_IRQ_36, E_INT_IRQ_USB2); //usb_int2
483 HAL_UpdateIrqTable(E_IRQ_37, E_INT_IRQ_UHC2); //uhc_int2
484 HAL_UpdateIrqTable(E_IRQ_38, E_INT_RESERVED); //Reserved
485 HAL_UpdateIrqTable(E_IRQ_39, E_INT_IRQ_UART1); //int_uart1
486 HAL_UpdateIrqTable(E_IRQ_40, E_INT_RESERVED); //Reserved
487 HAL_UpdateIrqTable(E_IRQ_41, E_INT_IRQ_MSPI1); //mspi1_int
488 HAL_UpdateIrqTable(E_IRQ_42, E_INT_IRQ_MIU_SECURITY); //miu_security_int
489 HAL_UpdateIrqTable(E_IRQ_43, E_INT_IRQ_DIPW); //dipw_INT
490 HAL_UpdateIrqTable(E_IRQ_44, E_INT_IRQ_MIIC_INT2); //miic2_int
491 HAL_UpdateIrqTable(E_IRQ_45, E_INT_IRQ_JPD); //jpd_int
492 HAL_UpdateIrqTable(E_IRQ_46, E_INT_RESERVED); //pm_irq_out (*)
493 HAL_UpdateIrqTable(E_IRQ_47, E_INT_IRQ_MFE); //mfe_int
494
495 HAL_UpdateIrqTable(E_IRQ_48, E_INT_IRQ_BDMA); //int_bdma_merge
496 HAL_UpdateIrqTable(E_IRQ_49, E_INT_IRQ_PAS_PTS_COMBINE_INT); //PAS_PTS_INTRL_COMBINE
497 HAL_UpdateIrqTable(E_IRQ_50, E_INT_IRQ_UART2MCU); //uart2mcu_intr
498 HAL_UpdateIrqTable(E_IRQ_51, E_INT_IRQ_URDMA2MCU); //urdma2mcu_intr
499 HAL_UpdateIrqTable(E_IRQ_52, E_INT_IRQ_DVI_HDMI_HDCP); //dvi_hdmi_hdcp_int
500 HAL_UpdateIrqTable(E_IRQ_53, E_INT_IRQ_G3D2MCU); //g3d2mcu_irq_dft
501 HAL_UpdateIrqTable(E_IRQ_54, E_INT_IRQ_PCM); //pcm2mcu_int
502 HAL_UpdateIrqTable(E_IRQ_55, E_INT_RESERVED); //Reserved
503 HAL_UpdateIrqTable(E_IRQ_56, E_INT_IRQ_HDCP_X74); //hdcp_x74_int
504 HAL_UpdateIrqTable(E_IRQ_57, E_INT_IRQ_WADR_ERR); //wadr_err_int
505 HAL_UpdateIrqTable(E_IRQ_58, E_INT_RESERVED); //Reserved
506 HAL_UpdateIrqTable(E_IRQ_59, E_INT_IRQ_SDIO); //sdio_int
507 HAL_UpdateIrqTable(E_IRQ_60, E_INT_RESERVED); //Reserved
508 HAL_UpdateIrqTable(E_IRQ_61, E_INT_IRQ_MIIC_DMA1); //miic1_dma_int
509 HAL_UpdateIrqTable(E_IRQ_62, E_INT_RESERVED); //Reserved
510 HAL_UpdateIrqTable(E_IRQ_63, E_INT_IRQ_MIIC_DMA0); //miic0_dma_int
511
512 HAL_UpdateIrqTable(E_FIQ_00, E_INT_FIQ_EXTIMER0); //int_timer0
513 HAL_UpdateIrqTable(E_FIQ_01, E_INT_FIQ_EXTIMER1); //int_timer1
514 HAL_UpdateIrqTable(E_FIQ_02, E_INT_FIQ_WDT); //int_wdt
515 HAL_UpdateIrqTable(E_FIQ_03, E_INT_RESERVED); //Reserved
516 HAL_UpdateIrqTable(E_FIQ_04, E_INT_FIQ_AU_SPDIF_TX_CS0);//AU_SPDIF_TX_CS_INT[0]
517 HAL_UpdateIrqTable(E_FIQ_05, E_INT_FIQ_AU_SPDIF_TX_CS1);//AU_SPDIF_TX_CS_INT[1]
518 HAL_UpdateIrqTable(E_FIQ_06, E_INT_FIQ_DSPTOMCU_INT0); //MB_DSP2toMCU_INT[0]
519 HAL_UpdateIrqTable(E_FIQ_07, E_INT_FIQ_DSPTOMCU_INT1); //MB_DSP2toMCU_INT[1]
520 HAL_UpdateIrqTable(E_FIQ_08, E_INT_FIQ_USB); //usb_int
521 HAL_UpdateIrqTable(E_FIQ_09, E_INT_FIQ_UHC); //uhc_int
522 HAL_UpdateIrqTable(E_FIQ_10, E_INT_RESERVED); //Reserved
523 HAL_UpdateIrqTable(E_FIQ_11, E_INT_FIQ_HDMI_NON_PCM); //HDMI_NON_PCM_MODE_INT_OUT
524 HAL_UpdateIrqTable(E_FIQ_12, E_INT_FIQ_SPDIF_IN_NON_PCM);//SPDIF_IN_NON_PCM_INT_OUT
525 HAL_UpdateIrqTable(E_FIQ_13, E_INT_FIQ_EMAC); //lan_esd_int
526 HAL_UpdateIrqTable(E_FIQ_14, E_INT_FIQ_SE_DSP2UP); //SE_DSP2UP_intr
527 HAL_UpdateIrqTable(E_FIQ_15, E_INT_FIQ_TSP2AEON); //tsp2aeon_int
528
529 HAL_UpdateIrqTable(E_FIQ_16, E_INT_FIQ_VIVALDI_STR); //vivaldi_str_intr
530 HAL_UpdateIrqTable(E_FIQ_17, E_INT_FIQ_VIVALDI_PTS); //vivaldi_pts_intr
531 HAL_UpdateIrqTable(E_FIQ_18, E_INT_FIQ_DSP_MIU_PROT); //DSP_MIU_PROT_intr
532 HAL_UpdateIrqTable(E_FIQ_19, E_INT_FIQ_XIU_TIMEOUT); //xiu_timeout_int
533 HAL_UpdateIrqTable(E_FIQ_20, E_INT_FIQ_DMDMCU2HK); //dmdmcu2hk_int
534 HAL_UpdateIrqTable(E_FIQ_21, E_INT_FIQ_IR_IN); //ir_in
535 HAL_UpdateIrqTable(E_FIQ_22, E_INT_RESERVED); //Reserved
536 HAL_UpdateIrqTable(E_FIQ_23, E_INT_FIQ_VDMCU2HK); //vdmcu2hk_int
537 HAL_UpdateIrqTable(E_FIQ_24, E_INT_FIQ_LDM_DMA0); //ldm_dma_done_int0
538 HAL_UpdateIrqTable(E_FIQ_25, E_INT_FIQ_LDM_DMA1); //ldm_dma_done_int1
539 HAL_UpdateIrqTable(E_FIQ_26, E_INT_FIQ_PM_SD_CDZ0); //PM_SD_CDZ_int
540 HAL_UpdateIrqTable(E_FIQ_27, E_INT_RESERVED); //Reserved
541 HAL_UpdateIrqTable(E_FIQ_28, E_INT_FIQ_AFEC_VSYNC); //AFEC_VSYNC
542 HAL_UpdateIrqTable(E_FIQ_29, E_INT_RESERVED); //Reserved
543 HAL_UpdateIrqTable(E_FIQ_30, E_INT_RESERVED); //Reserved
544 HAL_UpdateIrqTable(E_FIQ_31, E_INT_FIQ_DEC_DSP2MIPS); //DSP2MIPS_INT
545
546 HAL_UpdateIrqTable(E_FIQ_32, E_INT_RESERVED); //Reserved
547 HAL_UpdateIrqTable(E_FIQ_33, E_INT_FIQ_AU_DMA_BUF_INT); //AU_DMA_BUFFER_INT_EDGE
548 HAL_UpdateIrqTable(E_FIQ_34, E_INT_FIQ_IR); //ir_int_rc | ir_int
549 HAL_UpdateIrqTable(E_FIQ_35, E_INT_FIQ_PM_SD_CDZ1); //PM_SD_CDZ1_int
550 HAL_UpdateIrqTable(E_FIQ_36, E_INT_FIQ_8051_TO_AEON); //reg_hst0to3_int
551 HAL_UpdateIrqTable(E_FIQ_37, E_INT_FIQ_8051_TO_MIPS_VPE1); //reg_hst0to2_int
552 HAL_UpdateIrqTable(E_FIQ_38, E_INT_FIQ_8051_TO_BEON); //reg_hst0to1_int
553 HAL_UpdateIrqTable(E_FIQ_39, E_INT_FIQ_GPIO0); //ext_gpio_int[0]
554 HAL_UpdateIrqTable(E_FIQ_40, E_INT_FIQ_BEON_TO_AEON); //reg_hst1to3_int
555 HAL_UpdateIrqTable(E_FIQ_41, E_INT_RESERVED); //ca9_SCUEVABORT_INTR (*)
556 HAL_UpdateIrqTable(E_FIQ_42, E_INT_FIQ_BEON_TO_8051); //reg_hst1to0_int
557 HAL_UpdateIrqTable(E_FIQ_43, E_INT_FIQ_GPIO1); //ext_gpio_int[1]
558 HAL_UpdateIrqTable(E_FIQ_44, E_INT_FIQ_MIPS_VPE1_TO_AEON); //reg_hst2to3_int
559 HAL_UpdateIrqTable(E_FIQ_45, E_INT_IRQ_TIMER2); //int_timer2
560 HAL_UpdateIrqTable(E_FIQ_46, E_INT_FIQ_MIPS_VPE1_TO_8051); //reg_hst2to0_int
561 HAL_UpdateIrqTable(E_FIQ_47, E_INT_FIQ_GPIO2); //ext_gpio_int[2]
562
563 HAL_UpdateIrqTable(E_FIQ_48, E_INT_FIQ_AEON_TO_MIPS_VPE1); //reg_hst3to2_int
564 HAL_UpdateIrqTable(E_FIQ_49, E_INT_FIQ_AEON_TO_BEON); //reg_hst3to1_int
565 HAL_UpdateIrqTable(E_FIQ_50, E_INT_FIQ_AEON_TO_8051); //reg_hst3to0_int
566 HAL_UpdateIrqTable(E_FIQ_51, E_INT_FIQ_USB1); //usb_int1
567 HAL_UpdateIrqTable(E_FIQ_52, E_INT_FIQ_UHC1); //uhc_int1
568 HAL_UpdateIrqTable(E_FIQ_53, E_INT_FIQ_USB2); //usb_int2
569 HAL_UpdateIrqTable(E_FIQ_54, E_INT_FIQ_UHC2); //uhc_int2
570 HAL_UpdateIrqTable(E_FIQ_55, E_INT_FIQ_GPIO3); //ext_gpio_int[3]
571 HAL_UpdateIrqTable(E_FIQ_56, E_INT_FIQ_GPIO4); //ext_gpio_int[4]
572 HAL_UpdateIrqTable(E_FIQ_57, E_INT_FIQ_GPIO5); //ext_gpio_int[5]
573 HAL_UpdateIrqTable(E_FIQ_58, E_INT_FIQ_GPIO6); //ext_gpio_int[6]
574 HAL_UpdateIrqTable(E_FIQ_59, E_INT_IRQ_PWM_RP_L); //pwm_rp_l_int
575 HAL_UpdateIrqTable(E_FIQ_60, E_INT_IRQ_PWM_FP_L); //pwm_fp_l_int
576 HAL_UpdateIrqTable(E_FIQ_61, E_INT_IRQ_PWM_RP_R); //pwm_rp_r_int
577 HAL_UpdateIrqTable(E_FIQ_62, E_INT_IRQ_PWM_FP_R); //pwm_fp_r_int
578 HAL_UpdateIrqTable(E_FIQ_63, E_INT_FIQ_GPIO7); //ext_gpio_int[7]
579 }
580
581 #ifdef __cplusplus
582 }
583 #endif
584
585 #endif // _HAL_IRQTBL_H_
586
587