Lines Matching refs:E_FIQEXPL_START
237 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START))
238 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START))
239 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START))
241 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_36 - E_FIQEXPL_START))
242 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_37 - E_FIQEXPL_START))
243 #define FIQEXPL_8051_TO_MIPS_VPE0 (0x01 << (E_FIQ_38 - E_FIQEXPL_START))
244 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START))
245 #define FIQEXPL_MIPS_VPE0_TO_AEON (0x01 << (E_FIQ_40 - E_FIQEXPL_START))
246 #define FIQEXPL_MIPS_VPE0_TO_MIPS_VPE1 (0x01 << (E_FIQ_41 - E_FIQEXPL_START))
247 #define FIQEXPL_MIPS_VPE0_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START))
248 #define FIQEXPL_GPIO1 (0x01 << (E_FIQ_43 - E_FIQEXPL_START))
249 #define FIQEXPL_MIPS_VPE1_TO_AEON (0x01 << (E_FIQ_44 - E_FIQEXPL_START))
250 #define FIQEXPL_MIPS_VPE1_TO_MIPS_VPE0 (0x01 << (E_FIQ_45 - E_FIQEXPL_START))
251 #define FIQEXPL_MIPS_VPE1_TO_8051 (0x01 << (E_FIQ_46 - E_FIQEXPL_START))
252 #define FIQEXPL_GPIO2 (0x01 << (E_FIQ_47 - E_FIQEXPL_START))