1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regSystem.h 98 /// @brief System Chip Top Registers Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_SYSTEM_H_ 103 #define _REG_SYSTEM_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 115 #define REG_TOP_BASE 0xBF803C00 116 // Register access 117 #define TOP_READ(addr) READ_WORD(REG_TOP_BASE + ((addr)<<2)) 118 #define TOP_WRITE(addr, val) WRITE_WORD((REG_TOP_BASE + ((addr)<<2)), (val)) 119 // Register access utility 120 #define TOP_OR(addr, val) TOP_WRITE(addr, TOP_READ(addr) | (val)) 121 #define TOP_AND(addr, val) TOP_WRITE(addr, TOP_READ(addr) & (val)) 122 #define TOP_XOR(addr, val) TOP_WRITE(addr, TOP_READ(addr) ^ (val)) 123 124 #define REG_TOP_DEVICE_ID 0x0066 125 #define REG_TOP_CHIP_VERSION 0x0067 126 #define CHIP_VERSION_SHFT 0 127 #define CHIP_VERSION_MASK BMASK(7:0) 128 #define CHIP_REVISION_SHFT 8 129 #define CHIP_REVISION_MASK BMASK(15:8) 130 131 #ifdef MCU_AEON 132 #define REG_IRQ_BASE 0xA0200000+(0x0c80<<2) // 0xBF805600 133 134 #define REG_FIQ_MASK_L 0x0024 135 #define REG_FIQ_MASK_H 0x0025 136 #define REG_FIQEXP_MASK_L 0x0026 137 #define REG_FIQEXP_MASK_H 0x0027 138 #define REG_FIQ_CLEAR_L 0x002c 139 #define REG_FIQ_CLEAR_H 0x002d 140 #define REG_FIQEXP_CLEAR_L 0x002e 141 #define REG_FIQEXP_CLEAR_H 0x002f 142 #define REG_FIQ_PENDING_L 0x002c 143 #define REG_FIQ_PENDING_H 0x002d 144 #define REG_FIQEXP_PENDING_L 0x002e 145 #define REG_FIQEXP_PENDING_H 0x002f 146 147 #define REG_IRQ_MASK_L 0x0034 148 #define REG_IRQ_MASK_H 0x0035 149 #define REG_IRQEXP_MASK_L 0x0036 150 #define REG_IRQEXP_MASK_H 0x0037 151 #define REG_IRQ_PENDING_L 0x003c 152 #define REG_IRQ_PENDING_H 0x003d 153 #define REG_IRQEXP_PENDING_L 0x003e 154 #define REG_IRQEXP_PENDING_H 0x003f 155 #else 156 // for MIPS VPE 0 157 #define REG_IRQ_BASE 0xBF200000+(0x0c80<<2) // 0xBF800A80 158 159 #define REG_FIQ_MASK_L 0x0024 160 #define REG_FIQ_MASK_H 0x0025 161 #define REG_FIQEXP_MASK_L 0x0026 162 #define REG_FIQEXP_MASK_H 0x0027 163 #define REG_FIQ_CLEAR_L 0x002c 164 #define REG_FIQ_CLEAR_H 0x002d 165 #define REG_FIQEXP_CLEAR_L 0x002e 166 #define REG_FIQEXP_CLEAR_H 0x002f 167 #define REG_FIQ_PENDING_L 0x002c 168 #define REG_FIQ_PENDING_H 0x002d 169 #define REG_FIQEXP_PENDING_L 0x002e 170 #define REG_FIQEXP_PENDING_H 0x002f 171 172 #define REG_IRQ_MASK_L 0x0034 173 #define REG_IRQ_MASK_H 0x0035 174 #define REG_IRQEXP_MASK_L 0x0036 175 #define REG_IRQEXP_MASK_H 0x0037 176 #define REG_IRQ_PENDING_L 0x003c 177 #define REG_IRQ_PENDING_H 0x003d 178 #define REG_IRQEXP_PENDING_L 0x003e 179 #define REG_IRQEXP_PENDING_H 0x003f 180 #endif 181 182 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr)<<2)))) 183 184 // REG_FIQ_MASK_L 185 //FIQ Low 16 bits 186 #define FIQL_MASK 0xFFFF 187 #define FIQ_EXTIMER0 (0x1 << (E_FIQ_EXTIMER0 - E_FIQL_START) ) 188 #define FIQ_EXTIMER1 (0x1 << (E_FIQ_EXTIMER1 - E_FIQL_START) ) 189 #define FIQ_WDT (0x1 << (E_FIQ_WDT - E_FIQL_START) ) 190 #define FIQ_MB_auR2toMCU_INT0 (0x1 << (E_FIQ_AEON_MB2_MCU0 - E_FIQL_START) ) 191 #define FIQ_MB_auR2toMCU_INT1 (0x1 << (E_FIQ_AEON_MB2_MCU1 - E_FIQL_START) ) 192 #define FIQ_MB_DSP2toMCU_INT0 (0x1 << (E_FIQ_DSP2_MB2_MCU0 - E_FIQL_START) ) 193 #define FIQ_MB_DSP2toMCU_INT1 (0x1 << (E_FIQ_DSP2_MB2_MCU1 - E_FIQL_START) ) 194 #define FIQ_USB_INT (0x1 << (E_FIQ_USB - E_FIQL_START) ) 195 #define FIQ_UHC_INT (0x1 << (E_FIQ_UHC - E_FIQL_START) ) 196 #define FIQ_HDMI_NON_PCM (0x1 << (E_FIQ_HDMI_NON_PCM - E_FIQL_START) ) 197 #define FIQ_SPDIF_IN_NON_PCM (0x1 << (E_FIQ_SPDIF_IN_NON_PCM - E_FIQL_START) ) 198 #define FIQ_EMAC (0x1 << (E_FIQ_EMAC - E_FIQL_START) ) 199 #define FIQ_SE_DSP2UP (0x1 << (E_FIQ_SE_DSP2UP - E_FIQL_START) ) 200 #define FIQ_TSP2AEON (0x1 << (E_FIQ_TSP2AEON - E_FIQL_START) ) 201 202 203 // REG_FIQ_MASK_H 204 //FIQ High 16 bits 205 #define FIQH_MASK 0xFFFF 206 #define FIQ_VIVALDI_STR (0x1 << (E_FIQ_VIVALDI_STR - E_FIQH_START) ) 207 #define FIQ_VIVALDI_PTS (0x1 << (E_FIQ_VIVALDI_PTS - E_FIQH_START) ) 208 #define FIQ_DSP_MIU_PROT (0x1 << (E_FIQ_DSP_MIU_PROT - E_FIQH_START) ) 209 #define FIQ_XIU_TIMEOUT (0x1 << (E_FIQ_XIU_TIMEOUT - E_FIQH_START) ) 210 #define FIQ_DMDMCU2HK (0x1 << (E_FIQ_DMDMCU2HK - E_FIQH_START) ) 211 #define FIQ_VSYNC_VE4VBI (0x1 << (E_FIQ_VSYNC_VE4VBI - E_FIQH_START) ) 212 #define FIQ_FIELD_VE4VBI (0x1 << (E_FIQ_FIELD_VE4VBI - E_FIQH_START) ) 213 #define FIQ_VDMCU2HK (0x1 << (E_FIQ_VDMCU2HK - E_FIQH_START) ) 214 #define FIQ_VE_DONE_TT (0x1 << (E_FIQ_VE_DONE_TT - E_FIQH_START) ) 215 #define FIQ_INT_CCFL (0x1 << (E_FIQ_INT_CCFL - E_FIQH_START) ) 216 #define FIQ_INT (0x1 << (E_FIQ_INT - E_FIQH_START) ) 217 #define FIQ_IR (0x1 << (E_FIQ_IR - E_FIQH_START) ) 218 #define FIQ_AFEC_VSYNC (0x1 << (E_FIQ_AFEC_VSYNC - E_FIQH_START) ) 219 #define FIQ_DEC_DSP2UP (0x1 << (E_FIQ_DEC_DSP2UP - E_FIQH_START) ) 220 #define FIQ_FRC_R2_TO_MIPS (0x1 << (E_FIQ_FRC_R2_TO_MIPS - E_FIQH_START) ) 221 #define FIQ_DSP2MIPS (0x1 << (E_FIQ_DSP2MIPS - E_FIQH_START) ) 222 223 // #define REG_IRQ_PENDING_L 224 #define IRQ_UART0 (0x1 << (E_IRQ_UART0 - E_IRQL_START) ) 225 #define IRQ_PM_SLEEP (0x1 << (E_IRQ_PM_SLEEP - E_IRQL_START) ) 226 #define IRQ_ONIF (0x1 << (E_IRQ_ONIF - E_IRQL_START) ) 227 #define IRQ_MVD (0x1 << (E_IRQ_MVD - E_IRQL_START) ) 228 #define IRQ_PS (0x1 << (E_IRQ_PS - E_IRQL_START) ) 229 #define IRQ_NFIE (0x1 << (E_IRQ_NFIE - E_IRQL_START) ) 230 #define IRQ_USB (0x1 << (E_IRQ_USB - E_IRQL_START) ) 231 #define IRQ_UHC (0x1 << (E_IRQ_UHC - E_IRQL_START) ) 232 #define IRQ_EC_BRIDGE (0x1 << (E_IRQ_EC_BRIDGE - E_IRQL_START) ) 233 #define IRQ_EMAC (0x1 << (E_IRQ_EMAC - E_IRQL_START) ) 234 #define IRQ_DISP (0x1 << (E_IRQ_DISP - E_IRQL_START) ) 235 #define IRQ_FRC_SC (0x1 << (E_IRQ_FRC_SC - E_IRQL_START) ) 236 #define IRQ_IIC_DMA_INT3 (0x1 << (E_IRQ_MIIC_DMA_INT3 - E_IRQL_START) ) 237 #define IRQ_MIIC_INT3 (0x1 << (E_IRQ_MIIC_INT3 - E_IRQL_START) ) 238 #define IRQ_COMB (0x1 << (E_IRQ_COMB - E_IRQL_START) ) 239 #define IRQ_FRC_INT_FIQ2HST0 (0x1 << (E_IRQ_FRC_INT_FIQ2HST0 - E_IRQL_START) ) 240 241 242 // #define REG_IRQ_PENDING_H 243 #define IRQH_MASK 0xFFFF 244 #define IRQ_TSP2HK (0x1 << (E_IRQ_TSP2HK - E_IRQH_START) ) 245 #define IRQ_VE (0x1 << (E_IRQ_VE - E_IRQH_START) ) 246 #define IRQ_CIMAX2MCU (0x1 << (E_IRQ_CIMAX2MCU - E_IRQH_START) ) 247 #define IRQ_DC (0x1 << (E_IRQ_DC - E_IRQH_START) ) 248 #define IRQ_GOP (0x1 << (E_IRQ_GOP - E_IRQH_START) ) 249 #define IRQ_PCM (0x1 << (E_IRQ_PCM - E_IRQH_START) ) 250 #define IRQ_IIC0 (0x1 << (E_IRQ_IIC0 - E_IRQH_START) ) 251 #define IRQ_SMART (0x1 << (E_IRQ_SMART - E_IRQH_START) ) 252 #define IRQ_DDC2BI (0x1 << (E_IRQ_DDC2BI - E_IRQH_START) ) 253 #define IRQ_SCM (0x1 << (E_IRQ_SCM - E_IRQH_START) ) 254 #define IRQ_VBI (0x1 << (E_IRQ_VBI - E_IRQH_START) ) //#define IRQ_MLINK (0x1 << (E_IRQ_MLINK - E_IRQH_START) ) 255 #define IRQ_MVD2MIPS (0x1 << (E_IRQ_MVD2MIPS - E_IRQH_START) ) 256 #define IRQ_GPD (0x1 << (E_IRQ_GPD - E_IRQH_START) ) 257 #define IRQ_ADCDVI2RIU (0x1 << (E_IRQ_ADCDVI2RIU - E_IRQH_START) ) 258 259 // 260 #define IRQEXPL_MASK 0xFFFF 261 #define IRQEXPL_HVD (0x1 << (E_IRQEXPL_HVD - E_IRQEXPL_START) ) 262 #define IRQEXPL_USB1 (0x1 << (E_IRQEXPL_USB1 - E_IRQEXPL_START) ) 263 #define IRQEXPL_UHC1 (0x1 << (E_IRQEXPL_UHC1 - E_IRQEXPL_START) ) 264 #define IRQEXPL_MIU (0x1 << (E_IRQEXPL_MIU - E_IRQEXPL_START) ) 265 #define IRQEXPL_USB2 (0x1 << (E_IRQEXPL_USB2 - E_IRQEXPL_START) ) 266 #define IRQEXPL_UHC2 (0x1 << (E_IRQEXPL_UHC2 - E_IRQEXPL_START) ) 267 #define IRQEXPL_AEON2HI (0x1 << (E_IRQEXPL_AEON2HI - E_IRQEXPL_START) ) 268 #define IRQEXPL_UART1 (0x1 << (E_IRQEXPL_UART1 - E_IRQEXPL_START) ) 269 #define IRQEXPL_UART2 (0x1 << (E_IRQEXPL_UART2 - E_IRQEXPL_START) ) 270 #define IRQEXPL_FRC_INT_IRQ2HST0 (0x1 << (E_IRQEXPL_FRC_INT_IRQ2HST0 - E_IRQEXPL_START) ) 271 #define IRQEXPL_MPIF (0x1 << (E_IRQEXPL_MPIF - E_IRQEXPL_START) ) 272 #define IRQ_IIC_DMA_INT2 (0x1 << (E_IRQEXPL_MIIC_DMA_INT2 - E_IRQEXPL_START) ) 273 #define IRQ_MIIC_INT2 (0x1 << (E_IRQEXPL_MIIC_INT2 - E_IRQEXPL_START) ) 274 #define IRQEXPL_JPD (0x1 << (E_IRQEXPL_JPD - E_IRQEXPL_START) ) 275 #define IRQEXPL_DISPI (0x1 << (E_IRQEXPL_DISPI - E_IRQEXPL_START) ) 276 #define IRQEXPL_MFE (0x1 << (E_IRQEXPL_MFE - E_IRQEXPL_START) ) 277 278 #define IRQEXPH_MASK 0xFFFF 279 #define IRQEXPH_BDMA0 (0x1 << (E_IRQEXPH_BDMA0 - E_IRQEXPH_START) ) 280 #define IRQEXPH_BDMA1 (0x1 << (E_IRQEXPH_BDMA1 - E_IRQEXPH_START) ) 281 #define IRQEXPH_UART2MCU (0x1 << (E_IRQEXPH_UART2MCU - E_IRQEXPH_START) ) 282 #define IRQEXPH_URDMA2MCU (0x1 << (E_IRQEXPH_URDMA2MCU - E_IRQEXPH_START) ) 283 #define IRQEXPH_DVI_HDMI_HDCP (0x1 << (E_IRQEXPH_DVI_HDMI_HDCP - E_IRQEXPH_START) ) 284 #define IRQEXPH_G3D2MCU (0x1 << (E_IRQEXPH_G3D2MCU - E_IRQEXPH_START) ) 285 #define IRQEXPH_CEC_INT_PM (0x1 << (E_IRQEXPH_CEC - E_IRQEXPH_START) ) 286 #define IRQEXPH_HDCP_IIC (0x1 << (E_IRQEXPH_HDCP_IIC - E_IRQEXPH_START) ) 287 #define IRQEXPH_HDCP_X74 (0x1 << (E_IRQEXPH_HDCP_X74 - E_IRQEXPH_START) ) 288 #define IRQEXPH_WADR_ERR (0x1 << (E_IRQEXPH_WADR_ERR - E_IRQEXPH_START) ) 289 #define IRQEXPH_DCSUB (0x1 << (E_IRQEXPH_DCSUB - E_IRQEXPH_START) ) 290 #define IRQEXPH_GE (0x1 << (E_IRQEXPH_GE - E_IRQEXPH_START) ) 291 #define IRQEXPH_MIIC_DMA_INT1 (0x1 << (E_IRQEXPH_MIIC_DMA_INT1 - E_IRQEXPH_START) ) 292 #define IRQEXPH_MIIC_INT1 (0x1 << (E_IRQEXPH_MIIC_INT1 - E_IRQEXPH_START) ) 293 #define IRQEXPH_MIIC_DMA_INT0 (0x1 << (E_IRQEXPH_MIIC_DMA_INT0 - E_IRQEXPH_START) ) 294 #define IRQEXPH_MIIC_INT0 (0x1 << (E_IRQEXPH_MIIC_INT0 - E_IRQEXPH_START) ) 295 296 #define FIQEXPL_MASK 0xFFFF 297 #define FIQEXPL_IR_INT_RC (0x1 << (E_FIQEXPL_IR_INT_RC - E_FIQEXPL_START) ) 298 #define FIQEXPL_AU_DMA_BUF_INT (0x1 << (E_FIQEXPL_AU_DMA_BUF_INT - E_FIQEXPL_START) ) 299 #define FIQEXPL_IR_IN (0x1 << (E_FIQEXPL_IR_IN - E_FIQEXPL_START) ) 300 #define FIQEXPL_8051_TO_MIPS_VPE0 (0x1 << (E_FIQEXPL_8051_TO_MIPS_VPE0 - E_FIQEXPL_START) ) 301 #define FIQEXPL_EXT_GPIO_INT0 (0x1 << (E_FIQEXPL_EXT_GPIO_INT0 - E_FIQEXPL_START) ) 302 #define FIQEXPL_MIPS_VPE0_TO_8051 (0x1 << (E_FIQEXPL_MIPS_VPE1_TO_8051 - E_FIQEXPL_START) ) 303 #define FIQEXPL_EXT_GPIO_INT1 (0x1 << (E_FIQEXPL_EXT_GPIO_INT1 - E_FIQEXPL_START) ) 304 #define FIQEXPL_EXT_GPIO_INT2 (0x1 << (E_FIQEXPL_EXT_GPIO_INT2 - E_FIQEXPL_START) ) 305 306 #define FIQEXPH_MASK 0xFFFF 307 #define FIQEXPH_USB_INT1 (0x1 << (E_FIQEXPH_USB1 - E_FIQEXPH_START) ) 308 #define FIQEXPH_UHC_INT1 (0x1 << (E_FIQEXPH_UHC1 - E_FIQEXPH_START) ) 309 #define FIQEXPH_USB_INT2 (0x1 << (E_FIQEXPH_USB2 - E_FIQEXPH_START) ) 310 #define FIQEXPH_UHC_INT2 (0x1 << (E_FIQEXPH_UHC2 - E_FIQEXPH_START) ) 311 #define FIQEXPH_EXT_GPIO_INT3 (0x1 << (E_FIQEXPH_EXT_GPIO_INT3 - E_FIQEXPH_START) ) 312 #define FIQEXPH_EXT_GPIO_INT4 (0x1 << (E_FIQEXPH_EXT_GPIO_INT4 - E_FIQEXPH_START) ) 313 #define FIQEXPH_EXT_GPIO_INT5 (0x1 << (E_FIQEXPH_EXT_GPIO_INT5 - E_FIQEXPH_START) ) 314 #define FIQEXPH_EXT_GPIO_INT6 (0x1 << (E_FIQEXPH_EXT_GPIO_INT6 - E_FIQEXPH_START) ) 315 #define FIQEXPH_PWM_RP_L (0x1 << (E_FIQEXPH_PWM_RP_L - E_FIQEXPH_START) ) 316 #define FIQEXPH_PWM_FP_L (0x1 << (E_FIQEXPH_PWM_FP_L - E_FIQEXPH_START) ) 317 #define FIQEXPH_PWM_RP_R (0x1 << (E_FIQEXPH_PWM_RP_R - E_FIQEXPH_START) ) 318 #define FIQEXPH_PWM_FP_R (0x1 << (E_FIQEXPH_PWM_FP_R - E_FIQEXPH_START) ) 319 #define FIQEXPH_EXT_GPIO_INT7 (0x1 << (E_FIQEXPH_EXT_GPIO_INT7 - E_FIQEXPH_START) ) 320 321 322 323 //------------------------------------------------------------------------------------------------- 324 // Type and Structure 325 //------------------------------------------------------------------------------------------------- 326 327 #define INTERFACE extern 328 329 INTERFACE MS_U32 u32_ge0_mmio_base; 330 331 332 //extern MS_U32 u32_bdma_mmio_base; 333 //extern MS_U32 u32_scaler_mmio_base; 334 335 //------------------------------------------------------------------------------------------------- 336 // Defines 337 //------------------------------------------------------------------------------------------------- 338 #define REG_GE0_BASE u32_ge0_mmio_base 339 //#define REG_BDMA_BASE u32_bdma_mmio_base 340 //#define REG_SCALER_BASE u32_scaler_mmio_base 341 342 343 //------------------------------------------------------------------------------------------------- 344 345 // Macros 346 347 //------------------------------------------------------------------------------------------------- 348 349 #define MReg_Write2Byte(u32Base, u32Reg, u16Val ) \ 350 do {((volatile MS_U16*)(u32Base))[((u32Reg))] = u16Val;} while(0) 351 352 #define MReg_Read2Byte( u32Base, u32Reg ) \ 353 ((volatile MS_U16*)(u32Base))[((u32Reg) )] 354 355 #define MReg_WriteByte(u32Base, u32Reg, u8Val ) \ 356 do{((volatile MS_U8*)(u32Base))[((u32Reg) * 2) - ((u32Reg) & 1)] = u8Val;} while(0) 357 358 #define MReg_ReadByte( u32Base, u32Reg ) \ 359 ((volatile MS_U8*)(u32Base))[((u32Reg) * 2) - ((u32Reg) & 1)] 360 361 #define MReg_Write3Byte(u32Base, u32Reg, u32Val ) \ 362 do { \ 363 if ((u32Reg) & 0x01) \ 364 { \ 365 MReg_WriteByte(u32Base, u32Reg , u32Val); \ 366 MReg_Write2Byte(u32Base, (u32Reg + 1) , ((u32Val) >> 8)); \ 367 } \ 368 else \ 369 { \ 370 MReg_Write2Byte(u32Base, (u32Reg) , u32Val); \ 371 MReg_WriteByte(u32Base, (u32Reg + 2) , ((u32Val) >> 16)); \ 372 } \ 373 } while(0) 374 375 #define MReg_Write4Byte( u32Base, u32Reg, u32Val ) \ 376 do { \ 377 if ((u32Reg) & 0x01) \ 378 { \ 379 MReg_WriteByte( u32Base, u32Reg , u32Val); \ 380 MReg_Write2Byte( u32Base, (u32Reg + 1) , ( (u32Val) >> 8)); \ 381 MReg_WriteByte( u32Base, (u32Reg + 3) , ((u32Val) >> 24)); \ 382 } \ 383 else \ 384 { \ 385 MReg_Write2Byte(u32Base, u32Reg , u32Val); \ 386 MReg_Write2Byte(u32Base, (u32Reg + 2) , ((u32Val) >> 16)); \ 387 } \ 388 } while(0) 389 390 #define MReg_WriteByteMask(u32Base, u32Reg, u8Val, u8Msk ) \ 391 do { \ 392 MReg_WriteByte( u32Base, u32Reg, (MReg_ReadByte(u32Base, ((u32Reg) )) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 393 } while(0) 394 395 #define MReg_Write2ByteMask( u32Base, u32Reg, u16Val , u16Msk) \ 396 do { \ 397 if ( ((u32Reg) & 0x01) ) \ 398 { \ 399 MReg_WriteByteMask( u32Base, ((u32Reg)+1) , (((u16Val) & 0xff00)>>8) , (((u16Msk)&0xff00)>>8) ); \ 400 MReg_WriteByteMask( u32Base, (u32Reg) , ((u16Val) & 0x00ff) , ((u16Msk)&0x00ff) ); \ 401 } \ 402 else \ 403 { \ 404 MReg_Write2Byte(u32Base, u32Reg , (((u16Val) & (u16Msk)) | (MReg_Read2Byte(u32Base, u32Reg ) & (~( u16Msk )))) ); \ 405 } \ 406 } while(0) 407 408 409 410 #endif // _REG_SYSTEM_H_ 411 412