1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _REG_SYSTEM_H_ 80 #define _REG_SYSTEM_H_ 81 82 //------------------------------------------------------------------------------------------------- 83 // Hardware Capability 84 //------------------------------------------------------------------------------------------------- 85 86 //------------------------------------------------------------------------------------------------- 87 // Macro and Define 88 //------------------------------------------------------------------------------------------------- 89 90 #define REG_TOP_BASE (0x1F000000 + (0x101E00 << 1)) 91 92 //============================================================================= 93 // Register access 94 #define TOP_READ(addr) READ_WORD(REG_TOP_BASE + ((addr) << 2)) 95 #define TOP_WRITE(addr, val) WRITE_WORD((REG_TOP_BASE + ((addr) << 2)), (val)) 96 97 //============================================================================= 98 // Register access utility 99 #define TOP_OR(addr, val) TOP_WRITE(addr, TOP_READ(addr) | (val)) 100 #define TOP_AND(addr, val) TOP_WRITE(addr, TOP_READ(addr) & (val)) 101 #define TOP_XOR(addr, val) TOP_WRITE(addr, TOP_READ(addr) ^ (val)) 102 103 //============================================================================= 104 #define REG_TOP_DEVICE_ID 0x0066 105 #define REG_TOP_CHIP_VERSION 0x0067 106 #define CHIP_VERSION_SHFT 0 107 #define CHIP_VERSION_MASK BMASK(7:0) 108 #define CHIP_REVISION_SHFT 8 109 #define CHIP_REVISION_MASK BMASK(15:8) 110 111 //============================================================================= 112 #ifdef MCU_AEON 113 #define REG_IRQ_BASE 0xA0200000+(0x0c80<<2) // 0xBF805600 114 115 #define REG_FIQ_MASK_L 0x0024 116 #define REG_FIQ_MASK_H 0x0025 117 #define REG_FIQEXP_MASK_L 0x0026 118 #define REG_FIQEXP_MASK_H 0x0027 119 #define REG_FIQ_CLEAR_L 0x002c 120 #define REG_FIQ_CLEAR_H 0x002d 121 #define REG_FIQEXP_CLEAR_L 0x002e 122 #define REG_FIQEXP_CLEAR_H 0x002f 123 #define REG_FIQ_PENDING_L 0x002c 124 #define REG_FIQ_PENDING_H 0x002d 125 #define REG_FIQEXP_PENDING_L 0x002e 126 #define REG_FIQEXP_PENDING_H 0x002f 127 128 #define REG_IRQ_MASK_L 0x0034 129 #define REG_IRQ_MASK_H 0x0035 130 #define REG_IRQEXP_MASK_L 0x0036 131 #define REG_IRQEXP_MASK_H 0x0037 132 #define REG_IRQ_PENDING_L 0x003c 133 #define REG_IRQ_PENDING_H 0x003d 134 #define REG_IRQEXP_PENDING_L 0x003e 135 #define REG_IRQEXP_PENDING_H 0x003f 136 #else 137 #define REG_IRQ_BASE (0xFD000000 + (0x101900 << 1)) 138 #define REG_IRQHYP_BASE (0xFD000000 + (0x101000 << 1)) 139 #define REG_INT_BASE_ADDR 0x0040 140 #endif 141 142 #define REG_FIQ_MASK_L (REG_INT_BASE_ADDR + 0x0004) 143 #define REG_FIQ_MASK_H (REG_INT_BASE_ADDR + 0x0005) 144 #define REG_FIQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0006) 145 #define REG_FIQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0007) 146 147 #define REG_FIQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0004) 148 #define REG_FIQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0005) 149 #define REG_FIQSUP_MASK_L (REG_INT_BASE_ADDR + 0x0006) 150 #define REG_FIQSUP_MASK_H (REG_INT_BASE_ADDR + 0x0007) 151 152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c) 153 #define REG_FIQ_CLEAR_H (REG_INT_BASE_ADDR + 0x000d) 154 #define REG_FIQEXP_CLEAR_L (REG_INT_BASE_ADDR + 0x000e) 155 #define REG_FIQEXP_CLEAR_H (REG_INT_BASE_ADDR + 0x000f) 156 157 #define REG_FIQHYP_CLEAR_L (REG_INT_BASE_ADDR + 0x000c) 158 #define REG_FIQHYP_CLEAR_H (REG_INT_BASE_ADDR + 0x000d) 159 #define REG_FIQSUP_CLEAR_L (REG_INT_BASE_ADDR + 0x000e) 160 #define REG_FIQSUP_CLEAR_H (REG_INT_BASE_ADDR + 0x000f) 161 162 #define REG_FIQ_PENDING_L (REG_INT_BASE_ADDR + 0x000c) 163 #define REG_FIQ_PENDING_H (REG_INT_BASE_ADDR + 0x000d) 164 #define REG_FIQEXP_PENDING_L (REG_INT_BASE_ADDR + 0x000e) 165 #define REG_FIQEXP_PENDING_H (REG_INT_BASE_ADDR + 0x000f) 166 167 #define REG_FIQHYP_PENDING_L (REG_INT_BASE_ADDR + 0x000c) 168 #define REG_FIQHYP_PENDING_H (REG_INT_BASE_ADDR + 0x000d) 169 #define REG_FIQSUP_PENDING_L (REG_INT_BASE_ADDR + 0x000e) 170 #define REG_FIQSUP_PENDING_H (REG_INT_BASE_ADDR + 0x000f) 171 172 #define REG_IRQ_MASK_L (REG_INT_BASE_ADDR + 0x0014) 173 #define REG_IRQ_MASK_H (REG_INT_BASE_ADDR + 0x0015) 174 #define REG_IRQEXP_MASK_L (REG_INT_BASE_ADDR + 0x0016) 175 #define REG_IRQEXP_MASK_H (REG_INT_BASE_ADDR + 0x0017) 176 177 #define REG_IRQHYP_MASK_L (REG_INT_BASE_ADDR + 0x0014) 178 #define REG_IRQHYP_MASK_H (REG_INT_BASE_ADDR + 0x0015) 179 #define REG_IRQSUP_MASK_L (REG_INT_BASE_ADDR + 0x0016) 180 #define REG_IRQSUP_MASK_H (REG_INT_BASE_ADDR + 0x0017) 181 182 #define REG_IRQ_PENDING_L (REG_INT_BASE_ADDR + 0x001c) 183 #define REG_IRQ_PENDING_H (REG_INT_BASE_ADDR + 0x001d) 184 #define REG_IRQEXP_PENDING_L (REG_INT_BASE_ADDR + 0x001e) 185 #define REG_IRQEXP_PENDING_H (REG_INT_BASE_ADDR + 0x001f) 186 187 #define REG_IRQHYP_PENDING_L (REG_INT_BASE_ADDR + 0x001c) 188 #define REG_IRQHYP_PENDING_H (REG_INT_BASE_ADDR + 0x001d) 189 #define REG_IRQSUP_PENDING_L (REG_INT_BASE_ADDR + 0x001e) 190 #define REG_IRQSUP_PENDING_H (REG_INT_BASE_ADDR + 0x001f) 191 192 //============================================================================= 193 #define IRQ_REG(addr) (*((volatile MS_U16*)(REG_IRQ_BASE + ((addr) << 2)))) 194 #define IRQHYP_REG(addr) (*((volatile MS_U16*)(REG_IRQHYP_BASE + ((addr) << 2)))) 195 196 // REG_FIQ_MASK_L 197 //FIQ Low 16 bits 198 #define FIQL_MASK 0xFFFF 199 #define FIQ_EXTIMER0 (0x01 << (E_FIQ_00 - E_FIQL_START)) 200 #define FIQ_EXTIMER1 (0x01 << (E_FIQ_01 - E_FIQL_START)) 201 #define FIQ_WDT (0x01 << (E_FIQ_02 - E_FIQL_START)) 202 // #define FIQ_RESERVED (0x01 << (E_FIQ_03 - E_FIQL_START)) 203 #define FIQ_R2TOMCU_INT0 (0x01 << (E_FIQ_04 - E_FIQL_START)) 204 #define FIQ_R2TOMCU_INT1 (0x01 << (E_FIQ_05 - E_FIQL_START)) 205 #define FIQ_DSPTOMCU_INT0 (0x01 << (E_FIQ_06 - E_FIQL_START)) 206 #define FIQ_DSPTOMCU_INT1 (0x01 << (E_FIQ_07 - E_FIQL_START)) 207 #define FIQ_TEMPERATURE_FLAG_FALL (0x01 << (E_FIQ_08 - E_FIQL_START)) 208 #define FIQ_TEMPERATURE_FLAG_RISE (0x01 << (E_FIQ_09 - E_FIQL_START)) 209 // #define FIQ_RESERVED (0x01 << (E_FIQ_10 - E_FIQL_START)) 210 #define FIQ_HDMI_NON_PCM (0x01 << (E_FIQ_11 - E_FIQL_START)) 211 #define FIQ_SPDIF_IN_NON_PCM (0x01 << (E_FIQ_12 - E_FIQL_START)) 212 #define FIQ_EMAC (0x01 << (E_FIQ_13 - E_FIQL_START)) 213 #define FIQ_SE_DSP2UP (0x01 << (E_FIQ_14 - E_FIQL_START)) 214 #define FIQ_TSP2AEON (0x01 << (E_FIQ_15 - E_FIQL_START)) 215 216 // REG_FIQ_MASK_H 217 //FIQ High 16 bits 218 #define FIQH_MASK 0xFFFF 219 #define FIQ_VIVALDI_STR (0x01 << (E_FIQ_16 - E_FIQH_START)) 220 #define FIQ_VIVALDI_PTS (0x01 << (E_FIQ_17 - E_FIQH_START)) 221 #define FIQ_DSP_MIU_PROT (0x01 << (E_FIQ_18 - E_FIQH_START)) 222 #define FIQ_XIU_TIMEOUT (0x01 << (E_FIQ_19 - E_FIQH_START)) 223 #define FIQ_DMDMCU2HK (0x01 << (E_FIQ_20 - E_FIQH_START)) 224 #define FIQ_VSYNC_VE4VBI (0x01 << (E_FIQ_21 - E_FIQH_START)) 225 #define FIQ_FIELD_VE4VBI (0x01 << (E_FIQ_22 - E_FIQH_START)) 226 #define FIQ_VDMCU2HK (0x01 << (E_FIQ_23 - E_FIQH_START)) 227 #define FIQ_VE_DONE_TT (0x01 << (E_FIQ_24 - E_FIQH_START)) 228 #define FIQ_CMDQ (0x01 << (E_FIQ_25 - E_FIQH_START)) 229 // #define FIQ_RESERVED (0x01 << (E_FIQ_26 - E_FIQH_START)) 230 #define FIQ_IR (0x01 << (E_FIQ_27 - E_FIQH_START)) 231 #define FIQ_AFEC_VSYNC (0x01 << (E_FIQ_28 - E_FIQH_START)) 232 #define FIQ_DEC_DSP2UP (0x01 << (E_FIQ_29 - E_FIQH_START)) 233 // #define FIQ_RESERVED (0x01 << (E_FIQ_30 - E_FIQH_START)) 234 #define FIQ_DSP2MIPS (0x01 << (E_FIQ_31 - E_FIQH_START)) 235 236 #define FIQEXPL_MASK 0xFFFF 237 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START)) 238 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START)) 239 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START)) 240 // #define FIQEXPL_RESERVED (0x01 << (E_FIQ_35 - E_FIQH_START)) 241 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_36 - E_FIQEXPL_START)) 242 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_37 - E_FIQEXPL_START)) 243 #define FIQEXPL_8051_TO_MIPS_VPE0 (0x01 << (E_FIQ_38 - E_FIQEXPL_START)) 244 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START)) 245 #define FIQEXPL_MIPS_VPE0_TO_AEON (0x01 << (E_FIQ_40 - E_FIQEXPL_START)) 246 #define FIQEXPL_MIPS_VPE0_TO_MIPS_VPE1 (0x01 << (E_FIQ_41 - E_FIQEXPL_START)) 247 #define FIQEXPL_MIPS_VPE0_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START)) 248 #define FIQEXPL_GPIO1 (0x01 << (E_FIQ_43 - E_FIQEXPL_START)) 249 #define FIQEXPL_MIPS_VPE1_TO_AEON (0x01 << (E_FIQ_44 - E_FIQEXPL_START)) 250 #define FIQEXPL_MIPS_VPE1_TO_MIPS_VPE0 (0x01 << (E_FIQ_45 - E_FIQEXPL_START)) 251 #define FIQEXPL_MIPS_VPE1_TO_8051 (0x01 << (E_FIQ_46 - E_FIQEXPL_START)) 252 #define FIQEXPL_GPIO2 (0x01 << (E_FIQ_47 - E_FIQEXPL_START)) 253 254 #define FIQEXPH_MASK 0xFFFF 255 #define FIQEXPH_AEON_TO_MIPS_VPE1 (0x01 << (E_FIQ_48 - E_FIQEXPH_START)) 256 #define FIQEXPH_AEON_TO_MIPS_VPE0 (0x01 << (E_FIQ_49 - E_FIQEXPH_START)) 257 #define FIQEXPH_AEON_TO_8051 (0x01 << (E_FIQ_50 - E_FIQEXPH_START)) 258 #define FIQEXPH_AU_SPDIF_TX_CS0 (0x01 << (E_FIQ_51 - E_FIQEXPH_START)) 259 #define FIQEXPH_AU_SPDIF_TX_CS1 (0x01 << (E_FIQ_52 - E_FIQEXPH_START)) 260 #define FIQEXPH_PCM_DMA (0x01 << (E_FIQ_53 - E_FIQEXPH_START)) 261 #define FIQEXPH_U3_DPHY (0x01 << (E_FIQ_54 - E_FIQEXPH_START)) 262 #define FIQEXPH_GPIO3 (0x01 << (E_FIQ_55 - E_FIQEXPH_START)) 263 #define FIQEXPH_GPIO4 (0x01 << (E_FIQ_56 - E_FIQEXPH_START)) 264 #define FIQEXPH_GPIO5 (0x01 << (E_FIQ_57 - E_FIQEXPH_START)) 265 #define FIQEXPH_GPIO6 (0x01 << (E_FIQ_58 - E_FIQEXPH_START)) 266 #define FIQEXPH_PWM_RP_L (0x01 << (E_FIQ_59 - E_FIQEXPH_START)) 267 #define FIQEXPH_PWM_FP_L (0x01 << (E_FIQ_60 - E_FIQEXPH_START)) 268 #define FIQEXPH_PWM_RP_R (0x01 << (E_FIQ_61 - E_FIQEXPH_START)) 269 #define FIQEXPH_PWM_FP_R (0x01 << (E_FIQ_62 - E_FIQEXPH_START)) 270 #define FIQEXPH_GPIO7 (0x01 << (E_FIQ_63 - E_FIQEXPH_START)) 271 272 // #define REG_IRQ_PENDING_L 273 #define IRQL_MASK 0xFFFF 274 #define IRQ_UART0 (0x01 << (E_IRQ_00 - E_IRQL_START)) 275 #define IRQ_PMSLEEP (0x01 << (E_IRQ_01 - E_IRQL_START)) 276 #define IRQ_UHC3 (0x01 << (E_IRQ_02 - E_IRQL_START)) 277 #define IRQ_MVD (0x01 << (E_IRQ_03 - E_IRQL_START)) 278 #define IRQ_PS (0x01 << (E_IRQ_04 - E_IRQL_START)) 279 #define IRQ_NFIE (0x01 << (E_IRQ_05 - E_IRQL_START)) 280 #define IRQ_USB (0x01 << (E_IRQ_06 - E_IRQL_START)) 281 #define IRQ_UHC (0x01 << (E_IRQ_07 - E_IRQL_START)) 282 #define IRQ_AU_DMA (0x01 << (E_IRQ_08 - E_IRQL_START)) 283 #define IRQ_EMAC (0x01 << (E_IRQ_09 - E_IRQL_START)) 284 #define IRQ_DISP (0x01 << (E_IRQ_10 - E_IRQL_START)) 285 #define IRQ_MSPI0 (0x01 << (E_IRQ_11 - E_IRQL_START)) 286 #define IRQ_MIIC_DMA_INT3 (0x01 << (E_IRQ_12 - E_IRQL_START)) 287 #define IRQ_ERROR_RESP (0x01 << (E_IRQ_13 - E_IRQL_START)) 288 #define IRQ_COMB (0x01 << (E_IRQ_14 - E_IRQL_START)) 289 #define IRQ_LDM_DMA0 (0x01 << (E_IRQ_15 - E_IRQL_START)) 290 291 // #define REG_IRQ_PENDING_H 292 #define IRQH_MASK 0xFFFF 293 #define IRQ_TSP2HK (0x01 << (E_IRQ_16 - E_IRQH_START)) 294 #define IRQ_VE (0x01 << (E_IRQ_17 - E_IRQH_START)) 295 #define IRQ_CIMAX2MCU (0x01 << (E_IRQ_18 - E_IRQH_START)) 296 #define IRQ_DC (0x01 << (E_IRQ_19 - E_IRQH_START)) 297 #define IRQ_GOP (0x01 << (E_IRQ_20 - E_IRQH_START)) 298 #define IRQ_PCM (0x01 << (E_IRQ_21 - E_IRQH_START)) 299 #define IRQ_LDM_DMA1 (0x01 << (E_IRQ_22 - E_IRQH_START)) 300 #define IRQ_SMART (0x01 << (E_IRQ_23 - E_IRQH_START)) 301 #define IRQ_MHL_CBUS_PM (0x01 << (E_IRQ_24 - E_IRQH_START)) 302 // #define IRQ_RESERVED (0x01 << (E_IRQ_25 - E_IRQH_START)) 303 #define IRQ_DDC2BI (0x01 << (E_IRQ_26 - E_IRQH_START)) 304 #define IRQ_SCM (0x01 << (E_IRQ_27 - E_IRQH_START)) 305 #define IRQ_VBI (0x01 << (E_IRQ_28 - E_IRQH_START)) 306 #define IRQ_MVD2MIPS (0x01 << (E_IRQ_29 - E_IRQH_START)) 307 #define IRQ_GPD (0x01 << (E_IRQ_30 - E_IRQH_START)) 308 #define IRQ_ADCDVI2RIU (0x01 << (E_IRQ_31 - E_IRQH_START)) 309 310 #define IRQEXPL_MASK 0xFFFF 311 #define IRQEXPL_HVD (0x01 << (E_IRQ_32 - E_IRQEXPL_START)) 312 #define IRQEXPL_USB1 (0x01 << (E_IRQ_33 - E_IRQEXPL_START)) 313 #define IRQEXPL_UHC1 (0x01 << (E_IRQ_34 - E_IRQEXPL_START)) 314 #define IRQEXPL_MIU (0x01 << (E_IRQ_35 - E_IRQEXPL_START)) 315 #define IRQEXPL_USB2 (0x01 << (E_IRQ_36 - E_IRQEXPL_START)) 316 #define IRQEXPL_UHC2 (0x01 << (E_IRQ_37 - E_IRQEXPL_START)) 317 #define IRQEXPL_AEON2HI (0x01 << (E_IRQ_38 - E_IRQEXPL_START)) 318 #define IRQEXPL_UART1 (0x01 << (E_IRQ_39 - E_IRQEXPL_START)) 319 #define IRQEXPL_UART2 (0x01 << (E_IRQ_40 - E_IRQEXPL_START)) 320 #define IRQEXPL_MSPI1 (0x01 << (E_IRQ_41 - E_IRQEXPL_START)) 321 #define IRQEXPL_MIU_SECURITY (0x01 << (E_IRQ_42 - E_IRQEXPL_START)) 322 #define IRQEXPL_MIIC_DMA_INT2 (0x01 << (E_IRQ_43 - E_IRQEXPL_START)) 323 #define IRQEXPL_MIIC_INT2 (0x01 << (E_IRQ_44 - E_IRQEXPL_START)) 324 #define IRQEXPL_JPD (0x01 << (E_IRQ_45 - E_IRQEXPL_START)) 325 #define IRQEXPL_PM (0x01 << (E_IRQ_46 - E_IRQEXPL_START)) 326 #define IRQEXPL_MFE (0x01 << (E_IRQ_47 - E_IRQEXPL_START)) 327 328 #define IRQEXPH_MASK 0xFFFF 329 #define IRQEXPH_BDMA0 (0x01 << (E_IRQ_48 - E_IRQEXPH_START)) 330 #define IRQEXPH_BDMA1 (0x01 << (E_IRQ_49 - E_IRQEXPH_START)) 331 #define IRQEXPH_UART2MCU (0x01 << (E_IRQ_50 - E_IRQEXPH_START)) 332 #define IRQEXPH_URDMA2MCU (0x01 << (E_IRQ_51 - E_IRQEXPH_START)) 333 #define IRQEXPH_DVI_HDMI_HDCP (0x01 << (E_IRQ_52 - E_IRQEXPH_START)) 334 #define IRQEXPH_G3D2MCU (0x01 << (E_IRQ_53 - E_IRQEXPH_START)) 335 #define IRQEXPH_CEC (0x01 << (E_IRQ_54 - E_IRQEXPH_START)) 336 #define IRQEXPH_HDCP_IIC (0x01 << (E_IRQ_55 - E_IRQEXPH_START)) 337 #define IRQEXPH_HDCP_X74 (0x01 << (E_IRQ_56 - E_IRQEXPH_START)) 338 #define IRQEXPH_WADR_ERR (0x01 << (E_IRQ_57 - E_IRQEXPH_START)) 339 #define IRQEXPH_DCSUB (0x01 << (E_IRQ_58 - E_IRQEXPH_START)) 340 #define IRQEXPH_GE (0x01 << (E_IRQ_59 - E_IRQEXPH_START)) 341 #define IRQEXPH_MIIC_DMA1 (0x01 << (E_IRQ_60 - E_IRQEXPH_START)) 342 #define IRQEXPH_MIIC_INT1 (0x01 << (E_IRQ_61 - E_IRQEXPH_START)) 343 #define IRQEXPH_MIIC_DMA0 (0x01 << (E_IRQ_62 - E_IRQEXPH_START)) 344 #define IRQEXPH_MIIC_INT0 (0x01 << (E_IRQ_63 - E_IRQEXPH_START)) 345 346 //------------------------------------------------------------------------------------------------- 347 // Type and Structure 348 //------------------------------------------------------------------------------------------------- 349 #define INTERFACE extern 350 351 INTERFACE MS_U32 u32_ge0_mmio_base; 352 //extern MS_U32 u32_bdma_mmio_base; 353 //extern MS_U32 u32_scaler_mmio_base; 354 355 //------------------------------------------------------------------------------------------------- 356 // Defines 357 //------------------------------------------------------------------------------------------------- 358 #define REG_GE0_BASE u32_ge0_mmio_base 359 //#define REG_BDMA_BASE u32_bdma_mmio_base 360 //#define REG_SCALER_BASE u32_scaler_mmio_base 361 362 //------------------------------------------------------------------------------------------------- 363 364 // Macros 365 366 //------------------------------------------------------------------------------------------------- 367 368 #define MReg_Write2Byte(u32Base, u32Reg, u16Val) \ 369 do {((volatile MS_U16*)(u32Base))[((u32Reg))] = u16Val;} while(0) 370 371 #define MReg_Read2Byte(u32Base, u32Reg) \ 372 ((volatile MS_U16*)(u32Base))[((u32Reg))] 373 374 #define MReg_WriteByte(u32Base, u32Reg, u8Val) \ 375 do{((volatile MS_U8*)(u32Base))[((u32Reg) * 2) - ((u32Reg) & 1)] = u8Val;} while(0) 376 377 #define MReg_ReadByte(u32Base, u32Reg) \ 378 ((volatile MS_U8*)(u32Base))[((u32Reg) * 2) - ((u32Reg) & 1)] 379 380 #define MReg_Write3Byte(u32Base, u32Reg, u32Val) \ 381 do { \ 382 if ((u32Reg) & 0x01) \ 383 { \ 384 MReg_WriteByte(u32Base, u32Reg , u32Val); \ 385 MReg_Write2Byte(u32Base, (u32Reg + 1), ((u32Val) >> 8)); \ 386 } \ 387 else \ 388 { \ 389 MReg_Write2Byte(u32Base, (u32Reg), u32Val); \ 390 MReg_WriteByte(u32Base, (u32Reg + 2), ((u32Val) >> 16)); \ 391 } \ 392 } while(0) 393 394 #define MReg_Write4Byte(u32Base, u32Reg, u32Val) \ 395 do { \ 396 if ((u32Reg) & 0x01) \ 397 { \ 398 MReg_WriteByte(u32Base, u32Reg, u32Val); \ 399 MReg_Write2Byte(u32Base, (u32Reg + 1), ((u32Val) >> 8)); \ 400 MReg_WriteByte(u32Base, (u32Reg + 3), ((u32Val) >> 24)); \ 401 } \ 402 else \ 403 { \ 404 MReg_Write2Byte(u32Base, u32Reg, u32Val); \ 405 MReg_Write2Byte(u32Base, (u32Reg + 2), ((u32Val) >> 16)); \ 406 } \ 407 } while(0) 408 409 #define MReg_WriteByteMask(u32Base, u32Reg, u8Val, u8Msk) \ 410 do { \ 411 MReg_WriteByte(u32Base, u32Reg, (MReg_ReadByte(u32Base, ((u32Reg))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 412 } while(0) 413 414 #define MReg_Write2ByteMask(u32Base, u32Reg, u16Val, u16Msk) \ 415 do { \ 416 if (((u32Reg) & 0x01)) \ 417 { \ 418 MReg_WriteByteMask( u32Base, ((u32Reg) + 1) , (((u16Val) & 0xff00) >> 8) , (((u16Msk) & 0xff00) >> 8) ); \ 419 MReg_WriteByteMask( u32Base, (u32Reg) , ((u16Val) & 0x00ff) , ((u16Msk) & 0x00ff)); \ 420 } \ 421 else \ 422 { \ 423 MReg_Write2Byte(u32Base, u32Reg, (((u16Val) & (u16Msk)) | (MReg_Read2Byte(u32Base, u32Reg) & (~(u16Msk))))); \ 424 } \ 425 } while(0) 426 427 #endif // _REG_SYSTEM_H_ 428