1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
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31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
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43 // You agree that this Section 4 shall still apply without being affected
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45 // request or instruction for your use, except otherwise agreed by both
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47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
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50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
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53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
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59 // mark, symbol or any other identification;
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61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
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64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78
79 #ifndef _HAL_IRQTBL_H_
80 #define _HAL_IRQTBL_H_
81
82 #ifdef __cplusplus
83 extern "C"
84 {
85 #endif
86
87 #define E_INT_RESERVED E_INT_IRQ_FIQ_NONE
88
89 #if defined(MSOS_TYPE_LINUX)
90 #ifdef CHIP_INT_SPI_MODE
91 //[CHIP][HAL][008] Set interrupt base address in SPI mode (User Mode) [START]
92 #define CONFIG_IRQL_BASE_ADDRESS 0x00
93 #define CONFIG_IRQH_BASE_ADDRESS 0x10
94 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x20
95 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x30
96 #define CONFIG_FIQL_BASE_ADDRESS 0x40
97 #define CONFIG_FIQH_BASE_ADDRESS 0x50
98 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
99 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
100 #define CONFIG_IRQHYPL_BASE_ADDRESS 0xA0
101 #define CONFIG_IRQHYPH_BASE_ADDRESS 0xB0
102 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xFF
103 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xFF
104 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xC0
105 #define CONFIG_FIQHYPH_BASE_ADDRESS 0xD0
106 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xFF
107 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xFF
108 //[CHIP][HAL][008] Set interrupt base address in SPI mode (User Mode) [END]
109 #else
110 //[CHIP][HAL][009] Set interrupt base address in PPI mode (User Mode) [START]
111 #define CONFIG_FIQL_BASE_ADDRESS 0x00
112 #define CONFIG_FIQH_BASE_ADDRESS 0x10
113 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x20
114 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x30
115 #define CONFIG_IRQL_BASE_ADDRESS 0x40
116 #define CONFIG_IRQH_BASE_ADDRESS 0x50
117 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x60
118 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x70
119 #define CONFIG_FIQHYPL_BASE_ADDRESS 0x80
120 #define CONFIG_FIQHYPH_BASE_ADDRESS 0x90
121 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xA0
122 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xB0
123 #define CONFIG_IRQHYPL_BASE_ADDRESS 0xC0
124 #define CONFIG_IRQHYPH_BASE_ADDRESS 0xD0
125 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xE0
126 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xF0
127 //[CHIP][HAL][009] Set interrupt base address in PPI mode (User Mode) [END]
128 #endif
129
130 #elif defined(MSOS_TYPE_NOS)
131 //[CHIP][HAL][010] Set interrupt base address in PPI mode (Non-OS) [START]
132 #define CONFIG_IRQL_BASE_ADDRESS 0x00
133 #define CONFIG_IRQH_BASE_ADDRESS 0x10
134 #define CONFIG_FIQL_BASE_ADDRESS 0x20
135 #define CONFIG_FIQH_BASE_ADDRESS 0x30
136 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x40
137 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x50
138 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
139 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
140 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
141 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
142 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xA0
143 #define CONFIG_FIQHYPH_BASE_ADDRESS 0xB0
144 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xC0
145 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xD0
146 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xE0
147 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xF0
148 //[CHIP][HAL][010] Set interrupt base address in PPI mode (Non-OS) [END]
149 #elif defined(MSOS_TYPE_NUTTX)
150 //[CHIP][HAL][011] Set interrupt base address in PPI mode (Nuttx) [START]
151 #define CONFIG_IRQL_BASE_ADDRESS 0x00
152 #define CONFIG_IRQH_BASE_ADDRESS 0x10
153 #define CONFIG_FIQL_BASE_ADDRESS 0x20
154 #define CONFIG_FIQH_BASE_ADDRESS 0x30
155 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x40
156 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x50
157 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
158 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
159 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
160 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
161 #define CONFIG_FIQHYPL_BASE_ADDRESS 0xA0
162 #define CONFIG_FIQHYPH_BASE_ADDRESS 0xB0
163 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xC0
164 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xD0
165 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xE0
166 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xF0
167 //[CHIP][HAL][011] Set interrupt base address in PPI mode (Nuttx) [END]
168 #elif defined(MSOS_TYPE_LINUX_KERNEL)
169 //[CHIP][HAL][012] Set interrupt base address in PPI mode (Kernel Mode) [START]
170 // Interrupt Base definition needed to macth Kernel define ./arch/arm/arm-boards/napoli/chip_int.h
171 #define MSTAR_INT_BASE 0x80 //PPI mode
172
173 #define CONFIG_IRQL_BASE_ADDRESS 0x40
174 #define CONFIG_IRQH_BASE_ADDRESS 0x50
175 #define CONFIG_FIQL_BASE_ADDRESS 0x00
176 #define CONFIG_FIQH_BASE_ADDRESS 0x10
177 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x60
178 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x70
179 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x20
180 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x30
181
182 #define CONFIG_IRQHYPL_BASE_ADDRESS 0xC0
183 #define CONFIG_IRQHYPH_BASE_ADDRESS 0xD0
184 #define CONFIG_FIQHYPL_BASE_ADDRESS 0x80
185 #define CONFIG_FIQHYPH_BASE_ADDRESS 0x90
186 #define CONFIG_IRQSUPL_BASE_ADDRESS 0xE0
187 #define CONFIG_IRQSUPH_BASE_ADDRESS 0xF0
188 #define CONFIG_FIQSUPL_BASE_ADDRESS 0xA0
189 #define CONFIG_FIQSUPH_BASE_ADDRESS 0xB0
190 //[CHIP][HAL][012] Set interrupt base address in PPI mode (Kernel Mode) [END]
191 #else
192 #error "Unknown Platform Selection"
193 #endif
194
195 typedef enum
196 {
197 E_IRQL_START = CONFIG_IRQL_BASE_ADDRESS,
198 E_IRQ_00 = E_IRQL_START + 0,
199 E_IRQ_01 = E_IRQL_START + 1,
200 E_IRQ_02 = E_IRQL_START + 2,
201 E_IRQ_03 = E_IRQL_START + 3,
202 E_IRQ_04 = E_IRQL_START + 4,
203 E_IRQ_05 = E_IRQL_START + 5,
204 E_IRQ_06 = E_IRQL_START + 6,
205 E_IRQ_07 = E_IRQL_START + 7,
206 E_IRQ_08 = E_IRQL_START + 8,
207 E_IRQ_09 = E_IRQL_START + 9,
208 E_IRQ_10 = E_IRQL_START + 10,
209 E_IRQ_11 = E_IRQL_START + 11,
210 E_IRQ_12 = E_IRQL_START + 12,
211 E_IRQ_13 = E_IRQL_START + 13,
212 E_IRQ_14 = E_IRQL_START + 14,
213 E_IRQ_15 = E_IRQL_START + 15,
214 E_IRQL_END = E_IRQL_START + 15,
215
216 E_IRQH_START = CONFIG_IRQH_BASE_ADDRESS,
217 E_IRQ_16 = E_IRQH_START + 0,
218 E_IRQ_17 = E_IRQH_START + 1,
219 E_IRQ_18 = E_IRQH_START + 2,
220 E_IRQ_19 = E_IRQH_START + 3,
221 E_IRQ_20 = E_IRQH_START + 4,
222 E_IRQ_21 = E_IRQH_START + 5,
223 E_IRQ_22 = E_IRQH_START + 6,
224 E_IRQ_23 = E_IRQH_START + 7,
225 E_IRQ_24 = E_IRQH_START + 8,
226 E_IRQ_25 = E_IRQH_START + 9,
227 E_IRQ_26 = E_IRQH_START + 10,
228 E_IRQ_27 = E_IRQH_START + 11,
229 E_IRQ_28 = E_IRQH_START + 12,
230 E_IRQ_29 = E_IRQH_START + 13,
231 E_IRQ_30 = E_IRQH_START + 14,
232 E_IRQ_31 = E_IRQH_START + 15,
233 E_IRQH_END = E_IRQH_START + 15,
234
235 E_FIQL_START = CONFIG_FIQL_BASE_ADDRESS,
236 E_FIQ_00 = E_FIQL_START + 0,
237 E_FIQ_01 = E_FIQL_START + 1,
238 E_FIQ_02 = E_FIQL_START + 2,
239 E_FIQ_03 = E_FIQL_START + 3,
240 E_FIQ_04 = E_FIQL_START + 4,
241 E_FIQ_05 = E_FIQL_START + 5,
242 E_FIQ_06 = E_FIQL_START + 6,
243 E_FIQ_07 = E_FIQL_START + 7,
244 E_FIQ_08 = E_FIQL_START + 8,
245 E_FIQ_09 = E_FIQL_START + 9,
246 E_FIQ_10 = E_FIQL_START + 10,
247 E_FIQ_11 = E_FIQL_START + 11,
248 E_FIQ_12 = E_FIQL_START + 12,
249 E_FIQ_13 = E_FIQL_START + 13,
250 E_FIQ_14 = E_FIQL_START + 14,
251 E_FIQ_15 = E_FIQL_START + 15,
252 E_FIQL_END = E_FIQL_START + 15,
253
254 E_FIQH_START = CONFIG_FIQH_BASE_ADDRESS,
255 E_FIQ_16 = E_FIQH_START + 0,
256 E_FIQ_17 = E_FIQH_START + 1,
257 E_FIQ_18 = E_FIQH_START + 2,
258 E_FIQ_19 = E_FIQH_START + 3,
259 E_FIQ_20 = E_FIQH_START + 4,
260 E_FIQ_21 = E_FIQH_START + 5,
261 E_FIQ_22 = E_FIQH_START + 6,
262 E_FIQ_23 = E_FIQH_START + 7,
263 E_FIQ_24 = E_FIQH_START + 8,
264 E_FIQ_25 = E_FIQH_START + 9,
265 E_FIQ_26 = E_FIQH_START + 10,
266 E_FIQ_27 = E_FIQH_START + 11,
267 E_FIQ_28 = E_FIQH_START + 12,
268 E_FIQ_29 = E_FIQH_START + 13,
269 E_FIQ_30 = E_FIQH_START + 14,
270 E_FIQ_31 = E_FIQH_START + 15,
271 E_FIQH_END = E_FIQH_START + 15,
272
273 E_IRQEXPL_START = CONFIG_IRQEXPL_BASE_ADDRESS,
274 E_IRQ_32 = E_IRQEXPL_START + 0,
275 E_IRQ_33 = E_IRQEXPL_START + 1,
276 E_IRQ_34 = E_IRQEXPL_START + 2,
277 E_IRQ_35 = E_IRQEXPL_START + 3,
278 E_IRQ_36 = E_IRQEXPL_START + 4,
279 E_IRQ_37 = E_IRQEXPL_START + 5,
280 E_IRQ_38 = E_IRQEXPL_START + 6,
281 E_IRQ_39 = E_IRQEXPL_START + 7,
282 E_IRQ_40 = E_IRQEXPL_START + 8,
283 E_IRQ_41 = E_IRQEXPL_START + 9,
284 E_IRQ_42 = E_IRQEXPL_START + 10,
285 E_IRQ_43 = E_IRQEXPL_START + 11,
286 E_IRQ_44 = E_IRQEXPL_START + 12,
287 E_IRQ_45 = E_IRQEXPL_START + 13,
288 E_IRQ_46 = E_IRQEXPL_START + 14,
289 E_IRQ_47 = E_IRQEXPL_START + 15,
290 E_IRQEXPL_END = E_IRQEXPL_START + 15,
291
292 E_IRQEXPH_START = CONFIG_IRQEXPH_BASE_ADDRESS,
293 E_IRQ_48 = E_IRQEXPH_START + 0,
294 E_IRQ_49 = E_IRQEXPH_START + 1,
295 E_IRQ_50 = E_IRQEXPH_START + 2,
296 E_IRQ_51 = E_IRQEXPH_START + 3,
297 E_IRQ_52 = E_IRQEXPH_START + 4,
298 E_IRQ_53 = E_IRQEXPH_START + 5,
299 E_IRQ_54 = E_IRQEXPH_START + 6,
300 E_IRQ_55 = E_IRQEXPH_START + 7,
301 E_IRQ_56 = E_IRQEXPH_START + 8,
302 E_IRQ_57 = E_IRQEXPH_START + 9,
303 E_IRQ_58 = E_IRQEXPH_START + 10,
304 E_IRQ_59 = E_IRQEXPH_START + 11,
305 E_IRQ_60 = E_IRQEXPH_START + 12,
306 E_IRQ_61 = E_IRQEXPH_START + 13,
307 E_IRQ_62 = E_IRQEXPH_START + 14,
308 E_IRQ_63 = E_IRQEXPH_START + 15,
309 E_IRQEXPH_END = E_IRQEXPH_START + 15,
310
311 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS,
312 E_FIQ_32 = E_FIQEXPL_START + 0,
313 E_FIQ_33 = E_FIQEXPL_START + 1,
314 E_FIQ_34 = E_FIQEXPL_START + 2,
315 E_FIQ_35 = E_FIQEXPL_START + 3,
316 E_FIQ_36 = E_FIQEXPL_START + 4,
317 E_FIQ_37 = E_FIQEXPL_START + 5,
318 E_FIQ_38 = E_FIQEXPL_START + 6,
319 E_FIQ_39 = E_FIQEXPL_START + 7,
320 E_FIQ_40 = E_FIQEXPL_START + 8,
321 E_FIQ_41 = E_FIQEXPL_START + 9,
322 E_FIQ_42 = E_FIQEXPL_START + 10,
323 E_FIQ_43 = E_FIQEXPL_START + 11,
324 E_FIQ_44 = E_FIQEXPL_START + 12,
325 E_FIQ_45 = E_FIQEXPL_START + 13,
326 E_FIQ_46 = E_FIQEXPL_START + 14,
327 E_FIQ_47 = E_FIQEXPL_START + 15,
328 E_FIQEXPL_END = E_FIQEXPL_START + 15,
329
330 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS,
331 E_FIQ_48 = E_FIQEXPH_START + 0,
332 E_FIQ_49 = E_FIQEXPH_START + 1,
333 E_FIQ_50 = E_FIQEXPH_START + 2,
334 E_FIQ_51 = E_FIQEXPH_START + 3,
335 E_FIQ_52 = E_FIQEXPH_START + 4,
336 E_FIQ_53 = E_FIQEXPH_START + 5,
337 E_FIQ_54 = E_FIQEXPH_START + 6,
338 E_FIQ_55 = E_FIQEXPH_START + 7,
339 E_FIQ_56 = E_FIQEXPH_START + 8,
340 E_FIQ_57 = E_FIQEXPH_START + 9,
341 E_FIQ_58 = E_FIQEXPH_START + 10,
342 E_FIQ_59 = E_FIQEXPH_START + 11,
343 E_FIQ_60 = E_FIQEXPH_START + 12,
344 E_FIQ_61 = E_FIQEXPH_START + 13,
345 E_FIQ_62 = E_FIQEXPH_START + 14,
346 E_FIQ_63 = E_FIQEXPH_START + 15,
347 E_FIQEXPH_END = E_FIQEXPH_START + 15,
348
349 E_IRQHYPL_START = CONFIG_IRQHYPL_BASE_ADDRESS,
350 E_IRQ_64 = E_IRQHYPL_START + 0,
351 E_IRQ_65 = E_IRQHYPL_START + 1,
352 E_IRQ_66 = E_IRQHYPL_START + 2,
353 E_IRQ_67 = E_IRQHYPL_START + 3,
354 E_IRQ_68 = E_IRQHYPL_START + 4,
355 E_IRQ_69 = E_IRQHYPL_START + 5,
356 E_IRQ_70 = E_IRQHYPL_START + 6,
357 E_IRQ_71 = E_IRQHYPL_START + 7,
358 E_IRQ_72 = E_IRQHYPL_START + 8,
359 E_IRQ_73 = E_IRQHYPL_START + 9,
360 E_IRQ_74 = E_IRQHYPL_START + 10,
361 E_IRQ_75 = E_IRQHYPL_START + 11,
362 E_IRQ_76 = E_IRQHYPL_START + 12,
363 E_IRQ_77 = E_IRQHYPL_START + 13,
364 E_IRQ_78 = E_IRQHYPL_START + 14,
365 E_IRQ_79 = E_IRQHYPL_START + 15,
366 E_IRQHYPL_END = E_IRQHYPL_START + 15,
367
368 E_IRQHYPH_START = CONFIG_IRQHYPH_BASE_ADDRESS,
369 E_IRQ_80 = E_IRQHYPH_START + 0,
370 E_IRQ_81 = E_IRQHYPH_START + 1,
371 E_IRQ_82 = E_IRQHYPH_START + 2,
372 E_IRQ_83 = E_IRQHYPH_START + 3,
373 E_IRQ_84 = E_IRQHYPH_START + 4,
374 E_IRQ_85 = E_IRQHYPH_START + 5,
375 E_IRQ_86 = E_IRQHYPH_START + 6,
376 E_IRQ_87 = E_IRQHYPH_START + 7,
377 E_IRQ_88 = E_IRQHYPH_START + 8,
378 E_IRQ_89 = E_IRQHYPH_START + 9,
379 E_IRQ_90 = E_IRQHYPH_START + 10,
380 E_IRQ_91 = E_IRQHYPH_START + 11,
381 E_IRQ_92 = E_IRQHYPH_START + 12,
382 E_IRQ_93 = E_IRQHYPH_START + 13,
383 E_IRQ_94 = E_IRQHYPH_START + 14,
384 E_IRQ_95 = E_IRQHYPH_START + 15,
385 E_IRQHYPH_END = E_IRQHYPH_START + 15,
386
387
388 E_FIQHYPL_START = CONFIG_FIQHYPL_BASE_ADDRESS,
389 E_FIQ_64 = E_FIQHYPL_START + 0,
390 E_FIQ_65 = E_FIQHYPL_START + 1,
391 E_FIQ_66 = E_FIQHYPL_START + 2,
392 E_FIQ_67 = E_FIQHYPL_START + 3,
393 E_FIQ_68 = E_FIQHYPL_START + 4,
394 E_FIQ_69 = E_FIQHYPL_START + 5,
395 E_FIQ_70 = E_FIQHYPL_START + 6,
396 E_FIQ_71 = E_FIQHYPL_START + 7,
397 E_FIQ_72 = E_FIQHYPL_START + 8,
398 E_FIQ_73 = E_FIQHYPL_START + 9,
399 E_FIQ_74 = E_FIQHYPL_START + 10,
400 E_FIQ_75 = E_FIQHYPL_START + 11,
401 E_FIQ_76 = E_FIQHYPL_START + 12,
402 E_FIQ_77 = E_FIQHYPL_START + 13,
403 E_FIQ_78 = E_FIQHYPL_START + 14,
404 E_FIQ_79 = E_FIQHYPL_START + 15,
405 E_FIQHYPL_END = E_FIQHYPL_START + 15,
406
407 E_FIQHYPH_START = CONFIG_FIQHYPH_BASE_ADDRESS,
408 E_FIQ_80 = E_FIQHYPH_START + 0,
409 E_FIQ_81 = E_FIQHYPH_START + 1,
410 E_FIQ_82 = E_FIQHYPH_START + 2,
411 E_FIQ_83 = E_FIQHYPH_START + 3,
412 E_FIQ_84 = E_FIQHYPH_START + 4,
413 E_FIQ_85 = E_FIQHYPH_START + 5,
414 E_FIQ_86 = E_FIQHYPH_START + 6,
415 E_FIQ_87 = E_FIQHYPH_START + 7,
416 E_FIQ_88 = E_FIQHYPH_START + 8,
417 E_FIQ_89 = E_FIQHYPH_START + 9,
418 E_FIQ_90 = E_FIQHYPH_START + 10,
419 E_FIQ_91 = E_FIQHYPH_START + 11,
420 E_FIQ_92 = E_FIQHYPH_START + 12,
421 E_FIQ_93 = E_FIQHYPH_START + 13,
422 E_FIQ_94 = E_FIQHYPH_START + 14,
423 E_FIQ_95 = E_FIQHYPH_START + 15,
424 E_FIQHYPH_END = E_FIQHYPH_START + 15,
425
426 E_IRQ_FIQ_NONE = 0xFE,
427 E_IRQ_FIQ_ALL = 0xFF
428
429 } IRQFIQNum;
430
431 static MS_U32 IntEnum2HWIdx[E_INT_IRQ_MAX];
432 static MS_U32 HWIdx2IntEnum[E_IRQ_FIQ_ALL];
433 #if defined(MSOS_TYPE_LINUX_KERNEL)
434 static char DefaultName[5] = "NONE";
435 static char* HWIdx2IRQname[E_IRQ_FIQ_ALL] = {DefaultName};
436 #endif
437
HAL_UpdateIrqTable(MS_U32 byHardwareIndex,MS_U32 bySoftwareIndex)438 static void HAL_UpdateIrqTable(MS_U32 byHardwareIndex, MS_U32 bySoftwareIndex)
439 {
440 if(bySoftwareIndex == E_INT_RESERVED)
441 {
442 IntEnum2HWIdx[bySoftwareIndex] = E_IRQ_FIQ_NONE;
443 HWIdx2IntEnum[byHardwareIndex] = E_INT_IRQ_FIQ_NONE;
444 }
445 else
446 {
447 IntEnum2HWIdx[bySoftwareIndex] = byHardwareIndex;
448 HWIdx2IntEnum[byHardwareIndex] = bySoftwareIndex;
449 }
450 }
451
HAL_InitIrqTable(void)452 static void HAL_InitIrqTable(void)
453 {
454 unsigned int dwDataCounter = 0;
455
456 #if defined(CONFIG_FRC)//(frcr2_integration###)
457 for(dwDataCounter = 0; dwDataCounter < 256; dwDataCounter ++)
458 {
459 IntEnum2HWIdx[dwDataCounter] = E_IRQ_FIQ_NONE;
460 HWIdx2IntEnum[dwDataCounter] = E_INT_IRQ_FIQ_NONE;
461 }
462
463 //[CHIP][HAL][014] Set IRQ mapping table (FRC R2) [START]
464 //FRC IRQ
465 HAL_UpdateIrqTable(E_IRQ_06, E_FRCINT_IRQ_ERROR_RESP_INT);
466 HAL_UpdateIrqTable(E_IRQ_07, E_INT_RESERVED);
467 HAL_UpdateIrqTable(E_IRQ_08, E_INT_RESERVED);
468 HAL_UpdateIrqTable(E_IRQ_09, E_FRCINT_IRQ_MC2D_MEDONE_INT1);
469 HAL_UpdateIrqTable(E_IRQ_10, E_FRCINT_IRQ_MC2D_MEDONE_INT0);
470 HAL_UpdateIrqTable(E_IRQ_11, E_FRCINT_IRQ_FSC_INT1);
471 HAL_UpdateIrqTable(E_IRQ_12, E_FRCINT_IRQ_FSC_INT0);
472 HAL_UpdateIrqTable(E_IRQ_13, E_FRCINT_IRQ_FO_INT_CPU0_OP_INT);
473 HAL_UpdateIrqTable(E_IRQ_14, E_FRCINT_IRQ_FO_INT_CPU1_OP_INT);
474
475 //FRC FIQ
476 HAL_UpdateIrqTable(E_FIQ_00, E_FRCINT_FIQ_HST0_TO_HST1);
477 HAL_UpdateIrqTable(E_FIQ_01, E_FRCINT_FIQ_HST0_TO_HST2);
478 HAL_UpdateIrqTable(E_FIQ_02, E_FRCINT_FIQ_HST0_TO_HST3);
479 HAL_UpdateIrqTable(E_FIQ_03, E_FRCINT_FIQ_HST1_TO_HST0);
480 HAL_UpdateIrqTable(E_FIQ_04, E_FRCINT_FIQ_HST1_TO_HST2);
481 HAL_UpdateIrqTable(E_FIQ_05, E_FRCINT_FIQ_HST1_TO_HST3);
482 HAL_UpdateIrqTable(E_FIQ_06, E_FRCINT_FIQ_HST2_TO_HST0);
483 HAL_UpdateIrqTable(E_FIQ_07, E_FRCINT_FIQ_HST2_TO_HST1);
484 HAL_UpdateIrqTable(E_FIQ_08, E_FRCINT_FIQ_HST2_TO_HST3);
485 HAL_UpdateIrqTable(E_FIQ_09, E_FRCINT_FIQ_HST3_TO_HST0);
486 HAL_UpdateIrqTable(E_FIQ_10, E_FRCINT_FIQ_HST3_TO_HST1);
487 HAL_UpdateIrqTable(E_FIQ_11, E_FRCINT_FIQ_HST3_TO_HST2);
488
489 HAL_UpdateIrqTable(E_FIQ_12, E_FRCINT_FIQ_FRC_TIMER0);
490 HAL_UpdateIrqTable(E_FIQ_13, E_FRCINT_FIQ_FRC_TIMER1);
491 HAL_UpdateIrqTable(E_FIQ_18, E_FRCINT_FIQ_FRC_XIU_TIMEOUT);
492 HAL_UpdateIrqTable(E_FIQ_20, E_FRCINT_FIQ_FRC_TO_MCU);
493 HAL_UpdateIrqTable(E_FIQ_21, E_FRCINT_FIQ_MCU_TO_FRC);
494 HAL_UpdateIrqTable(E_FIQ_22, E_FRCINT_FIQ_MC2D_MEDONE_INT3);
495 HAL_UpdateIrqTable(E_FIQ_23, E_FRCINT_FIQ_MC2D_MEDONE_INT2);
496 HAL_UpdateIrqTable(E_FIQ_24, E_FRCINT_FIQ_FSC_INIT1);
497 HAL_UpdateIrqTable(E_FIQ_25, E_FRCINT_FIQ_FSC_INIT0);
498 HAL_UpdateIrqTable(E_FIQ_26, E_FRCINT_FIQ_FO_INT_CPU1_OP);
499 HAL_UpdateIrqTable(E_FIQ_27, E_FRCINT_FIQ_FO_INT_CPU0_OP);
500 //[CHIP][HAL][014] Set IRQ mapping table (FRC R2) [END]
501 #else
502 for(dwDataCounter = 0; dwDataCounter < E_IRQ_FIQ_ALL; dwDataCounter ++)
503 {
504 IntEnum2HWIdx[dwDataCounter] = E_IRQ_FIQ_NONE;
505 HWIdx2IntEnum[dwDataCounter] = E_INT_IRQ_FIQ_NONE;
506 }
507
508 for(dwDataCounter = E_IRQ_FIQ_ALL; dwDataCounter < E_INT_IRQ_MAX; dwDataCounter++)
509 {
510 IntEnum2HWIdx[dwDataCounter] = E_IRQ_FIQ_NONE;
511 }
512
513 //[CHIP][HAL][013] Set IRQ mapping table [START]
514 HAL_UpdateIrqTable(E_IRQ_00, E_INT_IRQ_UART0); //int_uart0
515 HAL_UpdateIrqTable(E_IRQ_01, E_INT_IRQ_PMSLEEP); //pm_sleep_int
516 HAL_UpdateIrqTable(E_IRQ_02, E_INT_IRQ_USB30_SS_INT); //usb30_ss_int
517 HAL_UpdateIrqTable(E_IRQ_03, E_INT_IRQ_MVD); //mvd_int
518 HAL_UpdateIrqTable(E_IRQ_04, E_INT_IRQ_PS); //ps_int
519 HAL_UpdateIrqTable(E_IRQ_05, E_INT_IRQ_NFIE); //nfie_int
520 HAL_UpdateIrqTable(E_IRQ_06, E_INT_IRQ_USB); //usb_int
521 HAL_UpdateIrqTable(E_IRQ_07, E_INT_IRQ_UHC); //uhc_int
522 HAL_UpdateIrqTable(E_IRQ_08, E_INT_IRQ_MIIC_INT5); //miic5_int
523 HAL_UpdateIrqTable(E_IRQ_09, E_INT_IRQ_EMAC); //emac_int
524 HAL_UpdateIrqTable(E_IRQ_10, E_INT_IRQ_DISP); //disp_be_int
525 HAL_UpdateIrqTable(E_IRQ_11, E_INT_IRQ_MSPI0); //mspi_int
526 HAL_UpdateIrqTable(E_IRQ_12, E_INT_IRQ_MIIC_INT3); //miic3_int
527 HAL_UpdateIrqTable(E_IRQ_13, E_INT_IRQ_EVD); //evd_int
528 HAL_UpdateIrqTable(E_IRQ_14, E_INT_IRQ_COMB); //comb_int
529 HAL_UpdateIrqTable(E_IRQ_15, E_INT_FIQ_LDM_DMA0); //ldm_dma_done_int0
530
531 HAL_UpdateIrqTable(E_IRQ_16, E_INT_IRQ_TSP2HK); //tsp2hk_int
532 HAL_UpdateIrqTable(E_IRQ_17, E_INT_IRQ_VE); //ve_int
533 HAL_UpdateIrqTable(E_IRQ_18, E_INT_IRQ_USB3); //usb_int3 - new
534 HAL_UpdateIrqTable(E_IRQ_19, E_INT_IRQ_DC); //dc_int
535 HAL_UpdateIrqTable(E_IRQ_20, E_INT_IRQ_GOP); //gop_int
536 HAL_UpdateIrqTable(E_IRQ_21, E_INT_IRQ_PCM); //pcm2mcu_int
537 HAL_UpdateIrqTable(E_IRQ_22, E_INT_FIQ_LDM_DMA1); //ldm_dma_done_int1
538 HAL_UpdateIrqTable(E_IRQ_23, E_INT_IRQ_SMART); //smart_int
539 HAL_UpdateIrqTable(E_IRQ_24, E_INT_IRQ_UART4); //int_uart4
540 HAL_UpdateIrqTable(E_IRQ_25, E_INT_IRQ_MOD_DET_INT); //mod_detect_intr
541 HAL_UpdateIrqTable(E_IRQ_26, E_INT_IRQ_MIIC_INT4); //miic4_int
542 HAL_UpdateIrqTable(E_IRQ_27, E_INT_IRQ_SCM); //scm_int
543 HAL_UpdateIrqTable(E_IRQ_28, E_INT_IRQ_VBI); //vbi_int
544 HAL_UpdateIrqTable(E_IRQ_29, E_INT_IRQ_MVD2MIPS); //mvd2mips_int
545 HAL_UpdateIrqTable(E_IRQ_30, E_INT_IRQ_GPD); //gpd_int
546 HAL_UpdateIrqTable(E_IRQ_31, E_INT_IRQ_ADCDVI2RIU); //adcdvi2riu_int
547
548 HAL_UpdateIrqTable(E_IRQ_32, E_INT_IRQ_SVD_HVD); //hvd_int
549 HAL_UpdateIrqTable(E_IRQ_33, E_INT_IRQ_USB1); //usb_int1
550 HAL_UpdateIrqTable(E_IRQ_34, E_INT_IRQ_UHC1); //uhc_int1
551 HAL_UpdateIrqTable(E_IRQ_35, E_INT_IRQ_ERROR_RESP); //error_resp_int
552 HAL_UpdateIrqTable(E_IRQ_36, E_INT_IRQ_USB2); //usb_int2
553 HAL_UpdateIrqTable(E_IRQ_37, E_INT_IRQ_UHC2); //uhc_int2
554 HAL_UpdateIrqTable(E_IRQ_38, E_INT_IRQ_MIU); //miu_int - new
555 HAL_UpdateIrqTable(E_IRQ_39, E_INT_IRQ_UART1); //int_uart1
556 HAL_UpdateIrqTable(E_IRQ_40, E_INT_IRQ_UART2); //int_uart2
557 HAL_UpdateIrqTable(E_IRQ_41, E_INT_IRQ_MSPI1); //mspi1_int
558 HAL_UpdateIrqTable(E_IRQ_42, E_INT_IRQ_MIU_SECURITY); //miu_security_int
559 HAL_UpdateIrqTable(E_IRQ_43, E_INT_IRQ_DIPW); //dipw_INT
560 HAL_UpdateIrqTable(E_IRQ_44, E_INT_IRQ_MIIC_INT2); //miic2_int
561 HAL_UpdateIrqTable(E_IRQ_45, E_INT_IRQ_JPD); //jpd_int
562 HAL_UpdateIrqTable(E_IRQ_46, E_INT_IRQ_PM); //pm_irq_out
563 HAL_UpdateIrqTable(E_IRQ_47, E_INT_IRQ_MFE); //mfe_int
564
565 HAL_UpdateIrqTable(E_IRQ_48, E_INT_IRQ_BDMA0); //int_bdma_merge
566 HAL_UpdateIrqTable(E_IRQ_49, E_INT_IRQ_UART3); //int_uart3
567 HAL_UpdateIrqTable(E_IRQ_50, E_INT_IRQ_UART2MCU); //uart2mcu_intr
568 HAL_UpdateIrqTable(E_IRQ_51, E_INT_IRQ_URDMA2MCU); //urdma2mcu_intr
569 HAL_UpdateIrqTable(E_IRQ_52, E_INT_IRQ_DVI_HDMI_HDCP); //dvi_hdmi_hdcp_int
570 HAL_UpdateIrqTable(E_IRQ_53, E_INT_IRQ_G3D2MCU); //g3d2mcu_irq_dft
571 HAL_UpdateIrqTable(E_IRQ_54, E_INT_IRQ_FRC_INT_FIQ2HST0); //irq_fiq2mips
572 HAL_UpdateIrqTable(E_IRQ_55, E_INT_HDCP_ICC_INT); //hdcp_icc_int
573 HAL_UpdateIrqTable(E_IRQ_56, E_INT_IRQ_HDCP_X74); //hdcp_x74_int
574 HAL_UpdateIrqTable(E_IRQ_57, E_INT_IRQ_WADR_ERR); //wadr_err_int
575 HAL_UpdateIrqTable(E_IRQ_58, E_INT_IRQ_DCSUB); //dcsub_int
576 HAL_UpdateIrqTable(E_IRQ_59, E_INT_IRQ_SDIO_OSP_INT); //sdio_int
577 HAL_UpdateIrqTable(E_IRQ_60, E_INT_FIQEXPH_CMDQ); //cmdq_int
578 HAL_UpdateIrqTable(E_IRQ_61, E_INT_IRQ_MIIC_INT1); //miic1_int
579 HAL_UpdateIrqTable(E_IRQ_62, E_INT_RESERVED); //non
580 HAL_UpdateIrqTable(E_IRQ_63, E_INT_IRQ_MIIC_INT0); //miic0_int
581 HAL_UpdateIrqTable(E_IRQ_64, E_INT_IRQ_HDMI_LEVEL); //HDMITX_IRQ_LEVEL - new
582 HAL_UpdateIrqTable(E_IRQ_65, E_INT_IRQ_VD_EVD_R22HI_INT); //irq_vd_evd_r22hi
583 HAL_UpdateIrqTable(E_IRQ_66, E_INT_IRQ_UHC3); //uhc_int3 - new
584 HAL_UpdateIrqTable(E_IRQ_67, E_INT_IRQ_GE); //ge_int
585 HAL_UpdateIrqTable(E_IRQ_68, E_INT_IRQ_CEC); //cec_int_pm
586 HAL_UpdateIrqTable(E_IRQ_69, E_INT_IRQ_DISP_FE_INT); //disp_fe_int
587 HAL_UpdateIrqTable(E_IRQ_70, E_INT_IRQ_SCDC_PM_INT); //scdc_int_pm
588 HAL_UpdateIrqTable(E_IRQ_71, E_INT_RESERVED); //non
589 HAL_UpdateIrqTable(E_IRQ_72, E_INT_RESERVED); //non
590 HAL_UpdateIrqTable(E_IRQ_73, E_INT_IRQ_USB30_HS_USB_INT); //usb30_hs_usb_int
591 HAL_UpdateIrqTable(E_IRQ_74, E_INT_IRQ_USB30_HS_UHC_INT); //usb30_hs_uhc_int
592 HAL_UpdateIrqTable(E_IRQ_75, E_INT_IRQ_HDMITX); //hdmitx_phy_int - new
593 HAL_UpdateIrqTable(E_IRQ_76, E_INT_KG1_INT); //kg1_int
594 HAL_UpdateIrqTable(E_IRQ_77, E_INT_IRQ_TSP_FI_QUEUE_INT); //tsp_fi_queue_int
595 HAL_UpdateIrqTable(E_IRQ_78, E_INT_IRQ_DISP_SC2_INT); //disp_sc2_int
596 HAL_UpdateIrqTable(E_IRQ_79, E_INT_IRQ_MSPI_MCARD_INT); //mspi_mcard_int
597 HAL_UpdateIrqTable(E_IRQ_80, E_FRCINT_IRQ_D2B); //d2b_int
598 HAL_UpdateIrqTable(E_IRQ_81, E_INT_IRQ_AUDMA_V2_INT); //AUDMA_V2_INTR
599 HAL_UpdateIrqTable(E_IRQ_82, E_INT_IRQ_EMMC_OSP_INT); //emmc_osp_init
600 HAL_UpdateIrqTable(E_IRQ_83, E_INT_IRQ_MHL_ECBUS_INT); //mhl_ecbus_int
601 HAL_UpdateIrqTable(E_IRQ_84, E_INT_PKA_ALL_INT); //pka_all_int
602 HAL_UpdateIrqTable(E_IRQ_85, E_INT_IRQ_CFKTKS_NONSEC_INT); //cfktks_int_nonsec
603 HAL_UpdateIrqTable(E_IRQ_86, E_INT_IRQ_CFKTKS_INT); //cfktks_int
604 HAL_UpdateIrqTable(E_IRQ_87, E_INT_IRQ_CFDONE_INT); //cfdone_int
605 HAL_UpdateIrqTable(E_IRQ_88, E_INT_IRQ_RXIU_TIMEOUT_NODEF_INT); //rxiu_timeout_nodifine_int - new
606 HAL_UpdateIrqTable(E_IRQ_89, E_INT_IRQ_PAS_PTS_COMBINE_INT); //PAS_PTS_INTRL_COMBINE
607 HAL_UpdateIrqTable(E_IRQ_90, E_INT_IRQ_AESDMA_S_INT); //aesdma_s_int
608 HAL_UpdateIrqTable(E_IRQ_91, E_INT_IRQ_MSPI0); //mspi0_int
609 HAL_UpdateIrqTable(E_IRQ_92, E_INT_CERT_KTKS_INI_NONSEC_INT); //cert_ktks_int_nonsec
610 HAL_UpdateIrqTable(E_IRQ_93, E_INT_CERT_KTKS_INT); //cert_ktks_int
611 HAL_UpdateIrqTable(E_IRQ_94, E_INT_IRQ_AESDMA2_S_INT); //aesdma2_s_int
612 HAL_UpdateIrqTable(E_IRQ_95, E_INT_IRQ_AESMDA2_INT); //aesdma2_int
613
614 HAL_UpdateIrqTable(E_FIQ_00, E_INT_FIQ_EXTIMER0); //int_timer0
615 HAL_UpdateIrqTable(E_FIQ_01, E_INT_FIQ_EXTIMER1); //int_timer1
616 HAL_UpdateIrqTable(E_FIQ_02, E_INT_FIQ_WDT); //int_wdt
617 HAL_UpdateIrqTable(E_FIQ_03, E_INT_RESERVED); //non
618 HAL_UpdateIrqTable(E_FIQ_04, E_INT_FIQ_R2TOMCU_INT0); //MB_auR2toMCU_INT[0]
619 HAL_UpdateIrqTable(E_FIQ_05, E_INT_FIQ_R2TOMCU_INT1); //MB_auR2toMCU_INT[1]
620 HAL_UpdateIrqTable(E_FIQ_06, E_INT_FIQ_DSPTOMCU_INT0); //MB_DSP2toMCU_INT[0]
621 HAL_UpdateIrqTable(E_FIQ_07, E_INT_FIQ_DSPTOMCU_INT1); //MB_DSP2toMCU_INT[1]
622 HAL_UpdateIrqTable(E_FIQ_08, E_INT_FIQ_USB); //usb_int
623 HAL_UpdateIrqTable(E_FIQ_09, E_INT_FIQ_UHC); //uhc_int
624 HAL_UpdateIrqTable(E_FIQ_10, E_INT_RESERVED); //non
625 HAL_UpdateIrqTable(E_FIQ_11, E_INT_FIQ_HDMI_NON_PCM); //HDMI_NON_PCM_MODE_INT_OUT
626 HAL_UpdateIrqTable(E_FIQ_12, E_INT_FIQ_SPDIF_IN_NON_PCM); //SPDIF_IN_NON_PCM_INT_OUT
627 HAL_UpdateIrqTable(E_FIQ_13, E_INT_FIQ_LAN_ESD_INT); //lan_esd_int
628 HAL_UpdateIrqTable(E_FIQ_14, E_INT_FIQ_SE_DSP2UP); //SE_DSP2UP_intr
629 HAL_UpdateIrqTable(E_FIQ_15, E_INT_FIQ_TSP2AEON); //tsp2aeon_int
630
631 HAL_UpdateIrqTable(E_FIQ_16, E_INT_FIQ_VIVALDI_STR); //vivaldi_str_intr
632 HAL_UpdateIrqTable(E_FIQ_17, E_INT_FIQ_VIVALDI_PTS); //vivaldi_pts_intr
633 HAL_UpdateIrqTable(E_FIQ_18, E_INT_FIQ_DSP_MIU_PROT); //DSP_MIU_PROT_intr
634 HAL_UpdateIrqTable(E_FIQ_19, E_INT_FIQ_XIU_TIMEOUT); //xiu_timeout_int
635 HAL_UpdateIrqTable(E_FIQ_20, E_INT_FIQ_DMDMCU2HK); //dmdmcu2hk_int
636 HAL_UpdateIrqTable(E_FIQ_21, E_INT_FIQ_VSYNC_VE4VBI); //ve_vbi_f0_int
637 HAL_UpdateIrqTable(E_FIQ_22, E_INT_FIQ_FIELD_VE4VBI); //ve_vbi_f1_int
638 HAL_UpdateIrqTable(E_FIQ_23, E_INT_FIQ_VDMCU2HK); //vdmcu2hk_int
639 HAL_UpdateIrqTable(E_FIQ_24, E_INT_FIQ_VE_DONE_TT); //ve_done_TT_irq
640 HAL_UpdateIrqTable(E_FIQ_25, E_INT_IRQ_FIQ_NONE); //non
641 HAL_UpdateIrqTable(E_FIQ_26, E_INT_FIQ_PM_SD_CDZ0); //PM_SD_CDZ_int
642 HAL_UpdateIrqTable(E_FIQ_27, E_INT_IRQ_FIQ_NONE); //non
643 HAL_UpdateIrqTable(E_FIQ_28, E_INT_FIQ_AFEC_VSYNC); //AFEC_VSYNC
644 HAL_UpdateIrqTable(E_FIQ_29, E_INT_IRQ_FIQ_NONE); //non
645 HAL_UpdateIrqTable(E_FIQ_30, E_INT_IRQEXPL_TSO); //tso_int
646 HAL_UpdateIrqTable(E_FIQ_31, E_INT_FIQ_DEC_DSP2MIPS); //DSP2MIPS_INT
647
648 HAL_UpdateIrqTable(E_FIQ_32, E_INT_IRQ_FIQ_NONE); //non
649 HAL_UpdateIrqTable(E_FIQ_33, E_INT_FIQ_AU_DMA_BUF_INT); //AU_DMA_BUFFER_INT_EDGE
650 HAL_UpdateIrqTable(E_FIQ_34, E_INT_FIQ_IR); //int_all
651 HAL_UpdateIrqTable(E_FIQ_35, E_INT_FIQ_PM_SD_CDZ1); //PM_SD_CDZ1_int
652 HAL_UpdateIrqTable(E_FIQ_36, E_INT_FIQ_8051_TO_AEON); //reg_hst0to3_int
653 HAL_UpdateIrqTable(E_FIQ_37, E_INT_FIQ_8051_TO_MIPS_VPE1); //reg_hst0to2_int
654 HAL_UpdateIrqTable(E_FIQ_38, E_INT_FIQ_8051_TO_BEON); //reg_hst0to1_int
655 HAL_UpdateIrqTable(E_FIQ_39, E_INT_FIQ_GPIO0); //ext_gpio_int[0]
656 HAL_UpdateIrqTable(E_FIQ_40, E_INT_FIQ_BEON_TO_AEON); //reg_hst1to3_int
657 HAL_UpdateIrqTable(E_FIQ_41, E_INT_IRQ_FIQ_NONE); //non
658 HAL_UpdateIrqTable(E_FIQ_42, E_INT_FIQ_MIPS_VPE0_TO_8051); //reg_hst1to0_int
659 HAL_UpdateIrqTable(E_FIQ_43, E_INT_FIQ_GPIO1); //ext_gpio_int[1]
660 HAL_UpdateIrqTable(E_FIQ_44, E_INT_FIQ_MIPS_VPE0_TO_MIPS_VPE1); //reg_hst2to3_int
661 HAL_UpdateIrqTable(E_FIQ_45, E_INT_FIQ_TIMER2_INT); //int_timer2
662 HAL_UpdateIrqTable(E_FIQ_46, E_INT_FIQ_MIPS_VPE1_TO_8051); //reg_hst2to0_int
663 HAL_UpdateIrqTable(E_FIQ_47, E_INT_FIQ_GPIO2); //ext_gpio_int[2]
664
665 HAL_UpdateIrqTable(E_FIQ_48, E_INT_FIQ_AEON_TO_MIPS_VPE1); //reg_hst3to2_int
666 HAL_UpdateIrqTable(E_FIQ_49, E_INT_FIQ_AEON_TO_MIPS_VPE0); //reg_hst3to1_int
667 HAL_UpdateIrqTable(E_FIQ_50, E_INT_FIQ_AEON_TO_8051); //reg_hst3to0_int
668 HAL_UpdateIrqTable(E_FIQ_51, E_INT_FIQ_USB1); //usb_int1
669 HAL_UpdateIrqTable(E_FIQ_52, E_INT_FIQ_UHC1); //uhc_int1
670 HAL_UpdateIrqTable(E_FIQ_53, E_INT_FIQ_USB2); //usb_int2
671 HAL_UpdateIrqTable(E_FIQ_54, E_INT_FIQ_UHC2); //uhc_int2
672 HAL_UpdateIrqTable(E_FIQ_55, E_INT_FIQ_GPIO3); //ext_gpio_int[3]
673 HAL_UpdateIrqTable(E_FIQ_56, E_INT_FIQ_GPIO4); //ext_gpio_int[4]
674 HAL_UpdateIrqTable(E_FIQ_57, E_INT_FIQ_GPIO5); //ext_gpio_int[5]
675 HAL_UpdateIrqTable(E_FIQ_58, E_INT_FIQ_GPIO6); //ext_gpio_int[6]
676 HAL_UpdateIrqTable(E_FIQ_59, E_INT_IRQ_PWM_RP_L); //pwm_rp_l_int
677 HAL_UpdateIrqTable(E_FIQ_60, E_INT_IRQ_PWM_FP_L); //pwm_fp_l_int
678 HAL_UpdateIrqTable(E_FIQ_61, E_INT_IRQ_PWM_RP_R); //pwm_rp_r_int
679 HAL_UpdateIrqTable(E_FIQ_62, E_INT_IRQ_PWM_FP_R); //pwm_fp_r_int
680 HAL_UpdateIrqTable(E_FIQ_63, E_INT_FIQ_GPIO7); //ext_gpio_int[7]
681
682 HAL_UpdateIrqTable(E_FIQ_64, E_INT_FIQ_MB_A2M_INT2); //MB_auR2toMCU_INT[2]
683 HAL_UpdateIrqTable(E_FIQ_65, E_INT_FIQ_MB_A2M_INT3); //MB_auR2toMCU_INT[3]
684 HAL_UpdateIrqTable(E_FIQ_66, E_INT_FIQ_AU_SPDIF_TX_CS0); //AU_SPDIF_TX_CS_INT[0]
685 HAL_UpdateIrqTable(E_FIQ_67, E_INT_FIQ_AU_SPDIF_TX_CS1); //AU_SPDIF_TX_CS_INT[1]
686 HAL_UpdateIrqTable(E_FIQ_68, E_FRCINT_FIQ_LDM_DMA_DONE0); //ldm_dma_done_int0
687 HAL_UpdateIrqTable(E_FIQ_69, E_FRCINT_FIQ_LDM_DMA_DONE1); //ldm_dma_done_int1
688 HAL_UpdateIrqTable(E_FIQ_70, E_INT_FIQ_IR_IN); //ir_in
689 //[CHIP][HAL][013] Set IRQ mapping table [END]
690 #endif
691 }
692
693 #ifdef __cplusplus
694 }
695 #endif
696
697 #endif // _HAL_IRQTBL_H_
698
699