Lines Matching refs:E_FIQEXPL_START
189 #define FIQEXPL_IR_INT_RC (0x01 << (E_FIQ_32 - E_FIQEXPL_START))
190 #define FIQEXPL_AU_DMA_BUF_INT (0x01 << (E_FIQ_33 - E_FIQEXPL_START))
191 #define FIQEXPL_IR_IN (0x01 << (E_FIQ_34 - E_FIQEXPL_START))
193 #define FIQEXPL_8051_TO_MIPS_VPE1 (0x01 << (E_FIQ_36 - E_FIQEXPL_START))
194 #define FIQEXPL_8051_TO_BEON (0x01 << (E_FIQ_37 - E_FIQEXPL_START))
195 #define FIQEXPL_8051_TO_AEON (0x01 << (E_FIQ_38 - E_FIQEXPL_START))
196 #define FIQEXPL_GPIO0 (0x01 << (E_FIQ_39 - E_FIQEXPL_START))
197 #define FIQEXPL_AEON_TO_MIPS_VPE1 (0x01 << (E_FIQ_40 - E_FIQEXPL_START))
198 #define FIQEXPL_AEON_TO_BEON (0x01 << (E_FIQ_41 - E_FIQEXPL_START))
199 #define FIQEXPL_AEON_TO_8051 (0x01 << (E_FIQ_42 - E_FIQEXPL_START))
200 #define FIQEXPL_GPIO1 (0x01 << (E_FIQ_43 - E_FIQEXPL_START))
201 #define FIQEXPL_MIPS_VPE0_TO_MIPS_VPE1 (0x01 << (E_FIQ_44 - E_FIQEXPL_START))
202 #define FIQEXPL_TIMER2 (0x01 << (E_FIQ_45 - E_FIQEXPL_START))
203 #define FIQEXPL_BEON_TO_8051 (0x01 << (E_FIQ_46 - E_FIQEXPL_START))
204 #define FIQEXPL_GPIO2 (0x01 << (E_FIQ_47 - E_FIQEXPL_START))