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Searched refs:hw_status (Results 1 – 25 of 28) sorted by relevance

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/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vepu540c.c282 cfg1.reg = &reg_out->hw_status; in hal_jpege_v540c_start()
316 vepu540c_hw_status hw_status = elem->hw_status; in hal_jpege_vepu540c_status_check() local
318 hal_jpege_dbg_detail("hw_status: 0x%08x", hw_status.val); in hal_jpege_vepu540c_status_check()
319 if (hw_status.int_sta.enc_done_sta) in hal_jpege_vepu540c_status_check()
322 if (hw_status.int_sta.wdg_sta) in hal_jpege_vepu540c_status_check()
325 if (hw_status.int_sta.jslc_done_sta) in hal_jpege_vepu540c_status_check()
328 if (hw_status.int_sta.jbsf_oflw_sta) in hal_jpege_vepu540c_status_check()
H A Dhal_jpege_vepu511.c521 cfg1.reg = &reg_out->hw_status; in hal_jpege_vepu511_start()
554 RK_U32 hw_status = elem->hw_status; in hal_jpege_vepu511_status_check() local
556 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH) in hal_jpege_vepu511_status_check()
559 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH) in hal_jpege_vepu511_status_check()
562 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH) in hal_jpege_vepu511_status_check()
565 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW) in hal_jpege_vepu511_status_check()
568 if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL) in hal_jpege_vepu511_status_check()
571 if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR) in hal_jpege_vepu511_status_check()
574 if (hw_status & RKV_ENC_INT_BUS_READ_ERROR) in hal_jpege_vepu511_status_check()
577 if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR) in hal_jpege_vepu511_status_check()
H A Dhal_jpege_vepu511_reg.h380 RK_U32 hw_status; member
H A Dhal_jpege_vepu540c_reg.h854 vepu540c_hw_status hw_status; member
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu540c.c49 vepu540c_hw_status hw_status; member
1424 cfg1.reg = &reg_out->hw_status; in hal_h265e_v540c_start()
1461 vepu540c_hw_status hw_status = elem->hw_status; in vepu540c_h265_set_feedback() local
1472 fb->hw_status = hw_status; in vepu540c_h265_set_feedback()
1473 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status.val); in vepu540c_h265_set_feedback()
1474 if (hw_status.int_sta.enc_done_sta) in vepu540c_h265_set_feedback()
1477 if (hw_status.int_sta.lkt_node_done_sta) in vepu540c_h265_set_feedback()
1480 if (hw_status.int_sta.sclr_done_sta) in vepu540c_h265_set_feedback()
1483 if (hw_status.int_sta.vslc_done_sta) in vepu540c_h265_set_feedback()
1486 if (hw_status.int_sta.vbsf_oflw_sta) in vepu540c_h265_set_feedback()
[all …]
H A Dhal_h265e_vepu541.c51 RK_U32 hw_status; /* 0:corret, 1:error */ member
1717 cfg1.reg = &reg_out->hw_status; in hal_h265e_v540_start()
1810 cfg1.reg = &reg_out->hw_status; in hal_h265e_v541_start()
1869 RK_U32 hw_status = elem->hw_status; in vepu541_h265_set_feedback() local
1875 fb->hw_status = hw_status; in vepu541_h265_set_feedback()
1876 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status); in vepu541_h265_set_feedback()
1877 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH) in vepu541_h265_set_feedback()
1880 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH) in vepu541_h265_set_feedback()
1883 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH) in vepu541_h265_set_feedback()
1886 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH) in vepu541_h265_set_feedback()
[all …]
H A Dhal_h265e_vepu580.c56 RK_U32 hw_status; /* 0:corret, 1:error */ member
2264 cfg1.reg = &reg_out->hw_status; in hal_h265e_v580_send_regs()
3000 RK_U32 hw_status = elem->hw_status; in vepu580_h265_set_feedback() local
3009 fb->hw_status = hw_status; in vepu580_h265_set_feedback()
3010 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status); in vepu580_h265_set_feedback()
3011 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH) in vepu580_h265_set_feedback()
3014 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH) in vepu580_h265_set_feedback()
3017 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH) in vepu580_h265_set_feedback()
3020 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH) in vepu580_h265_set_feedback()
3023 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW) in vepu580_h265_set_feedback()
[all …]
H A Dhal_h265e_vepu510.c40 RK_U32 hw_status; /* 0:corret, 1:error */ member
2193 cfg1.reg = &reg_out->hw_status; in hal_h265e_v510_start()
2230 RK_U32 hw_status = elem->hw_status; in vepu510_h265_set_feedback() local
2239 fb->hw_status = hw_status; in vepu510_h265_set_feedback()
2240 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status); in vepu510_h265_set_feedback()
2241 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH) in vepu510_h265_set_feedback()
2244 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH) in vepu510_h265_set_feedback()
2247 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH) in vepu510_h265_set_feedback()
2250 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH) in vepu510_h265_set_feedback()
2253 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW) in vepu510_h265_set_feedback()
[all …]
H A Dhal_h265e_vepu511.c41 RK_U32 hw_status; /* 0:corret, 1:error */ member
2385 cfg1.reg = &reg_out->hw_status; in hal_h265e_vepu511_start()
2422 RK_U32 hw_status = elem->hw_status; in vepu511_h265_set_feedback() local
2431 fb->hw_status = hw_status; in vepu511_h265_set_feedback()
2432 hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status); in vepu511_h265_set_feedback()
2433 if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH) in vepu511_h265_set_feedback()
2436 if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH) in vepu511_h265_set_feedback()
2439 if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH) in vepu511_h265_set_feedback()
2442 if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH) in vepu511_h265_set_feedback()
2445 if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW) in vepu511_h265_set_feedback()
[all …]
H A Dhal_h265e_vepu510_reg.h818 RK_U32 hw_status; member
H A Dhal_h265e_vepu541_reg.h899 RK_U32 hw_status; member
H A Dhal_h265e_vepu540c_reg.h1081 vepu540c_hw_status hw_status; member
H A Dhal_h265e_vepu511_reg.h1571 RK_U32 hw_status; member
H A Dhal_h265e_vepu580_reg.h3264 RK_U32 hw_status; member
/rockchip-linux_mpp/mpp/common/
H A Djpege_syntax.h114 RK_U32 hw_status; /* zero -> correct; non-zero -> error */ member
H A Dvp8e_syntax.h38 RK_U32 hw_status; /* 0:corret, 1:error */ member
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c1695 rd_cfg.reg = &ctx->regs_ret.hw_status; in hal_h264e_vepu541_start()
1733 if (regs_ret->hw_status.lkt_done_sta) in hal_h264e_vepu541_status_check()
1736 if (regs_ret->hw_status.enc_done_sta) in hal_h264e_vepu541_status_check()
1739 if (regs_ret->hw_status.enc_slice_done_sta) in hal_h264e_vepu541_status_check()
1742 if (regs_ret->hw_status.sclr_done_sta) in hal_h264e_vepu541_status_check()
1745 if (regs_ret->hw_status.oflw_done_sta) in hal_h264e_vepu541_status_check()
1748 if (regs_ret->hw_status.brsp_done_sta) in hal_h264e_vepu541_status_check()
1751 if (regs_ret->hw_status.berr_done_sta) in hal_h264e_vepu541_status_check()
1754 if (regs_ret->hw_status.rerr_done_sta) in hal_h264e_vepu541_status_check()
1757 if (regs_ret->hw_status.wdg_done_sta) in hal_h264e_vepu541_status_check()
H A Dhal_h264e_vepu541_reg.h2213 } hw_status; /* reg007 */ member
/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu_v2.h165 RK_U32 hw_status; member
H A Dhal_h264e_vepu1_v2.c635 mb_rc->hw_status = reg_val[VEPU_REG_INTERRUPT / 4]; in h264e_vepu1_get_mbrc()
H A Dhal_h264e_vepu2_v2.c700 mb_rc->hw_status = reg_val[VEPU_REG_INTERRUPT / 4]; in h264e_vepu2_get_mbrc()
/rockchip-linux_mpp/mpp/hal/vpu/jpege/
H A Dhal_jpege_vepu2_v2.c764 feedback->hw_status = val & 0x70; in multi_core_wait()
782 feedback->hw_status = val & 0x70; in multi_core_wait()
879 feedback->hw_status = val & 0x70; in hal_jpege_vepu2_wait()
H A Dhal_jpege_vepu1_v2.c448 feedback->hw_status = val & 0x70; in hal_jpege_vepu1_wait()
/rockchip-linux_mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_vepu1_v2.c463 fb->hw_status = regs->sw1.val & HW_STATUS_MASK; in hal_vp8e_vepu1_wait_v2()
H A Dhal_vp8e_vepu2_v2.c466 fb->hw_status = regs->sw109.val & HW_STATUS_MASK; in hal_vp8e_vepu2_wait_v2()

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