51     RK_U32 hw_status; /* 0:corret, 1:error */  member
1717         cfg1.reg = &reg_out->hw_status;  in hal_h265e_v540_start()
1810         cfg1.reg = &reg_out->hw_status;  in hal_h265e_v541_start()
1869     RK_U32 hw_status = elem->hw_status;  in vepu541_h265_set_feedback()  local
1875     fb->hw_status = hw_status;  in vepu541_h265_set_feedback()
1876     hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);  in vepu541_h265_set_feedback()
1877     if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)  in vepu541_h265_set_feedback()
1880     if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)  in vepu541_h265_set_feedback()
1883     if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)  in vepu541_h265_set_feedback()
1886     if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)  in vepu541_h265_set_feedback()
1889     if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)  in vepu541_h265_set_feedback()
1892     if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)  in vepu541_h265_set_feedback()
1895     if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)  in vepu541_h265_set_feedback()
1898     if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)  in vepu541_h265_set_feedback()
1901     if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)  in vepu541_h265_set_feedback()
1969         mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);  in hal_h265e_v541_wait()