| /rk3399_rockchip-uboot/drivers/clk/at91/ |
| H A D | clk-generated.c | 84 u32 div, best_div = 0; in generic_clk_set_rate() local
109 best_div = div - 1; in generic_clk_set_rate()
123 best_parent.dev->name, best_rate, best_div); in generic_clk_set_rate()
134 AT91_PMC_PCR_GCKDIV_(best_div) | in generic_clk_set_rate()
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3368.c | 143 struct pll_div *best_div = NULL; in pll_para_config() local
163 best_div = rkclk_get_pll_config(freq_hz * (*ext_div)); in pll_para_config()
164 if (best_div) { in pll_para_config()
165 div->nr = best_div->nr; in pll_para_config()
166 div->nf = best_div->nf; in pll_para_config()
167 div->no = best_div->no; in pll_para_config()
168 div->nb = best_div->nb; in pll_para_config()
337 u32 *best_div) in rk3368_mmc_find_best_rate_and_parent() argument
376 *best_div = div - 1; in rk3368_mmc_find_best_rate_and_parent()
380 __func__, *best_mux, *best_div, best_rate); in rk3368_mmc_find_best_rate_and_parent()
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| H A D | clk_rk3576.c | 1177 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; in rk3576_dclk_vop_set_clk() local
1263 best_div = div; in rk3576_dclk_vop_set_clk()
1267 pll_rate, best_rate, best_div, best_sel); in rk3576_dclk_vop_set_clk()
1274 (best_div - 1) << div_shift); in rk3576_dclk_vop_set_clk()
1319 u32 i, con, div, best_div = 0, best_sel = 0; in rk3576_clk_csihost_set_clk() local
1363 best_div = div; in rk3576_clk_csihost_set_clk()
1367 pll_rate, best_rate, best_div, best_sel); in rk3576_clk_csihost_set_clk()
1373 (best_div - 1) << div_shift); in rk3576_clk_csihost_set_clk()
1437 u32 i, con, sel, div, best_div = 0, best_sel = 0; in rk3576_dclk_ebc_set_clk() local
1503 best_div = div; in rk3576_dclk_ebc_set_clk()
[all …]
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| H A D | clk_rk3288.c | 357 struct pll_div *best_div = NULL; in pll_para_config() local
377 best_div = rkclk_get_pll_config(freq_hz * (*ext_div)); in pll_para_config()
378 if (best_div) { in pll_para_config()
379 div->nr = best_div->nr; in pll_para_config()
380 div->nf = best_div->nf; in pll_para_config()
381 div->no = best_div->no; in pll_para_config()
382 div->nb = best_div->nb; in pll_para_config()
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| H A D | clk_rk3308.c | 565 u32 i, div, best_div = 0, best_sel = 0; in rk3308_vop_set_clk() local
589 best_div = div; in rk3308_vop_set_clk()
593 pll_rate, best_rate, best_div, best_sel); in rk3308_vop_set_clk()
606 (best_div - 1) << DCLK_VOP_DIV_SHIFT); in rk3308_vop_set_clk()
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| H A D | clk_rk3562.c | 1177 u32 i, div, sel, best_div = 0, best_sel = 0; in rk3562_vop_set_rate() local
1235 best_div = div; in rk3562_vop_set_rate()
1239 pll_rate, best_rate, best_div, best_sel); in rk3562_vop_set_rate()
1245 (best_div - 1) << DCLK_VOP1_DIV_SHIFT); in rk3562_vop_set_rate()
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| H A D | clk_rv1126.c | 1224 u32 i, div, best_div = 0, best_sel = 0; in rv1126_dclk_vop_set_clk() local
1245 best_div = div; in rv1126_dclk_vop_set_clk()
1249 pll_rate, best_rate, best_div, best_sel); in rv1126_dclk_vop_set_clk()
1256 (best_div - 1) << DCLK_VOP_DIV_SHIFT); in rv1126_dclk_vop_set_clk()
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| H A D | clk_rk3588.c | 1114 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; in rk3588_dclk_vop_set_clk() local
1203 best_div = div; in rk3588_dclk_vop_set_clk()
1207 pll_rate, best_rate, best_div, best_sel); in rk3588_dclk_vop_set_clk()
1214 (best_div - 1) << div_shift); in rk3588_dclk_vop_set_clk()
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| H A D | clk_rk3568.c | 1825 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; in rk3568_dclk_vop_set_clk() local
1884 best_div = div; in rk3568_dclk_vop_set_clk()
1888 pll_rate, best_rate, best_div, best_sel); in rk3568_dclk_vop_set_clk()
1895 (best_div - 1) << DCLK0_VOP_DIV_SHIFT); in rk3568_dclk_vop_set_clk()
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